forked from rpms/kernel
		
	Try turning off the MLX configs which seem to generate bad divisions?
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				| @ -1 +1 @@ | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
|  | ||||
| @ -1 +1 @@ | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
|  | ||||
| @ -3048,8 +3048,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3028,8 +3028,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3251,8 +3251,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3105,8 +3105,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3085,8 +3085,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3231,8 +3231,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2949,8 +2949,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_INFINIBAND is not set | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2969,8 +2969,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_INFINIBAND is not set | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2969,8 +2969,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_INFINIBAND is not set | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2949,8 +2949,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| # CONFIG_MLX5_INFINIBAND is not set | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2811,8 +2811,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2790,8 +2790,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2757,8 +2757,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2736,8 +2736,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2756,8 +2756,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2735,8 +2735,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2694,8 +2694,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2673,8 +2673,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -3011,8 +3011,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
| @ -2991,8 +2991,8 @@ CONFIG_MLX5_CORE_EN_DCB=y | ||||
| CONFIG_MLX5_CORE_EN=y | ||||
| CONFIG_MLX5_CORE_IPOIB=y | ||||
| CONFIG_MLX5_CORE=m | ||||
| CONFIG_MLX5_EN_IPSEC=y | ||||
| CONFIG_MLX5_FPGA=y | ||||
| # CONFIG_MLX5_EN_IPSEC is not set | ||||
| # CONFIG_MLX5_FPGA is not set | ||||
| CONFIG_MLX5_INFINIBAND=m | ||||
| # CONFIG_MLX90614 is not set | ||||
| CONFIG_MLX_CPLD_PLATFORM=m | ||||
|  | ||||
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