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Linux v5.6-11374-ga10c9c710f9e

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Justin M. Forbes 2020-04-06 13:56:22 -05:00
parent 2703d9b16c
commit 0561e0bf0e
48 changed files with 158 additions and 3978 deletions
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168
ARM-dts-bcm2711-Move-emmc2-into-its-own-bus.patch
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@ -1,168 +0,0 @@
From patchwork Wed Mar 4 13:24:37 2020
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: Rob Herring <robh+dt@kernel.org>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Subject: [PATCH v2] ARM: dts: bcm2711: Move emmc2 into its own bus
Date: Wed, 4 Mar 2020 14:24:37 +0100
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Cc: devicetree@vger.kernel.org, f.fainelli@gmail.com, phil@raspberrypi.org,
linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com,
linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org
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Depending on bcm2711's revision its emmc2 controller might have
different DMA constraints. Raspberry Pi 4's firmware will take care of
updating those, but only if a certain alias is found in the device tree.
So, move emmc2 into its own bus, so as not to pollute other devices with
dma-ranges changes and create the emmc2bus alias.
Based in Phil ELwell's downstream implementation.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v1:
- Add comment in dt
- Fix commit title
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 1 +
arch/arm/boot/dts/bcm2711.dtsi | 25 ++++++++++++++++++++-----
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 1d4b589fe233..e26ea9006378 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -20,6 +20,7 @@ memory@0 {
};
aliases {
+ emmc2bus = &emmc2bus;
ethernet0 = &genet;
pcie0 = &pcie0;
};
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index d1e684d0acfd..a91cf68e3c4c 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -241,17 +241,32 @@ pwm1: pwm@7e20c800 {
status = "disabled";
};
+ hvs@7e400000 {
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ /*
+ * emmc2 has different DMA constraints based on SoC revisions. It was
+ * moved into its own bus, so as for RPi4's firmware to update them.
+ * The firmware will find whether the emmc2bus alias is defined, and if
+ * so, it'll edit the dma-ranges property below accordingly.
+ */
+ emmc2bus: emmc2bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
+ dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
+
emmc2: emmc2@7e340000 {
compatible = "brcm,bcm2711-emmc2";
- reg = <0x7e340000 0x100>;
+ reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2711_CLOCK_EMMC2>;
status = "disabled";
};
-
- hvs@7e400000 {
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- };
};
arm-pmu {

477
ARM64-Tegra-fixes.patch
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@ -1,477 +0,0 @@
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Subject: [PATCH 1/4] ARM64: Tegra: Enable I2C controller for EEPROM
Date: Mon, 24 Feb 2020 14:34:33 +0000
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Commit a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1
module") populated the EEPROM on the Jetson TX1 module, but did not
enable the corresponding I2C controller. Enable the I2C controller so
that this EEPROM can be accessed.
Fixes: a5b6b67364cb ("arm64: tegra: Add ID EEPROM for Jetson TX1 module")
Cc: <stable@vger.kernel.org>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index cb58f79deb48..95b1a6e76e6e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -265,6 +265,8 @@
};
i2c@7000c500 {
+ status = "okay";
+
/* module ID EEPROM */
eeprom@50 {
compatible = "atmel,24c02";
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From: Jon Hunter <jonathanh@nvidia.com>
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CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Jon Hunter <jonathanh@nvidia.com>
Subject: [PATCH 2/4] ARM64: tegra: Add EEPROM supplies
Date: Mon, 24 Feb 2020 14:34:34 +0000
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The following warning is observed on Jetson TX1, Jetson Nano and Jetson
TX2 platforms because the supply regulators are not specified for the
EEPROMs.
WARNING KERN at24 0-0050: 0-0050 supply vcc not found, using dummy regulator
WARNING KERN at24 0-0057: 0-0057 supply vcc not found, using dummy regulator
For both of these platforms the EEPROM is powered by the main 1.8V
supply rail and so populate the supply for these devices to fix these
warnings.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 1 +
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 +
arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 ++
5 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index d7628f5afb85..961b1be0c56b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -226,6 +226,7 @@
compatible = "atmel,24c02";
reg = <0x57>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index 947744d0f04c..da96de04d003 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -171,6 +171,7 @@
compatible = "atmel,24c02";
reg = <0x50>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 95b1a6e76e6e..f87d2437d11c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -272,6 +272,7 @@
compatible = "atmel,24c02";
reg = <0x50>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index a3cafe39ba4c..c70a610f8e3a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -85,6 +85,7 @@
compatible = "atmel,24c02";
reg = <0x57>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 848afd855da6..21ed1756b889 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -114,6 +114,7 @@
compatible = "atmel,24c02";
reg = <0x50>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
@@ -124,6 +125,7 @@
compatible = "atmel,24c02";
reg = <0x57>;
+ vcc-supply = <&vdd_1v8>;
address-bits = <8>;
page-size = <8>;
size = <256>;
From patchwork Mon Feb 24 14:34:35 2020
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From: Jon Hunter <jonathanh@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Jon Hunter <jonathanh@nvidia.com>, <stable@vger.kernel.org>
Subject: [PATCH 3/4] ARM64: tegra: Fix Tegra186 SOR supply
Date: Mon, 24 Feb 2020 14:34:35 +0000
Message-ID: <20200224143436.5438-3-jonathanh@nvidia.com>
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The following warning is observed on the Jetson TX2 platform ...
WARNING KERN tegra-sor 15540000.sor: 15540000.sor supply \
vdd-hdmi-dp-pll not found, using dummy regulator
The problem is caused because the regulator for the SOR device is
missing the '-supply' suffix in Device-Tree. Therefore, add the
'-supply' suffix to fix this warning.
Fixes: 3fdfaf8718fa arm64: tegra: Enable DP support on Jetson TX2
Cc: <stable@vger.kernel.org>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
index 961b1be0c56b..1af7f9ffb7b6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts
@@ -278,7 +278,7 @@
status = "okay";
avdd-io-hdmi-dp-supply = <&vdd_hdmi_1v05>;
- vdd-hdmi-dp-pll = <&vdd_1v8_ap>;
+ vdd-hdmi-dp-pll-supply = <&vdd_1v8_ap>;
nvidia,dpaux = <&dpaux>;
};
From patchwork Mon Feb 24 14:34:36 2020
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CC: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
Jon Hunter <jonathanh@nvidia.com>
Subject: [PATCH 4/4] ARM64: tegra: Populate LP8557 backlight regulator
Date: Mon, 24 Feb 2020 14:34:36 +0000
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The following warning is observed on Jetson TX1 platform because the
supply regulator is not specified for the backlight.
WARNING KERN lp855x 0-002c: 0-002c supply power not found, using dummy regulator
The backlight supply is provided by the 3.3V SYS rail and so add this
as the supply for the backlight.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
index c70a610f8e3a..ea0e1efa6973 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts
@@ -56,6 +56,7 @@
backlight: backlight@2c {
compatible = "ti,lp8557";
reg = <0x2c>;
+ power-supply = <&vdd_3v3_sys>;
dev-ctrl = /bits/ 8 <0x80>;
init-brt = /bits/ 8 <0xff>;

1360
Add-support-for-the-pine64-Pinebook-Pro.patch
View File

File diff suppressed because it is too large Load Diff

69
arm64-a64-mbus.patch
View File

@ -1,69 +0,0 @@
From daae9f66b29a04a94708b1b5a9b61e3ee14df031 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Mon, 10 Feb 2020 18:06:52 +0100
Subject: [PATCH 1/2] dt-bindings: interconnect: sunxi: Add A64 MBUS compatible
A64 contains MBUS controller. Add a compatible for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
index 9370e64992dd..aa0738b4d534 100644
--- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
@@ -30,6 +30,7 @@ properties:
enum:
- allwinner,sun5i-a13-mbus
- allwinner,sun8i-h3-mbus
+ - allwinner,sun50i-a64-mbus
reg:
maxItems: 1
--
2.24.1
From 410bb2be7e1f1d329c238e2d6d06b6c25dcee404 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Mon, 10 Feb 2020 18:06:54 +0100
Subject: [PATCH 2/2] arm64: dts: allwinner: a64: Add MBUS controller node
A64 contains MBUS, which is the bus used by DMA devices to access
system memory.
MBUS controller is responsible for arbitration between channels based
on set priority and can do some other things as well, like report
bandwidth used. It also maps RAM region to different address than CPU.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 862b47dc9dc9..251c91724de1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 {
status = "disabled";
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun50i-a64-mbus";
+ reg = <0x01c62000 0x1000>;
+ clocks = <&ccu 112>;
+ dma-ranges = <0x00000000 0x40000000 0xc0000000>;
+ #interconnect-cells = <1>;
+ };
+
csi: csi@1cb0000 {
compatible = "allwinner,sun50i-a64-csi";
reg = <0x01cb0000 0x1000>;
--
2.24.1

200
arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch
View File

@ -1,200 +0,0 @@
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From: Alifer Moraes <alifer.wsdm@gmail.com>
To: robh+dt@kernel.org
Subject: [PATCH] arm64: dts: imx8mq-phanbell: Add support for ethernet
Date: Tue, 11 Feb 2020 10:48:28 -0300
Message-Id: <20200211134828.138-1-alifer.wsdm@gmail.com>
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Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, festevam@gmail.com,
s.hauer@pengutronix.de, linux-kernel@vger.kernel.org,
Alifer Moraes <alifer.wsdm@gmail.com>, marco.franchi@nxp.com,
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Add support for ethernet on Google's i.MX 8MQ Phanbell
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
---
.../boot/dts/freescale/imx8mq-phanbell.dts | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 3f2a489a4ad8..16ed13c44a47 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -201,6 +201,27 @@
};
};
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <30>;
+ phy-handle = <&ethphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+ };
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -254,6 +275,26 @@
};
&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f

568
arm64-pine64-pinephone.patch
View File

@ -1,568 +0,0 @@
From 836821a0addbd8589e949801aaa7be244703c7f8 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 27 Feb 2020 02:26:48 +0100
Subject: [PATCH 1/3] arm64: dts: sun50i-a64: Add i2c2 pins
PinePhone needs I2C2 pins description. Add it, and make it default
for i2c2, since it's the only possiblilty.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 862b47dc9dc9..107a48f9c5b3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -671,6 +671,11 @@ i2c1_pins: i2c1-pins {
function = "i2c1";
};
+ i2c2_pins: i2c2-pins {
+ pins = "PE14", "PE15";
+ function = "i2c2";
+ };
+
/omit-if-no-ref/
lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD0", "PD1", "PD2", "PD3", "PD4",
@@ -958,12 +963,13 @@ i2c2: i2c@1c2b400 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
-
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.24.1
From 5c4e2cd9e8b600cc622c10543f69fcd897557eee Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 27 Feb 2020 02:26:49 +0100
Subject: [PATCH 2/3] dt-bindings: arm: sunxi: Add PinePhone 1.0 and 1.1
bindings
Document board compatible names for Pine64 PinePhone:
- 1.0 - Developer variant
- 1.1 - Braveheart variant
Signed-off-by: Ondrej Jirman <megous@megous.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 159060b65c5d..c632252be48b 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -636,6 +636,16 @@ properties:
- const: pine64,pinebook
- const: allwinner,sun50i-a64
+ - description: Pine64 PinePhone Developer Batch (1.0)
+ items:
+ - const: pine64,pinephone-1.0
+ - const: allwinner,sun50i-a64
+
+ - description: Pine64 PinePhone Braveheart (1.1)
+ items:
+ - const: pine64,pinephone-1.1
+ - const: allwinner,sun50i-a64
+
- description: Pine64 PineTab
items:
- const: pine64,pinetab
--
2.24.1
From 697f60799172569e8d502a44ad98994f2c48778c Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megous@megous.com>
Date: Thu, 27 Feb 2020 02:26:50 +0100
Subject: [PATCH 3/3] arm64: dts: allwinner: Add initial support for Pine64
PinePhone
At the moment PinePhone comes in two slightly incompatible variants:
- 1.0: Early Developer Batch
- 1.1: Braveheart Batch
There will be at least one more incompatible variant in the very near
future, so let's start by sharing the dtsi among multiple variants,
right away, even though the HW description doesn't yet include the
different bits.
The differences between 1.0 and 1.1 are: change in pins that control
the flash LED, differences in modem power status signal routing, and
maybe some other subtler things, that have not been determined yet.
This is a basic DT that includes only features that are already
supported by mainline drivers.
Co-developed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Co-developed-by: Martijn Braam <martijn@brixit.nl>
Signed-off-by: Martijn Braam <martijn@brixit.nl>
Co-developed-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Bhushan Shah <bshah@kde.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun50i-a64-pinephone-1.0.dts | 11 +
.../allwinner/sun50i-a64-pinephone-1.1.dts | 11 +
.../dts/allwinner/sun50i-a64-pinephone.dtsi | 379 ++++++++++++++++++
4 files changed, 403 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 6dad63881cd3..e4d3cd0ac5bb 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
new file mode 100644
index 000000000000..0c42272106af
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+ model = "Pine64 PinePhone Developer Batch (1.0)";
+ compatible = "pine64,pinephone-1.0", "allwinner,sun50i-a64";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
new file mode 100644
index 000000000000..06a775c41664
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-a64-pinephone.dtsi"
+
+/ {
+ model = "Pine64 PinePhone Braveheart (1.1)";
+ compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
new file mode 100644
index 000000000000..cefda145c3c9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
+// Copyright (C) 2020 Martijn Braam <martijn@brixit.nl>
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+
+#include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ blue {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ };
+
+ green {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
+ };
+
+ red {
+ function = LED_FUNCTION_INDICATOR;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ };
+ };
+
+ speaker_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ vibrator {
+ compatible = "gpio-vibrator";
+ enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ vcc-supply = <&reg_dcdc1>;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&codec_analog {
+ cpvdd-supply = <&reg_eldo1>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&dai {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* Magnetometer */
+ lis3mdl@1e {
+ compatible = "st,lis3mdl-magn";
+ reg = <0x1e>;
+ vdd-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_dldo1>;
+ };
+
+ /* Accelerometer/gyroscope */
+ mpu6050@68 {
+ compatible = "invensense,mpu6050";
+ reg = <0x68>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */
+ vdd-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_dldo1>;
+ };
+};
+
+/* Connected to pogo pins (external spring based pinheader for user addons) */
+&i2c2 {
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_aldo3>;
+ status = "okay";
+
+ button-200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button-400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <&reg_dcdc1>;
+ vcc-pc-supply = <&reg_dcdc1>;
+ vcc-pd-supply = <&reg_dcdc1>;
+ vcc-pe-supply = <&reg_aldo1>;
+ vcc-pf-supply = <&reg_dcdc1>;
+ vcc-pg-supply = <&reg_dldo4>;
+ vcc-ph-supply = <&reg_dcdc1>;
+};
+
+&r_pio {
+ /*
+ * FIXME: We can't add that supply for now since it would
+ * create a circular dependency between pinctrl, the regulator
+ * and the RSB Bus.
+ *
+ * vcc-pl-supply = <&reg_aldo2>;
+ */
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp803.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&reg_aldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dovdd-csi";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-dsi-sensor";
+};
+
+&reg_dldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-mipi-io";
+};
+
+&reg_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+&reg_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-lpddr";
+};
+
+&reg_eldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-1v8-csi";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-lcd-ctp-stk";
+ status = "okay";
+};
+
+&reg_ldo_io1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-1v8-typec";
+ status = "okay";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&sound {
+ status = "okay";
+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ simple-audio-card,widgets = "Microphone", "Headset Microphone",
+ "Microphone", "Internal Microphone",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Internal Earpiece",
+ "Speaker", "Internal Speaker";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP",
+ "Internal Earpiece", "EARPIECE",
+ "Internal Speaker", "Speaker Amp OUTL",
+ "Internal Speaker", "Speaker Amp OUTR",
+ "Speaker Amp INL", "LINEOUT",
+ "Speaker Amp INR", "LINEOUT",
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "AIF1 Slot 0 Left ADC", "Left ADC",
+ "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Internal Microphone", "MBIAS",
+ "MIC1", "Internal Microphone",
+ "Headset Microphone", "HBIAS",
+ "MIC2", "Headset Microphone";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+/* Connected to the modem (hardware flow control can't be used) */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.24.1

583
arm64-pine64-pinetab.patch
View File

@ -1,583 +0,0 @@
From e15d9c7cb74033f668c19a65abfd77ed7331f91e Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Thu, 16 Jan 2020 11:36:35 +0800
Subject: [PATCH 1/2] dt-bindings: arm: sunxi: add binding for PineTab tablet
Add the device tree binding for Pine64's PineTab tablet, which uses
Allwinner A64 SoC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 327ce6730823..159060b65c5d 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -636,6 +636,11 @@ properties:
- const: pine64,pinebook
- const: allwinner,sun50i-a64
+ - description: Pine64 PineTab
+ items:
+ - const: pine64,pinetab
+ - const: allwinner,sun50i-a64
+
- description: Pine64 SoPine Baseboard
items:
- const: pine64,sopine-baseboard
--
2.24.1
From d7b56d337bb980f0b996958ec6808253c4f50771 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Thu, 16 Jan 2020 11:36:36 +0800
Subject: [PATCH 2/2] arm64: dts: allwinner: a64: add support for PineTab
PineTab is a 10.1" tablet by Pine64 with Allwinner A64 inside.
It includes the following peripherals:
USB:
- A microUSB Type-B port connected to the OTG-capable USB PHY of
Allwinner A64. The ID pin is connected to a GPIO of the A64 SoC, and the
Vbus is connected to the Vbus of AXP803 PMIC. These enables OTG
functionality on this port.
- A USB Type-A port is connected to the internal hub attached to the
non-OTG USB PHY of Allwinner A64.
- There are reserved pins for an external keyboard connected to the
internal hub.
Power:
- The microUSB port has its Vbus connected to AXP803, mentioned above.
- A DC jack (of a strange size, 2.5mm outer diameter) is connected to
the ACIN of AXP803.
- A Li-Polymer battery is connected to the battery pins of AXP803.
Storage:
- An tradition Pine64 eMMC slot is on the board, mounted with an eMMC
module by factory.
- An external microSD slot is hidden under a protect case.
Display:
- A MIPI-DSI LCD panel (800x1280) is connected to the DSI port of A64 SoC.
- A mini HDMI port.
Input:
- A touch panel attached to a Goodix GT9271 touch controller.
- Volume keys connected to the LRADC of the A64 SoC.
Camera:
- An OV5640 CMOS camera is at rear, connected to the CSI bus of A64 SoC.
- A GC2145 CMOS camera is at front, shares the same CSI bus with OV5640.
Audio:
- A headphone jack is conencted to the SoC's internal codec.
- A speaker connected is to the Line Out port of SoC's internal codec, via
an amplifier.
Misc:
- Debug UART is muxed with the headphone jack, with the switch next to
the microSD slot.
- A bosch BMA223 accelerometer is connected to the I2C bus of A64 SoC.
- Wi-Fi and Bluetooth are available via a RTL8723CS chip, similar to the
one in Pinebook.
This commit adds a basically usable device tree for it, implementing
most of the features mentioned above. HDMI is not supported now because
bad LCD-HDMI coexistence situation of mainline A64 display driver, the
front camera currently lacks a driver and a facility to share the bus
with the rear one, and the accelerometer currently lacks a DT binding.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-a64-pinetab.dts | 460 ++++++++++++++++++
2 files changed, 461 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index cf4f78617c3f..6dad63881cd3 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
new file mode 100644
index 000000000000..316e8a443913
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
@@ -0,0 +1,460 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "PineTab";
+ compatible = "pine64,pinetab", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &rtl8723cs;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ brightness-levels = <0 16 18 20 22 24 26 29 32 35 38 42 46 51 56 62 68 75 83 91 100>;
+ default-brightness-level = <15>;
+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+ power-supply = <&vdd_bl>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ i2c-csi {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */
+ scl-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
+ i2c-gpio,delay-us = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Rear camera */
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_mclk_pin>;
+ clocks = <&ccu CLK_CSI_MCLK>;
+ clock-names = "xclk";
+
+ AVDD-supply = <&reg_dldo3>;
+ DOVDD-supply = <&reg_aldo1>;
+ DVDD-supply = <&reg_eldo3>;
+ reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
+ powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
+
+ port {
+ ov5640_ep: endpoint {
+ remote-endpoint = <&csi_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+ };
+ };
+
+ speaker_amp: audio-amplifier {
+ compatible = "simple-audio-amplifier";
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ sound-name-prefix = "Speaker Amp";
+ };
+
+ vdd_bl: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "bl-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ enable-active-high;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&codec {
+ status = "okay";
+};
+
+&codec_analog {
+ hpvcc-supply = <&reg_eldo1>;
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&csi {
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_ep: endpoint {
+ remote-endpoint = <&ov5640_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+ data-active = <1>; /* Active high */
+ pclk-sample = <1>; /* Rising */
+ };
+ };
+};
+
+&dai {
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&dphy {
+ status = "okay";
+};
+
+&dsi {
+ vcc-dsi-supply = <&reg_dldo1>;
+ status = "okay";
+
+ panel@0 {
+ compatible = "feixin,k101-im2ba02";
+ reg = <0>;
+ avdd-supply = <&reg_dc1sw>;
+ dvdd-supply = <&reg_dc1sw>;
+ cvdd-supply = <&reg_ldo_io1>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ backlight = <&backlight>;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt9271";
+ reg = <0x5d>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */
+ irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ reset-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ AVDD28-supply = <&reg_ldo_io1>;
+ };
+};
+
+&i2c0_pins {
+ bias-pull-up;
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* TODO: add Bochs BMA223 accelerometer here */
+};
+
+&lradc {
+ vref-supply = <&reg_aldo3>;
+ status = "okay";
+
+ button-200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button-400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mixer1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <&reg_dldo4>;
+ vqmmc-supply = <&reg_eldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723cs: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic@3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en;
+ };
+};
+
+#include "axp803.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&reg_aldo1 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "dovdd-csi";
+};
+
+&reg_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+&reg_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+&reg_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+&reg_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+&reg_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+&reg_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi-dsi-sensor";
+};
+
+&reg_dldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "avdd-csi";
+};
+
+&reg_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
+&reg_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+&reg_eldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca-1v8";
+};
+
+&reg_eldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "dvdd-1v8-csi";
+};
+
+&reg_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+&reg_ldo_io0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-usb";
+ status = "okay";
+};
+
+&reg_ldo_io1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <3500000>;
+ regulator-name = "vcc-touchscreen";
+ status = "okay";
+};
+
+&reg_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&sound {
+ status = "okay";
+ simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
+ "Microphone", "Internal Microphone Right",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Internal Speaker";
+ simple-audio-card,routing =
+ "Left DAC", "AIF1 Slot 0 Left",
+ "Right DAC", "AIF1 Slot 0 Right",
+ "Speaker Amp INL", "LINEOUT",
+ "Speaker Amp INR", "LINEOUT",
+ "Internal Speaker", "Speaker Amp OUTL",
+ "Internal Speaker", "Speaker Amp OUTR",
+ "Headphone Jack", "HP",
+ "AIF1 Slot 0 Left ADC", "Left ADC",
+ "AIF1 Slot 0 Right ADC", "Right ADC",
+ "Internal Microphone Left", "MBIAS",
+ "MIC1", "Internal Microphone Left",
+ "Internal Microphone Right", "HBIAS",
+ "MIC2", "Internal Microphone Right";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <&reg_drivevbus>;
+ usb1_vbus-supply = <&reg_ldo_io0>;
+ status = "okay";
+};
--
2.24.1

429
arm64-pinebook-fixes.patch
View File

@ -1,429 +0,0 @@
From e7a6e6b0c6506a9f070dbfb2ca948770c47a1d78 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:30:57 -0600
Subject: [PATCH 1/8] arm64: dts: allwinner: pinebook: Remove unused vcc3v3
regulator
This fixed regulator has no consumers, GPIOs, or other connections.
Remove it.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 3d894b208901..ff32ca1a495e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -63,13 +63,6 @@ lid_switch {
};
};
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
--
2.24.1
From 5eea216437eeff908d6d2942bf893fb77ebfc111 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:30:59 -0600
Subject: [PATCH 2/8] arm64: dts: allwinner: pinebook: Sort device tree nodes
The r_i2c node should come before r_rsb, and in any case should not
separate the axp803 node from its subnodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../boot/dts/allwinner/sun50i-a64-pinebook.dts | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index ff32ca1a495e..77784f7b1da7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -172,6 +172,14 @@ &pwm {
status = "okay";
};
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pl89_pins>;
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -183,14 +191,6 @@ axp803: pmic@3a3 {
};
};
-/* The ANX6345 eDP-bridge is on r_i2c */
-&r_i2c {
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&r_i2c_pl89_pins>;
- status = "okay";
-};
-
#include "axp803.dtsi"
&ac_power_supply {
--
2.24.1
From 4bdf53ffc64e5c6738c942dcdc422d5ca8a2070a Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:31:00 -0600
Subject: [PATCH 3/8] arm64: dts: allwinner: pinebook: Make simplefb more
consistent
Boards generally reference the simplefb nodes from the SoC dtsi by
label, not by full path. simplefb_hdmi is already like this in the
Pinebook DTS. Update simplefb_lcd to match.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 77784f7b1da7..224bed65d008 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -41,12 +41,6 @@ backlight: backlight {
chosen {
stdout-path = "serial0:115200n8";
-
- framebuffer-lcd {
- panel-supply = <&reg_dc1sw>;
- dvdd25-supply = <&reg_dldo2>;
- dvdd12-supply = <&reg_fldo1>;
- };
};
gpio_keys {
@@ -316,6 +310,12 @@ &reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
+&simplefb_lcd {
+ panel-supply = <&reg_dc1sw>;
+ dvdd25-supply = <&reg_dldo2>;
+ dvdd12-supply = <&reg_fldo1>;
+};
+
&simplefb_hdmi {
vcc-hdmi-supply = <&reg_dldo1>;
};
--
2.24.1
From c0f416de7141bbc713f080ad123b256f6320ec92 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:31:01 -0600
Subject: [PATCH 4/8] arm64: dts: allwinner: pinebook: Document MMC0 CD pin
name
Normally GPIO pin references are followed by a comment giving the pin
name for searchability. Add the comment here where it was missing.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 224bed65d008..a1e15777d524 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -119,7 +119,7 @@ &mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
disable-wp;
bus-width = <4>;
status = "okay";
--
2.24.1
From 8818d55ec31fa6e0dc14fb7a4924b3e8d3ecef7d Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:31:02 -0600
Subject: [PATCH 5/8] arm64: dts: allwinner: pinebook: Add GPIO port regulators
Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL.
VCC-PC and VCC-PG are supplied by ELDO1 at 1.8v.
VCC-PD is supplied by DCDC1 (VCC-IO) at 3.3v.
VCC-PE is supplied by ALDO1, and is unused.
VCC-PL creates a circular dependency, so it is omitted for now.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../boot/dts/allwinner/sun50i-a64-pinebook.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index a1e15777d524..1ec39120323f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -162,6 +162,13 @@ &ohci1 {
status = "okay";
};
+&pio {
+ vcc-pc-supply = <&reg_eldo1>;
+ vcc-pd-supply = <&reg_dcdc1>;
+ vcc-pe-supply = <&reg_aldo1>;
+ vcc-pg-supply = <&reg_eldo1>;
+};
+
&pwm {
status = "okay";
};
@@ -174,6 +181,16 @@ &r_i2c {
status = "okay";
};
+&r_pio {
+ /*
+ * FIXME: We can't add that supply for now since it would
+ * create a circular dependency between pinctrl, the regulator
+ * and the RSB Bus.
+ *
+ * vcc-pl-supply = <&reg_aldo2>;
+ */
+};
+
&r_rsb {
status = "okay";
--
2.24.1
From bd863f25d41173e140850772f9a02ffb3b3e0d6b Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:31:03 -0600
Subject: [PATCH 6/8] arm64: dts: allwinner: pinebook: Fix backlight regulator
The output from the backlight regulator is labeled as "VBKLT" in the
schematic. Using the equation and resistor values from the schematic,
the output is approximately 18V, not 3.3V. Since the regulator in use
(SS6640STR) is a boost regulator powered by PS (battery or AC input),
which are both >3.3V, the output could not be 3.3V anyway.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../dts/allwinner/sun50i-a64-pinebook.dts | 20 +++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 1ec39120323f..313f4e6edc19 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -21,22 +21,13 @@ aliases {
ethernet0 = &rtl8723cs;
};
- vdd_bl: regulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "bl-3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
- enable-active-high;
- };
-
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 0>;
brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
default-brightness-level = <2>;
enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
- power-supply = <&vdd_bl>;
+ power-supply = <&reg_vbklt>;
};
chosen {
@@ -57,6 +48,15 @@ lid_switch {
};
};
+ reg_vbklt: vbklt {
+ compatible = "regulator-fixed";
+ regulator-name = "vbklt";
+ regulator-min-microvolt = <18000000>;
+ regulator-max-microvolt = <18000000>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
--
2.24.1
From 425472eb612873c9c64b41df70020de58448bef3 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:31:04 -0600
Subject: [PATCH 7/8] arm64: dts: allwinner: pinebook: Fix 5v0 boost regulator
Now that AXP803 GPIO support is available, we can properly model
the hardware. Replace the use of GPIO0-LDO with a fixed regulator
controlled by GPIO0. This boost regulator is used to power the
(internal and external) USB ports, as well as the speakers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../dts/allwinner/sun50i-a64-pinebook.dts | 27 +++++++++----------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index 313f4e6edc19..c06c540e6c08 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -57,6 +57,15 @@ reg_vbklt: vbklt {
enable-active-high;
};
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
@@ -64,12 +73,7 @@ wifi_pwrseq: wifi_pwrseq {
speaker_amp: audio-amplifier {
compatible = "simple-audio-amplifier";
- /*
- * TODO This is actually a fixed regulator controlled by
- * the GPIO line on the PMIC. This should be corrected
- * once GPIO support is added for this PMIC.
- */
- VCC-supply = <&reg_ldo_io0>;
+ VCC-supply = <&reg_vcc5v0>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
sound-name-prefix = "Speaker Amp";
};
@@ -316,13 +320,6 @@ &reg_fldo2 {
regulator-name = "vdd-cpus";
};
-&reg_ldo_io0 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "vcc-usb";
- status = "okay";
-};
-
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
@@ -371,7 +368,7 @@ &usb_otg {
};
&usbphy {
- usb0_vbus-supply = <&reg_ldo_io0>;
- usb1_vbus-supply = <&reg_ldo_io0>;
+ usb0_vbus-supply = <&reg_vcc5v0>;
+ usb1_vbus-supply = <&reg_vcc5v0>;
status = "okay";
};
--
2.24.1
From c3aea4ea2117f5dc28da3d4175fc93296653ecd5 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 19 Jan 2020 10:30:58 -0600
Subject: [PATCH 8/8] arm64: dts: allwinner: pinebook: Remove unused AXP803
regulators
The Pinebook does not use the CSI bus on the A64. In fact it does not
use GPIO port E for anything at all. Thus the following regulators are
not used and do not need voltages set:
- ALDO1: Connected to VCC-PE only
- DLDO3: Not connected
- ELDO3: Not connected
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
.../boot/dts/allwinner/sun50i-a64-pinebook.dts | 16 +---------------
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
index c06c540e6c08..12e513ba8f50 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -217,9 +217,7 @@ &battery_power_supply {
};
&reg_aldo1 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-name = "vcc-csi";
+ regulator-name = "vcc-pe";
};
&reg_aldo2 {
@@ -282,12 +280,6 @@ &reg_dldo2 {
regulator-name = "vcc-edp";
};
-&reg_dldo3 {
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "avdd-csi";
-};
-
&reg_dldo4 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -301,12 +293,6 @@ &reg_eldo1 {
regulator-name = "cpvdd";
};
-&reg_eldo3 {
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-name = "vdd-1v8-csi";
-};
-
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
--
2.24.1

101
arm64-tegra-fix-pcie.patch
View File

@ -1,101 +0,0 @@
From 5fc5158c547fc3a2b46cbc6f73b926d8b78cd6e2 Mon Sep 17 00:00:00 2001
From: "Signed-off-by: Jon Hunter" <jonathanh@nvidia.com>
Date: Fri, 14 Feb 2020 13:53:53 +0000
Subject: [PATCH] ARM64: tegra: Fix Tegra194 PCIe compatible string
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic
designware PCIe platform driver instead of the Tegra194 designware PCIe
driver. This causes a boot failure on Tegra194 because the necessary
configuration to access the hardware is not performed.
The order in which the compatible strings are populated in Device-Tree
is not relevant in this case, because the kernel will attempt to probe
the device as soon as a driver is loaded and if the generic designware
PCIe driver is loaded first, then this driver will be probed first.
Therefore, to fix this problem, remove the "snps,dw-pcie" string from
the compatible string as we never want this driver to be probe on
Tegra194.
Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
.../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 2 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index b739f92da58e..1f90eb39870b 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -118,7 +118,7 @@ Tegra194:
--------
pcie@14180000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ccac43be12ac..4c58cb10fb9c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1208,7 +1208,7 @@ sor3: sor@15bc0000 {
};
pcie@14100000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
@@ -1253,7 +1253,7 @@ pcie@14100000 {
};
pcie@14120000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
@@ -1298,7 +1298,7 @@ pcie@14120000 {
};
pcie@14140000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
@@ -1343,7 +1343,7 @@ pcie@14140000 {
};
pcie@14160000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
@@ -1388,7 +1388,7 @@ pcie@14160000 {
};
pcie@14180000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
@@ -1433,7 +1433,7 @@ pcie@14180000 {
};
pcie@141a0000 {
- compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
+ compatible = "nvidia,tegra194-pcie";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
--
2.24.1

1
configs/fedora/generic/CONFIG_EXFAT_DEFAULT_IOCHARSET Normal file
View File

@ -0,0 +1 @@
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"

1
configs/fedora/generic/CONFIG_EXFAT_FS Normal file
View File

@ -0,0 +1 @@
CONFIG_EXFAT_FS=m

1
configs/fedora/generic/CONFIG_MHI_BUS Normal file
View File

@ -0,0 +1 @@
CONFIG_MHI_BUS=m

1
configs/fedora/generic/CONFIG_PCIE_EDR Normal file
View File

@ -0,0 +1 @@
CONFIG_PCIE_EDR=y

1
configs/fedora/generic/arm/CONFIG_INTERCONNECT_QCOM_OSM_L3 Normal file
View File

@ -0,0 +1 @@
CONFIG_INTERCONNECT_QCOM_OSM_L3=m

1
configs/fedora/generic/arm/CONFIG_INTERCONNECT_QCOM_SC7180 Normal file
View File

@ -0,0 +1 @@
CONFIG_INTERCONNECT_QCOM_SC7180=m

1
configs/fedora/generic/arm/CONFIG_MESON_SECURE_PM_DOMAINS Normal file
View File

@ -0,0 +1 @@
CONFIG_MESON_SECURE_PM_DOMAINS=y

1
configs/fedora/generic/arm/CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG Normal file
View File

@ -0,0 +1 @@
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y

1
configs/fedora/generic/arm/CONFIG_PHY_MESON_AXG_PCIE Normal file
View File

@ -0,0 +1 @@
CONFIG_PHY_MESON_AXG_PCIE=m

1
configs/fedora/generic/arm/CONFIG_SC_MSS_7180 Normal file
View File

@ -0,0 +1 @@
# CONFIG_SC_MSS_7180 is not set

1
configs/fedora/generic/arm/CONFIG_SM_GCC_8250 Normal file
View File

@ -0,0 +1 @@
CONFIG_SM_GCC_8250=m

1
configs/fedora/generic/arm/CONFIG_SOC_IMX8M Normal file
View File

@ -0,0 +1 @@
CONFIG_SOC_IMX8M=y

1
configs/fedora/generic/arm/aarch64/CONFIG_GPIO_MLXBF2 Normal file
View File

@ -0,0 +1 @@
CONFIG_GPIO_MLXBF2=m

1
configs/fedora/generic/arm/aarch64/CONFIG_PCIE_LAYERSCAPE_GEN4 Normal file
View File

@ -0,0 +1 @@
CONFIG_PCIE_LAYERSCAPE_GEN4=y

1
configs/fedora/generic/arm/aarch64/CONFIG_PCIE_MOBIVEIL Normal file
View File

@ -0,0 +1 @@
CONFIG_PCIE_MOBIVEIL=y

1
configs/fedora/generic/arm/aarch64/CONFIG_PCIE_MOBIVEIL_PLAT Normal file
View File

@ -0,0 +1 @@
CONFIG_PCIE_MOBIVEIL_PLAT=y

1
configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST Normal file
View File

@ -0,0 +1 @@
CONFIG_PCIE_TEGRA194_HOST=m

1
configs/fedora/generic/arm/armv7/CONFIG_ARCH_IPQ40XX Normal file
View File

@ -0,0 +1 @@
# CONFIG_ARCH_IPQ40XX is not set

1
configs/fedora/generic/arm/armv7/CONFIG_ARM_TEGRA_CPUIDLE Normal file
View File

@ -0,0 +1 @@
CONFIG_ARM_TEGRA_CPUIDLE=y

1
configs/fedora/generic/arm/armv7/CONFIG_TI_SYSCON_CLK Normal file
View File

@ -0,0 +1 @@
CONFIG_TI_SYSCON_CLK=m

1
configs/fedora/generic/powerpc/CONFIG_PMU_SYSFS Normal file
View File

@ -0,0 +1 @@
# CONFIG_PMU_SYSFS is not set

2
configs/fedora/generic/s390x/CONFIG_NODES_SHIFT
View File

@ -1 +1 @@
CONFIG_NODES_SHIFT=4
CONFIG_NODES_SHIFT=1

2
gitrev
View File

@ -1 +1 @@
bef7b2a7be28638770972ab2709adf11d601c11a
a10c9c710f9ecea87b9f4bbb837467893b4bef01

18
kernel-aarch64-debug-fedora.config
View File

@ -1841,6 +1841,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2135,6 +2137,7 @@ CONFIG_GPIO_MAX77620=y
CONFIG_GPIO_MAX77650=m
CONFIG_GPIO_MB86S7X=m
# CONFIG_GPIO_MC33880 is not set
CONFIG_GPIO_MLXBF2=m
CONFIG_GPIO_MLXBF=m
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_MOXTET=m
@ -2716,7 +2719,9 @@ CONFIG_INTEL_XWAY_PHY=m
CONFIG_INTERCONNECT=m
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
CONFIG_INTERCONNECT_QCOM_SDM845=m
CONFIG_INTERCONNECT_QCOM=y
# CONFIG_INTERVAL_TREE_TEST is not set
@ -3425,6 +3430,7 @@ CONFIG_MESON_IRQ_GPIO=y
# CONFIG_MESON_MX_EFUSE is not set
# CONFIG_MESON_MX_SOCINFO is not set
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
# CONFIG_MESON_WATCHDOG is not set
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3540,6 +3546,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4568,15 +4575,19 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
CONFIG_PCIE_HISI_STB=y
CONFIG_PCIE_KIRIN=y
# CONFIG_PCIE_MOBIVEIL is not set
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_MOBIVEIL_PLAT=y
CONFIG_PCIE_MOBIVEIL=y
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_QCOM=y
# CONFIG_PCIE_ROCKCHIP_HOST is not set
CONFIG_PCIE_TEGRA194_HOST=m
CONFIG_PCIE_TEGRA194=m
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX=y
@ -4648,6 +4659,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
CONFIG_PHY_MESON_GXL_USB2=m
@ -5441,6 +5454,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -5895,6 +5909,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
CONFIG_SM_GCC_8150=y
CONFIG_SM_GCC_8250=m
CONFIG_SMP=y
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
@ -6323,6 +6338,7 @@ CONFIG_SND_YMFPCI=m
CONFIG_SNI_NETSEC=m
# CONFIG_SOC_BRCMSTB is not set
# CONFIG_SOC_CAMERA is not set
CONFIG_SOC_IMX8M=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_SOC_TEGRA_FLOWCTRL=y
# CONFIG_SOC_TI is not set

18
kernel-aarch64-fedora.config
View File

@ -1833,6 +1833,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2119,6 +2121,7 @@ CONFIG_GPIO_MAX77620=y
CONFIG_GPIO_MAX77650=m
CONFIG_GPIO_MB86S7X=m
# CONFIG_GPIO_MC33880 is not set
CONFIG_GPIO_MLXBF2=m
CONFIG_GPIO_MLXBF=m
# CONFIG_GPIO_MOCKUP is not set
CONFIG_GPIO_MOXTET=m
@ -2700,7 +2703,9 @@ CONFIG_INTEL_XWAY_PHY=m
CONFIG_INTERCONNECT=m
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
CONFIG_INTERCONNECT_QCOM_SDM845=m
CONFIG_INTERCONNECT_QCOM=y
# CONFIG_INTERVAL_TREE_TEST is not set
@ -3406,6 +3411,7 @@ CONFIG_MESON_IRQ_GPIO=y
# CONFIG_MESON_MX_EFUSE is not set
# CONFIG_MESON_MX_SOCINFO is not set
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
# CONFIG_MESON_WATCHDOG is not set
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3521,6 +3527,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4548,15 +4555,19 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
CONFIG_PCIE_HISI_STB=y
CONFIG_PCIE_KIRIN=y
# CONFIG_PCIE_MOBIVEIL is not set
CONFIG_PCIE_LAYERSCAPE_GEN4=y
CONFIG_PCIE_MOBIVEIL_PLAT=y
CONFIG_PCIE_MOBIVEIL=y
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_PTM=y
CONFIG_PCIE_QCOM=y
# CONFIG_PCIE_ROCKCHIP_HOST is not set
CONFIG_PCIE_TEGRA194_HOST=m
CONFIG_PCIE_TEGRA194=m
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX=y
@ -4628,6 +4639,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
CONFIG_PHY_MESON_GXL_USB2=m
@ -5420,6 +5433,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -5874,6 +5888,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
CONFIG_SM_GCC_8150=y
CONFIG_SM_GCC_8250=m
CONFIG_SMP=y
CONFIG_SMSC911X=m
CONFIG_SMSC9420=m
@ -6301,6 +6316,7 @@ CONFIG_SND_YMFPCI=m
CONFIG_SNI_NETSEC=m
# CONFIG_SOC_BRCMSTB is not set
# CONFIG_SOC_CAMERA is not set
CONFIG_SOC_IMX8M=y
CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
CONFIG_SOC_TEGRA_FLOWCTRL=y
# CONFIG_SOC_TI is not set

15
kernel-armv7hl-debug-fedora.config
View File

@ -229,6 +229,7 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HIGHBANK=y
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IPQ40XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_MDM9615 is not set
@ -377,6 +378,7 @@ CONFIG_ARM_STI_CPUFREQ=m
CONFIG_ARM_TEGRA124_CPUFREQ=y
CONFIG_ARM_TEGRA20_CPUFREQ=m
CONFIG_ARM_TEGRA20_DEVFREQ=m
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_ARM_TEGRA_DEVFREQ=m
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_THUMB=y
@ -1858,6 +1860,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2732,7 +2736,9 @@ CONFIG_INTEL_XWAY_PHY=m
# CONFIG_INTERCONNECT is not set
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_IIO=m
@ -3463,6 +3469,7 @@ CONFIG_MESON_IRQ_GPIO=y
CONFIG_MESON_MX_EFUSE=m
CONFIG_MESON_MX_SOCINFO=y
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
CONFIG_MESON_WATCHDOG=m
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3583,6 +3590,7 @@ CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_WM8994=m
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MICREL_KS8995MA=m
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4650,6 +4658,7 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -4723,6 +4732,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
# CONFIG_PHY_MESON_GXL_USB2 is not set
@ -5553,6 +5564,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -6017,6 +6029,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
# CONFIG_SM_GCC_8150 is not set
CONFIG_SM_GCC_8250=m
CONFIG_SMP_ON_UP=y
CONFIG_SMP=y
CONFIG_SMSC911X=m
@ -6502,6 +6515,7 @@ CONFIG_SOC_IMX6UL=y
CONFIG_SOC_IMX6=y
CONFIG_SOC_IMX7D=y
CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_IMX8M=y
# CONFIG_SOC_LS1021A is not set
CONFIG_SOC_OMAP3430=y
CONFIG_SOC_OMAP5=y
@ -6913,6 +6927,7 @@ CONFIG_TI_PWMSS=y
CONFIG_TI_SCI_PROTOCOL=m
CONFIG_TI_SOC_THERMAL=m
# CONFIG_TI_ST is not set
CONFIG_TI_SYSCON_CLK=m
CONFIG_TI_THERMAL=y
# CONFIG_TI_TLC4541 is not set
# CONFIG_TLAN is not set

15
kernel-armv7hl-fedora.config
View File

@ -229,6 +229,7 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HIGHBANK=y
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IPQ40XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_MDM9615 is not set
@ -377,6 +378,7 @@ CONFIG_ARM_STI_CPUFREQ=m
CONFIG_ARM_TEGRA124_CPUFREQ=y
CONFIG_ARM_TEGRA20_CPUFREQ=m
CONFIG_ARM_TEGRA20_DEVFREQ=m
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_ARM_TEGRA_DEVFREQ=m
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_THUMB=y
@ -1851,6 +1853,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2717,7 +2721,9 @@ CONFIG_INTEL_XWAY_PHY=m
# CONFIG_INTERCONNECT is not set
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_IIO=m
@ -3445,6 +3451,7 @@ CONFIG_MESON_IRQ_GPIO=y
CONFIG_MESON_MX_EFUSE=m
CONFIG_MESON_MX_SOCINFO=y
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
CONFIG_MESON_WATCHDOG=m
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3565,6 +3572,7 @@ CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_WM8994=m
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MICREL_KS8995MA=m
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4631,6 +4639,7 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -4704,6 +4713,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
# CONFIG_PHY_MESON_GXL_USB2 is not set
@ -5533,6 +5544,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -5997,6 +6009,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
# CONFIG_SM_GCC_8150 is not set
CONFIG_SM_GCC_8250=m
CONFIG_SMP_ON_UP=y
CONFIG_SMP=y
CONFIG_SMSC911X=m
@ -6481,6 +6494,7 @@ CONFIG_SOC_IMX6UL=y
CONFIG_SOC_IMX6=y
CONFIG_SOC_IMX7D=y
CONFIG_SOC_IMX7ULP=y
CONFIG_SOC_IMX8M=y
# CONFIG_SOC_LS1021A is not set
CONFIG_SOC_OMAP3430=y
CONFIG_SOC_OMAP5=y
@ -6892,6 +6906,7 @@ CONFIG_TI_PWMSS=y
CONFIG_TI_SCI_PROTOCOL=m
CONFIG_TI_SOC_THERMAL=m
# CONFIG_TI_ST is not set
CONFIG_TI_SYSCON_CLK=m
CONFIG_TI_THERMAL=y
# CONFIG_TI_TLC4541 is not set
# CONFIG_TLAN is not set

15
kernel-armv7hl-lpae-debug-fedora.config
View File

@ -225,6 +225,7 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HIGHBANK=y
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IPQ40XX is not set
# CONFIG_ARCH_IXP4XX is not set
CONFIG_ARCH_KEYSTONE=y
# CONFIG_ARCH_MEDIATEK is not set
@ -367,6 +368,7 @@ CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SPE_PMU=m
CONFIG_ARM_TEGRA124_CPUFREQ=y
# CONFIG_ARM_TEGRA20_CPUFREQ is not set
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_ARM_TEGRA_DEVFREQ=m
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_THUMB=y
@ -1810,6 +1812,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2663,7 +2667,9 @@ CONFIG_INTEL_XWAY_PHY=m
# CONFIG_INTERCONNECT is not set
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_IIO=m
@ -3380,6 +3386,7 @@ CONFIG_MESON_IRQ_GPIO=y
CONFIG_MESON_MX_EFUSE=m
CONFIG_MESON_MX_SOCINFO=y
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
CONFIG_MESON_WATCHDOG=m
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3498,6 +3505,7 @@ CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_WM8994=m
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MICREL_KS8995MA=m
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4537,6 +4545,7 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -4610,6 +4619,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
# CONFIG_PHY_MESON_GXL_USB2 is not set
@ -5370,6 +5381,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -5823,6 +5835,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
# CONFIG_SM_GCC_8150 is not set
CONFIG_SM_GCC_8250=m
CONFIG_SMP_ON_UP=y
CONFIG_SMP=y
CONFIG_SMSC911X=m
@ -6273,6 +6286,7 @@ CONFIG_SOC_EXYNOS5800=y
# CONFIG_SOC_HAS_OMAP2_SDRC is not set
CONFIG_SOC_HAS_REALTIME_COUNTER=y
# CONFIG_SOC_IMX6SLL is not set
CONFIG_SOC_IMX8M=y
# CONFIG_SOC_LS1021A is not set
CONFIG_SOC_OMAP5=y
CONFIG_SOC_TEGRA_FLOWCTRL=y
@ -6670,6 +6684,7 @@ CONFIG_TI_PWMSS=y
CONFIG_TI_SCI_PROTOCOL=m
CONFIG_TI_SOC_THERMAL=m
# CONFIG_TI_ST is not set
CONFIG_TI_SYSCON_CLK=m
CONFIG_TI_THERMAL=y
# CONFIG_TI_TLC4541 is not set
# CONFIG_TLAN is not set

15
kernel-armv7hl-lpae-fedora.config
View File

@ -225,6 +225,7 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_ARCH_HIGHBANK=y
# CONFIG_ARCH_HISI is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IPQ40XX is not set
# CONFIG_ARCH_IXP4XX is not set
CONFIG_ARCH_KEYSTONE=y
# CONFIG_ARCH_MEDIATEK is not set
@ -367,6 +368,7 @@ CONFIG_ARM_SP805_WATCHDOG=m
CONFIG_ARM_SPE_PMU=m
CONFIG_ARM_TEGRA124_CPUFREQ=y
# CONFIG_ARM_TEGRA20_CPUFREQ is not set
CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_ARM_TEGRA_DEVFREQ=m
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_THUMB=y
@ -1803,6 +1805,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2648,7 +2652,9 @@ CONFIG_INTEL_XWAY_PHY=m
# CONFIG_INTERCONNECT is not set
CONFIG_INTERCONNECT_QCOM_MSM8916=m
# CONFIG_INTERCONNECT_QCOM_MSM8974 is not set
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
# CONFIG_INTERCONNECT_QCOM_QCS404 is not set
CONFIG_INTERCONNECT_QCOM_SC7180=m
# CONFIG_INTERVAL_TREE_TEST is not set
CONFIG_INV_MPU6050_I2C=m
CONFIG_INV_MPU6050_IIO=m
@ -3362,6 +3368,7 @@ CONFIG_MESON_IRQ_GPIO=y
CONFIG_MESON_MX_EFUSE=m
CONFIG_MESON_MX_SOCINFO=y
CONFIG_MESON_SARADC=m
CONFIG_MESON_SECURE_PM_DOMAINS=y
CONFIG_MESON_SM=y
CONFIG_MESON_WATCHDOG=m
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
@ -3480,6 +3487,7 @@ CONFIG_MFD_WL1273_CORE=m
CONFIG_MFD_WM8994=m
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MICREL_KS8995MA=m
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4518,6 +4526,7 @@ CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_DW_PLAT_HOST=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -4591,6 +4600,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLINK=m
# CONFIG_PHY_MAPPHONE_MDM6600 is not set
CONFIG_PHY_MESON8B_USB2=m
CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG=y
CONFIG_PHY_MESON_AXG_PCIE=m
CONFIG_PHY_MESON_G12A_USB2=y
CONFIG_PHY_MESON_G12A_USB3_PCIE=m
# CONFIG_PHY_MESON_GXL_USB2 is not set
@ -5350,6 +5361,7 @@ CONFIG_SCHED_SMT=y
CONFIG_SCHEDSTATS=y
CONFIG_SCHED_THERMAL_PRESSURE=y
CONFIG_SCHED_TRACER=y
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SCR24X is not set
# CONFIG_SCSI_3W_9XXX is not set
# CONFIG_SCSI_3W_SAS is not set
@ -5803,6 +5815,7 @@ CONFIG_SMC_DIAG=m
CONFIG_SMC=m
# CONFIG_SM_FTL is not set
# CONFIG_SM_GCC_8150 is not set
CONFIG_SM_GCC_8250=m
CONFIG_SMP_ON_UP=y
CONFIG_SMP=y
CONFIG_SMSC911X=m
@ -6252,6 +6265,7 @@ CONFIG_SOC_EXYNOS5800=y
# CONFIG_SOC_HAS_OMAP2_SDRC is not set
CONFIG_SOC_HAS_REALTIME_COUNTER=y
# CONFIG_SOC_IMX6SLL is not set
CONFIG_SOC_IMX8M=y
# CONFIG_SOC_LS1021A is not set
CONFIG_SOC_OMAP5=y
CONFIG_SOC_TEGRA_FLOWCTRL=y
@ -6649,6 +6663,7 @@ CONFIG_TI_PWMSS=y
CONFIG_TI_SCI_PROTOCOL=m
CONFIG_TI_SOC_THERMAL=m
# CONFIG_TI_ST is not set
CONFIG_TI_SYSCON_CLK=m
CONFIG_TI_THERMAL=y
# CONFIG_TI_TLC4541 is not set
# CONFIG_TLAN is not set

4
kernel-i686-debug-fedora.config
View File

@ -1568,6 +1568,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -3230,6 +3232,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4202,6 +4205,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_INTEL_GW is not set
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set

4
kernel-i686-fedora.config
View File

@ -1559,6 +1559,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -3211,6 +3213,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -4183,6 +4186,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_INTEL_GW is not set
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set

5
kernel-ppc64le-debug-fedora.config
View File

@ -1424,6 +1424,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2966,6 +2968,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -3895,6 +3898,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -4020,6 +4024,7 @@ CONFIG_PM_STD_PARTITION=""
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_TRACE=y
# CONFIG_PMU_SYSFS is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PNFS_BLOCK=m

5
kernel-ppc64le-fedora.config
View File

@ -1415,6 +1415,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -2946,6 +2948,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -3874,6 +3877,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set
@ -3999,6 +4003,7 @@ CONFIG_PM_STD_PARTITION=""
CONFIG_PM_TEST_SUSPEND=y
CONFIG_PM_TRACE_RTC=y
CONFIG_PM_TRACE=y
# CONFIG_PMU_SYSFS is not set
# CONFIG_PM_WAKELOCKS is not set
CONFIG_PM=y
CONFIG_PNFS_BLOCK=m

6
kernel-s390x-debug-fedora.config
View File

@ -1430,6 +1430,8 @@ CONFIG_ETHERNET=y
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
CONFIG_EXPOLINE_AUTO=y
# CONFIG_EXPOLINE_FULL is not set
@ -2940,6 +2942,7 @@ CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -3707,7 +3710,7 @@ CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_NLS=y
# CONFIG_NOA1305 is not set
CONFIG_NODES_SHIFT=4
CONFIG_NODES_SHIFT=1
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
@ -3858,6 +3861,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set

6
kernel-s390x-fedora.config
View File

@ -1421,6 +1421,8 @@ CONFIG_ETHERNET=y
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
CONFIG_EXPOLINE_AUTO=y
# CONFIG_EXPOLINE_FULL is not set
@ -2920,6 +2922,7 @@ CONFIG_MFD_SM501_GPIO=y
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
CONFIG_MICROCHIP_PHY=m
@ -3686,7 +3689,7 @@ CONFIG_NLS_MAC_TURKISH=m
CONFIG_NLS_UTF8=m
CONFIG_NLS=y
# CONFIG_NOA1305 is not set
CONFIG_NODES_SHIFT=4
CONFIG_NODES_SHIFT=1
# CONFIG_NO_HZ_FULL is not set
CONFIG_NO_HZ_IDLE=y
CONFIG_NO_HZ=y
@ -3837,6 +3840,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_PCI_ENDPOINT_TEST is not set

4
kernel-x86_64-debug-fedora.config
View File

@ -1607,6 +1607,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -3279,6 +3281,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MIC_COSM=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
@ -4249,6 +4252,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_INTEL_GW is not set
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set

4
kernel-x86_64-fedora.config
View File

@ -1598,6 +1598,8 @@ CONFIG_ETHOC=m
CONFIG_ETHTOOL_NETLINK=y
# CONFIG_EUROTECH_WDT is not set
# CONFIG_EVM is not set
CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"
CONFIG_EXFAT_FS=m
# CONFIG_EXPERT is not set
# CONFIG_EXPOLINE_AUTO is not set
CONFIG_EXPOLINE_FULL=y
@ -3260,6 +3262,7 @@ CONFIG_MFD_WL1273_CORE=m
# CONFIG_MFD_WM8994 is not set
# CONFIG_MGEODEGX1 is not set
# CONFIG_MGEODE_LX is not set
CONFIG_MHI_BUS=m
CONFIG_MIC_COSM=m
# CONFIG_MICREL_KS8995MA is not set
CONFIG_MICREL_PHY=m
@ -4230,6 +4233,7 @@ CONFIG_PCIE_CADENCE_HOST=y
CONFIG_PCIE_DPC=y
# CONFIG_PCIE_DW_PLAT_HOST is not set
CONFIG_PCIE_ECRC=y
CONFIG_PCIE_EDR=y
# CONFIG_PCIE_INTEL_GW is not set
# CONFIG_PCIE_MOBIVEIL is not set
# CONFIG_PCI_ENDPOINT is not set

20
kernel.spec
View File

@ -107,7 +107,7 @@ Summary: The Linux kernel
# The rc snapshot level
%global rcrev 0
# The git snapshot level
%define gitrev 5
%define gitrev 6
# Set rpm version accordingly
%define rpmversion 5.%{upstream_sublevel}.0
%endif
@ -822,32 +822,17 @@ Patch304: ARM-tegra-usb-no-reset.patch
# Raspberry Pi
# v5 https://patchwork.kernel.org/cover/11429245/
Patch311: USB-pci-quirks-Add-Raspberry-Pi-4-quirk.patch
# https://patchwork.kernel.org/patch/11420129/
Patch313: ARM-dts-bcm2711-Move-emmc2-into-its-own-bus.patch
# Tegra bits
# https://www.spinics.net/lists/linux-tegra/msg48152.html
Patch320: ARM64-Tegra-fixes.patch
# https://lkml.org/lkml/2020/2/14/401
Patch323: arm64-tegra-fix-pcie.patch
# http://patchwork.ozlabs.org/patch/1243112/
Patch325: backlight-lp855x-Ensure-regulators-are-disabled-on-probe-failure.patch
# https://patchwork.ozlabs.org/patch/1261638/
Patch326: arm64-drm-tegra-Fix-SMMU-support-on-Tegra124-and-Tegra210.patch
# Coral
Patch330: arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch
# Pine64 bits
# 340-345 queued for 5.7
Patch340: arm64-pinebook-fixes.patch
Patch341: arm64-a64-mbus.patch
# v4 https://patchwork.kernel.org/cover/11420797/
Patch342: Add-support-for-the-pine64-Pinebook-Pro.patch
# https://lkml.org/lkml/2020/1/15/1320
Patch344: arm64-pine64-pinetab.patch
# https://www.spinics.net/lists/arm-kernel/msg789135.html
Patch345: arm64-pine64-pinephone.patch
# https://patchwork.kernel.org/cover/11440399/
Patch346: Add-support-for-PinePhone-LCD-panel.patch
@ -2978,6 +2963,9 @@ fi
#
#
%changelog
* Mon Apr 06 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.7.0-0.rc0.git6.1
- Linux v5.6-11374-ga10c9c710f9e
* Fri Apr 03 2020 Justin M. Forbes <jforbes@fedoraproject.org> - 5.7.0-0.rc0.git5.1
- Linux v5.6-9431-gbef7b2a7be28

2
sources
View File

@ -1,2 +1,2 @@
SHA512 (linux-5.6.tar.xz) = 80846fe2b4e4a7ff471d2dde28a8216ae807a3209f959e93d39ea4fc9a189ea28ec3db9d303b3fe15a28c2cb90e7446876678e93e23353c2d6f262e364a06bc9
SHA512 (patch-5.6-git5.xz) = 9c133ce6a1c57a1c09dcfb2fa5025cf9731439f73e98741f88792c804e57a1a1404efe83817ec2a40c1da5c02942254820b387ab83f05d2fc5823d0631556fb4
SHA512 (patch-5.6-git6.xz) = a47a364b1c28ce9aba00ef7e4698242489cbc3cfd48778bb23181c589fb611120b039400b291614115d040fa71d9040b292571d2f1f13736831c55b12d25ee47