2b187d056f
- xserver-1.3.0-edid-quirk-backports.patch: Update the EDID quirks code to match current git.
91 lines
2.7 KiB
Diff
91 lines
2.7 KiB
Diff
diff -up xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c.edid-quirks xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c
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--- xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c.edid-quirks 2007-04-18 00:33:14.000000000 -0400
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+++ xorg-server-1.3.0.0/hw/xfree86/modes/xf86EdidModes.c 2007-09-17 14:37:36.000000000 -0400
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@@ -49,32 +49,12 @@
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typedef enum {
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DDC_QUIRK_NONE = 0,
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- /* Force detailed sync polarity to -h +v */
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- DDC_QUIRK_DT_SYNC_HM_VP = 1 << 0,
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/* First detailed mode is bogus, prefer largest mode at 60hz */
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- DDC_QUIRK_PREFER_LARGE_60 = 1 << 1,
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+ DDC_QUIRK_PREFER_LARGE_60 = 1 << 0,
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/* 135MHz clock is too high, drop a bit */
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- DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 2
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+ DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1
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} ddc_quirk_t;
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-static Bool quirk_dt_sync_hm_vp (int scrnIndex, xf86MonPtr DDC)
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-{
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- /* Belinea 1924S1W */
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- if (memcmp (DDC->vendor.name, "MAX", 4) == 0 &&
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- DDC->vendor.prod_id == 1932)
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- return TRUE;
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- /* Belinea 10 20 30W */
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- if (memcmp (DDC->vendor.name, "MAX", 4) == 0 &&
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- DDC->vendor.prod_id == 2007)
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- return TRUE;
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- /* ViewSonic VX2025wm (bug #9941) */
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- if (memcmp (DDC->vendor.name, "VSC", 4) == 0 &&
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- DDC->vendor.prod_id == 58653)
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- return TRUE;
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-
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- return FALSE;
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-}
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-
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static Bool quirk_prefer_large_60 (int scrnIndex, xf86MonPtr DDC)
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{
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/* Belinea 10 15 55 */
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@@ -87,9 +67,10 @@ static Bool quirk_prefer_large_60 (int s
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DDC->vendor.prod_id == 44358)
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return TRUE;
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- /* Samsung SyncMaster 226BW */
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+ /* Samsung SyncMaster 22[56]BW */
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if (memcmp (DDC->vendor.name, "SAM", 4) == 0 &&
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- DDC->vendor.prod_id == 638)
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+ (DDC->vendor.prod_id == 638 ||
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+ DDC->vendor.prod_id == 596))
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return TRUE;
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return FALSE;
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@@ -112,10 +93,6 @@ typedef struct {
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} ddc_quirk_map_t;
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static const ddc_quirk_map_t ddc_quirks[] = {
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- {
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- quirk_dt_sync_hm_vp, DDC_QUIRK_DT_SYNC_HM_VP,
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- "Set detailed timing sync polarity to -h +v"
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- },
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{
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quirk_prefer_large_60, DDC_QUIRK_PREFER_LARGE_60,
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"Detailed timing is not preferred, use largest mode at 60Hz"
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@@ -251,20 +228,15 @@ DDCModeFromDetailedTiming(int scrnIndex,
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if (timing->interlaced)
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Mode->Flags |= V_INTERLACE;
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- if (quirks & DDC_QUIRK_DT_SYNC_HM_VP)
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- Mode->Flags |= V_NHSYNC | V_PVSYNC;
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+ if (timing->misc & 0x02)
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+ Mode->Flags |= V_PVSYNC;
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else
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- {
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- if (timing->misc & 0x02)
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- Mode->Flags |= V_PHSYNC;
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- else
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- Mode->Flags |= V_NHSYNC;
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+ Mode->Flags |= V_NVSYNC;
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- if (timing->misc & 0x01)
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- Mode->Flags |= V_PVSYNC;
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- else
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- Mode->Flags |= V_NVSYNC;
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- }
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+ if (timing->misc & 0x01)
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+ Mode->Flags |= V_PHSYNC;
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+ else
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+ Mode->Flags |= V_NHSYNC;
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return Mode;
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}
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