ba355a609a
0001-Prepare-NEWS-for-branch-3.23-fixes.patch 0002-486180-MIPS-VexGuestArchState-has-no-member-named-gu.patch 0003-Bug-486293-memccpy-false-positives.patch 0004-Bug-486569-linux-inotify_init-syscall-wrapper-missin.patch 0005-aarch64-frinta-and-frinta-vector-instructions.patch 0006-mips-skip-using-shared-syscall-numbers-for-mips32.patch 0007-Fix-uninitialized-err-in-handle_extension.patch 0008-Avoid-use-of-guest_IP_AT_SYSCALL-in-handle_extension.patch 0009-s390x-Minor-fixes-in-extension-s390x.c.patch 0010-Bug-453044-gbserver_tests-failures-in-aarch64.patch 0011-Linux-regtest-reallocarray-needs-malloc.h.patch 0012-Bug-487439-SIGILL-in-JDK11-JDK17.patch 0013-Don-t-leave-fds-created-with-log-file-xml-file-or-lo.patch 0014-Close-both-internal-pipe-fds-after-VG_-fork-in-paren.patch 0015-Don-t-allow-programs-calling-fnctl-on-valgrind-s-own.patch 0016-mips-skip-using-shared-syscall-numbers-for-mips64.patch 0017-gdbserver_tests-filters-remove-python-rpm-module-loa.patch 0018-Implement-VMOVQ-xmm1-xmm2-m64.patch 0019-arm64-Fix-fcvtas-instruction.patch 0020-gdbserver_tests-filters-remove-more-verbose-python-r.patch 0021-Avoid-dev-inode-check-on-btrfs-with-sanity-level-3.patch Resolves: #RHEL-46588 Add valgrind 3.23 stable branch fixes (rhel-10-beta)
283 lines
9.6 KiB
Diff
283 lines
9.6 KiB
Diff
From f5d1c336e9276dd5947ef94c9831d9d53673b75b Mon Sep 17 00:00:00 2001
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From: Paul Floyd <pjfloyd@wanadoo.fr>
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Date: Thu, 9 May 2024 21:01:52 +0200
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Subject: [PATCH 05/11] aarch64 frinta and frinta vector instructions
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The initial fix for Bug 484426 only corrected frinta and frintn
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scalar instructions. This adds support for the vector variants.
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(cherry picked from commit 7b66a5b58219ac1a4865da8e371edbdb8d765f32)
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---
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NEWS | 1 +
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VEX/priv/guest_arm64_toIR.c | 47 ++++++----
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none/tests/arm64/frinta_frintn.cpp | 141 +++++++++++++++++++++++++++++
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3 files changed, 171 insertions(+), 18 deletions(-)
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diff --git a/NEWS b/NEWS
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index b65f9206679b..adb52169dd87 100644
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--- a/NEWS
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+++ b/NEWS
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@@ -8,6 +8,7 @@ The following bugs have been fixed or resolved on this branch.
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486180 [MIPS] 'VexGuestArchState' has no member named 'guest_IP_AT_SYSCALL'
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486293 memccpy false positives
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486569 linux inotify_init syscall wrapper missing POST entry in syscall_table
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+n-i-bz aarch64 frinta and frinta vector instructions
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To see details of a given bug, visit
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https://bugs.kde.org/show_bug.cgi?id=XXXXXX
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index c7e395b4b63d..27d945d6328d 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -13821,46 +13821,57 @@ Bool dis_AdvSIMD_two_reg_misc(/*MB_OUT*/DisResult* dres, UInt insn)
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/* -------- 1,1x,11000 (apparently unassigned) (7) -------- */
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/* -------- 1,1x,11001 FRINTI 2d_2d, 4s_4s, 2s_2s (8) -------- */
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/* rm plan:
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- FRINTN: tieeven -- !! FIXME KLUDGED !!
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+ FRINTN: tieeven
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FRINTM: -inf
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FRINTP: +inf
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FRINTZ: zero
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- FRINTA: tieaway -- !! FIXME KLUDGED !!
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+ FRINTA: tieaway
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FRINTX: per FPCR + "exact = TRUE"
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FRINTI: per FPCR
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*/
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Bool isD = (size & 1) == 1;
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if (bitQ == 0 && isD) return False; // implied 1d case
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- IRTemp irrmRM = mk_get_IR_rounding_mode();
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-
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- UChar ch = '?';
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- IRTemp irrm = newTemp(Ity_I32);
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+ UChar ch = '?';
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+ IROp op = isD ? Iop_RoundF64toInt : Iop_RoundF32toInt;
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+ Bool isBinop = True;
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+ IRExpr* irrmE = NULL;
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switch (ix) {
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- case 1: ch = 'n'; assign(irrm, mkU32(Irrm_NEAREST)); break;
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- case 2: ch = 'm'; assign(irrm, mkU32(Irrm_NegINF)); break;
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- case 3: ch = 'p'; assign(irrm, mkU32(Irrm_PosINF)); break;
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- case 4: ch = 'z'; assign(irrm, mkU32(Irrm_ZERO)); break;
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+ case 1: ch = 'n'; isBinop = False; op = isD ? Iop_RoundF64toIntE : Iop_RoundF32toIntE; break;
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+ case 2: ch = 'm'; irrmE = mkU32(Irrm_NegINF); break;
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+ case 3: ch = 'p'; irrmE = mkU32(Irrm_PosINF); break;
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+ case 4: ch = 'z'; irrmE = mkU32(Irrm_ZERO); break;
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// The following is a kludge. Should be: Irrm_NEAREST_TIE_AWAY_0
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- case 5: ch = 'a'; assign(irrm, mkU32(Irrm_NEAREST)); break;
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+ case 5: ch = 'a'; isBinop = False; op = isD ? Iop_RoundF64toIntA0 : Iop_RoundF32toIntA0; break;
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// I am unsure about the following, due to the "integral exact"
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// description in the manual. What does it mean? (frintx, that is)
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- case 6: ch = 'x'; assign(irrm, mkexpr(irrmRM)); break;
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- case 8: ch = 'i'; assign(irrm, mkexpr(irrmRM)); break;
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+ case 6: ch = 'x'; irrmE = mkexpr(mk_get_IR_rounding_mode()); break;
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+ case 8: ch = 'i'; irrmE = mkexpr(mk_get_IR_rounding_mode()); break;
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default: vassert(0);
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}
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- IROp opRND = isD ? Iop_RoundF64toInt : Iop_RoundF32toInt;
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if (isD) {
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for (UInt i = 0; i < 2; i++) {
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- putQRegLane(dd, i, binop(opRND, mkexpr(irrm),
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- getQRegLane(nn, i, Ity_F64)));
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+ if (isBinop) {
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+ IRTemp irrm = newTemp(Ity_I32);
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+ assign(irrm, irrmE);
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+ putQRegLane(dd, i, binop(op, mkexpr(irrm),
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+ getQRegLane(nn, i, Ity_F64)));
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+ } else {
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+ putQRegLane(dd, i, unop(op, getQRegLane(nn, i, Ity_F64)));
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+ }
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}
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} else {
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UInt n = bitQ==1 ? 4 : 2;
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for (UInt i = 0; i < n; i++) {
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- putQRegLane(dd, i, binop(opRND, mkexpr(irrm),
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- getQRegLane(nn, i, Ity_F32)));
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+ if (isBinop) {
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+ IRTemp irrm = newTemp(Ity_I32);
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+ assign(irrm, irrmE);
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+ putQRegLane(dd, i, binop(op, mkexpr(irrm),
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+ getQRegLane(nn, i, Ity_F32)));
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+ } else {
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+ putQRegLane(dd, i, unop(op, getQRegLane(nn, i, Ity_F32)));
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+ }
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}
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if (bitQ == 0)
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putQRegLane(dd, 1, mkU64(0)); // zero out lanes 2 and 3
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diff --git a/none/tests/arm64/frinta_frintn.cpp b/none/tests/arm64/frinta_frintn.cpp
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index 8e13761eb966..c0803688f698 100644
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--- a/none/tests/arm64/frinta_frintn.cpp
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+++ b/none/tests/arm64/frinta_frintn.cpp
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@@ -36,6 +36,55 @@ void test_frinta(T input, T expected)
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}
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}
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+template<typename T>
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+void test_frinta_fullvec(T* input, T* expected)
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+{
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+ T result[2*sizeof(double)/sizeof(T)];
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+ T* rp = result;
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+ if constexpr (std::is_same_v<double, T> == true)
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+ {
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+ __asm__ __volatile__(
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+ "ldr q23, [%1];\n"
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+ "frinta v22.2d, v23.2d;\n"
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+ "str q22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+ }
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+ else
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+ {
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+ __asm__ __volatile__(
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+ "ldr q23, [%1];\n"
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+ "frinta v22.4s, v23.4s;\n"
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+ "str q22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+ assert(result[2] == expected[2]);
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+ assert(result[3] == expected[3]);
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+ }
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+}
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+
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+void test_frinta_halfvec(float* input, float* expected)
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+{
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+ float result[2];
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+ float* rp = result;
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+ __asm__ __volatile__(
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+ "ldr d23, [%1];\n"
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+ "frinta v22.2s, v23.2s;\n"
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+ "str d22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+}
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+
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+
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template<typename T>
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void test_frintn(T input, T expected)
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{
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@@ -66,6 +115,54 @@ void test_frintn(T input, T expected)
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}
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}
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+template<typename T>
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+void test_frintn_fullvec(T* input, T* expected)
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+{
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+ T result[2*sizeof(double)/sizeof(T)];
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+ T* rp = result;
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+ if constexpr (std::is_same_v<double, T> == true)
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+ {
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+ __asm__ __volatile__(
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+ "ldr q23, [%1];\n"
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+ "frintn v22.2d, v23.2d;\n"
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+ "str q22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+ }
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+ else
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+ {
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+ __asm__ __volatile__(
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+ "ldr q23, [%1];\n"
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+ "frintn v22.4s, v23.4s;\n"
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+ "str q22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+ assert(result[2] == expected[2]);
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+ assert(result[3] == expected[3]);
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+ }
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+}
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+
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+void test_frintn_halfvec(float* input, float* expected)
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+{
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+ float result[2];
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+ float* rp = result;
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+ __asm__ __volatile__(
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+ "ldr d23, [%1];\n"
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+ "frintn v22.2s, v23.2s;\n"
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+ "str d22, [%0];\n"
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+ : "+rm" (rp)
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+ : "r" (input)
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+ : "memory", "v22", "v23");
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+ assert(result[0] == expected[0]);
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+ assert(result[1] == expected[1]);
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+}
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+
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int main()
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{
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// round "away from zero"
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@@ -78,6 +175,36 @@ int main()
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test_frinta(-1.5F, -2.0F);
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test_frinta(-2.5F, -3.0F);
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+ double in1[] = {1.5, 1.5};
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+ double out1[] = {2.0, 2,0};
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+ test_frinta_fullvec(in1, out1);
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+ double in2[] = {2.5, 2.5};
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+ double out2[] = {3.0, 3,0};
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+ test_frinta_fullvec(in2, out2);
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+ double in3[] = {-1.5, -1.5};
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+ double out3[] = {-2.0, -2,0};
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+ test_frinta_fullvec(in3, out3);
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+ double in4[] = {-2.5, -2.5};
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+ double out4[] = {-3.0, -3,0};
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+ test_frinta_fullvec(in4, out4);
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+
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+ float in1f[] = {1.5F, 1.5F, 1.5F, 1.5F};
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+ float out1f[] = {2.0F, 2.0F, 2.0F, 2.0F};
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+ test_frinta_fullvec(in1f, out1f);
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+ test_frinta_halfvec(in1f, out1f);
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+ float in2f[] = {2.5F, 2.5F, 2.5F, 2.5F};
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+ float out2f[] = {3.0F, 3.0F, 3.0F, 3.0F};
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+ test_frinta_fullvec(in2f, out2f);
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+ test_frinta_halfvec(in2f, out2f);
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+ float in3f[] = {-1.5F, -1.5F, -1.5F, -1.5F};
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+ float out3f[] = {-2.0F, -2.0F, -2.0F, -2.0F};
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+ test_frinta_fullvec(in3f, out3f);
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+ test_frinta_halfvec(in3f, out3f);
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+ float in4f[] = {-2.5F, -2.5F, -2.5F, -2.5F};
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+ float out4f[] = {-3.0F, -3.0F, -3.0F, -3.0F};
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+ test_frinta_fullvec(in4f, out4f);
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+ test_frinta_halfvec(in4f, out4f);
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+
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// round "to even"
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test_frintn(1.5, 2.0);
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test_frintn(2.5, 2.0);
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@@ -87,5 +214,19 @@ int main()
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test_frintn(2.5F, 2.0F);
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test_frintn(-1.5F, -2.0F);
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test_frintn(-2.5F, -2.0F);
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+
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+ test_frintn_fullvec(in1, out1);
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+ test_frintn_fullvec(in2, out1);
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+ test_frintn_fullvec(in3, out3);
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+ test_frintn_fullvec(in4, out3);
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+
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+ test_frintn_fullvec(in1f, out1f);
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+ test_frintn_halfvec(in1f, out1f);
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+ test_frintn_fullvec(in2f, out1f);
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+ test_frintn_halfvec(in2f, out1f);
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+ test_frintn_fullvec(in3f, out3f);
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+ test_frintn_halfvec(in3f, out3f);
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+ test_frintn_fullvec(in4f, out3f);
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+ test_frintn_halfvec(in4f, out3f);
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}
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--
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2.45.2
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