144 lines
5.5 KiB
Diff
144 lines
5.5 KiB
Diff
commit 4e8ca2298aa12f10a40134f0aac161954597952e
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Author: sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9>
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Date: Thu May 15 16:47:56 2014 +0000
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Enable: sys_add_key, sys_keyctl, apparently needed by glibc-2.19.90 on
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arm64-linux.
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git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13972 a5019735-40e9-0310-863c-91ae7b9d1cf9
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diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
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index b82b06b..c6de921 100644
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--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
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+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
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@@ -1024,6 +1024,8 @@ static SyscallTableEntry syscall_main_table[] = {
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GENX_(__NR_brk, sys_brk), // 214
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GENXY(__NR_munmap, sys_munmap), // 215
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GENX_(__NR_mremap, sys_mremap), // 216
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+ LINX_(__NR_add_key, sys_add_key), // 217
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+ LINXY(__NR_keyctl, sys_keyctl), // 219
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PLAX_(__NR_clone, sys_clone), // 220
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GENX_(__NR_execve, sys_execve), // 221
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@@ -1342,9 +1344,7 @@ static SyscallTableEntry syscall_main_table[] = {
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//ZZ LINXY(__NR_msgrcv, sys_msgrcv),
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//ZZ LINXY(__NR_msgctl, sys_msgctl), // 304
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//ZZ
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-//ZZ LINX_(__NR_add_key, sys_add_key), // 286
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//ZZ LINX_(__NR_request_key, sys_request_key), // 287
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-//ZZ LINXY(__NR_keyctl, sys_keyctl), // not 288...
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//ZZ // LINX_(__NR_ioprio_set, sys_ioprio_set), // 289
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//ZZ
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//ZZ // LINX_(__NR_ioprio_get, sys_ioprio_get), // 290
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commit e013b24c6f62fda9836f5b0378573f1f7923ec8a
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Author: sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Thu May 15 16:49:21 2014 +0000
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Initial front-end fixings needed to handle code generated by gcc-4.9
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on arm64-linux.
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git-svn-id: svn://svn.valgrind.org/vex/trunk@2862 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 862eb20..85b2f2d 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -1004,6 +1004,8 @@ static IRExpr* getQRegLO ( UInt qregNo, IRType ty )
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{
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Int off = offsetQRegLane(qregNo, ty, 0);
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switch (ty) {
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+ case Ity_I8:
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+ case Ity_I16:
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case Ity_I32: case Ity_I64:
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case Ity_F32: case Ity_F64: case Ity_V128:
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break;
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@@ -7102,6 +7104,20 @@ Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn)
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/* else it's really an ORR; fall through. */
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}
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+ /* ---------------- CMEQ_d_d_#0 ---------------- */
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+ /*
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+ 010 11110 11 10000 0100 110 n d
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+ */
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+ if ((INSN(31,0) & 0xFFFFFC00) == 0x5EE09800) {
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+ UInt nn = INSN(9,5);
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+ UInt dd = INSN(4,0);
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+ putQReg128(dd, unop(Iop_ZeroHI64ofV128,
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+ binop(Iop_CmpEQ64x2, getQReg128(nn),
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+ mkV128(0x0000))));
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+ DIP("cmeq d%u, d%u, #0\n", dd, nn);
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+ return True;
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+ }
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+
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vex_printf("ARM64 front end: simd_and_fp\n");
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return False;
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# undef INSN
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commit 5a75f1c5aad7e96a7f785fc05afecec96fab8166
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Author: sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Fri May 16 11:20:07 2014 +0000
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Implement SHL_d_d_#imm.
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git-svn-id: svn://svn.valgrind.org/vex/trunk@2863 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 85b2f2d..25659b8 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -7106,7 +7106,7 @@ Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn)
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/* ---------------- CMEQ_d_d_#0 ---------------- */
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/*
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- 010 11110 11 10000 0100 110 n d
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+ 010 11110 11 10000 0100 110 n d CMEQ Dd, Dn, #0
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*/
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if ((INSN(31,0) & 0xFFFFFC00) == 0x5EE09800) {
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UInt nn = INSN(9,5);
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@@ -7118,6 +7118,22 @@ Bool dis_ARM64_simd_and_fp(/*MB_OUT*/DisResult* dres, UInt insn)
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return True;
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}
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+ /* ---------------- SHL_d_d_#imm ---------------- */
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+ /* 31 22 21 18 15 9 4
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+ 010 111110 1 ih3 ib 010101 n d SHL Dd, Dn, #(ih3:ib)
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+ */
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+ if (INSN(31,22) == BITS10(0,1,0,1,1,1,1,1,0,1)
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+ && INSN(15,10) == BITS6(0,1,0,1,0,1)) {
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+ UInt nn = INSN(9,5);
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+ UInt dd = INSN(4,0);
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+ UInt sh = INSN(21,16);
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+ vassert(sh < 64);
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+ putQReg128(dd, unop(Iop_ZeroHI64ofV128,
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+ binop(Iop_ShlN64x2, getQReg128(nn), mkU8(sh))));
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+ DIP("shl d%u, d%u, #%u\n", dd, nn, sh);
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+ return True;
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+ }
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+
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vex_printf("ARM64 front end: simd_and_fp\n");
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return False;
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# undef INSN
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diff --git a/VEX/priv/host_arm64_isel.c b/VEX/priv/host_arm64_isel.c
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index eb06cdf..470df6b 100644
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--- a/VEX/priv/host_arm64_isel.c
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+++ b/VEX/priv/host_arm64_isel.c
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@@ -5543,10 +5543,14 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
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default:
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vassert(0);
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}
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- if (op != ARM64vecsh_INVALID && amt > 0 && amt <= limit) {
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+ if (op != ARM64vecsh_INVALID && amt >= 0 && amt <= limit) {
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HReg src = iselV128Expr(env, argL);
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HReg dst = newVRegV(env);
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- addInstr(env, ARM64Instr_VShiftImmV(op, dst, src, amt));
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+ if (amt > 0) {
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+ addInstr(env, ARM64Instr_VShiftImmV(op, dst, src, amt));
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+ } else {
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+ dst = src;
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+ }
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return dst;
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}
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}
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