269 lines
12 KiB
Diff
269 lines
12 KiB
Diff
commit 8f36c464966045b51a75144ca4c65f354082194f
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Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
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Date: Tue Mar 15 15:08:01 2016 +0000
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Bug #360425 - arm64 unsupported instruction ldpsw tests.
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Add tests for ldpsw implementation VEX svn r3212.
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git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15830 a5019735-40e9-0310-863c-91ae7b9d1cf9
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diff --git a/none/tests/arm64/memory.c b/none/tests/arm64/memory.c
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index cbf31fd..91949ac 100644
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--- a/none/tests/arm64/memory.c
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+++ b/none/tests/arm64/memory.c
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@@ -280,6 +280,18 @@ TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
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////////////////////////////////////////////////////////////////
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printf("STL{R,RH,RB} (entirely MISSING)\n");
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+
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+////////////////////////////////////////////////////////////////
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+// TESTINST2_hide2 allows use of x28 as scratch
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+printf("LDPSW (immediate, simm7)\n");
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+
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+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
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+TESTINST2_hide2("ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
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+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
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+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
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+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
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+TESTINST2_hide2("ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
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+
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} /* end of test_memory_old() */
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@@ -1608,6 +1620,12 @@ MEM_TEST("prfm pstl2strm, [x5,w6,uxtw #3]", 12, 4);
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MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
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MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]", 12, -4);
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+////////////////////////////////////////////////////////////////
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+printf("LDPSW (immediate, simm7)\n");
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+MEM_TEST("ldpsw x13, x23, [x5], #-24", 0, 0);
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+MEM_TEST("ldpsw x13, x23, [x5, #-40]!", 0, 0);
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+MEM_TEST("ldpsw x13, x23, [x5, #-40]", 0, 0);
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+
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} /* end of test_memory2() */
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////////////////////////////////////////////////////////////////
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diff --git a/none/tests/arm64/memory.stdout.exp b/none/tests/arm64/memory.stdout.exp
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index eb6ec3f..be57108 100644
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--- a/none/tests/arm64/memory.stdout.exp
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+++ b/none/tests/arm64/memory.stdout.exp
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@@ -98,6 +98,13 @@ ldar w21, [x22] :: rd 00000000f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
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ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000
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ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000
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STL{R,RH,RB} (entirely MISSING)
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+LDPSW (immediate, simm7)
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+ldpsw x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd ffffffffebe9e7e4 rn (hidden), cin 0, nzcv 00000000
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+ldpsw x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
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+ldpsw x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000
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+ldpsw x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
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+ldpsw x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd ffffffff9b999794 rn (hidden), cin 0, nzcv 00000000
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+ldpsw x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
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LDR,STR (immediate, uimm12)ldr x13, [x5, #24] with x5 = middle_of_block+-1, x6=0
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[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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@@ -26258,3 +26265,94 @@ prfm pstl3strm, [x5,w6,sxtw #3] with x5 = middle_of_block+12, x6=-4
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0 x5 (sub, base reg)
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0 x6 (sub, index reg)
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+LDPSW (immediate, simm7)
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+ldpsw x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
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+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ 5430cb99daf026bb x13 (xor, xfer intreg #1)
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+ 58eb9b702726900d x23 (xor, xfer intreg #2)
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+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
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+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
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+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
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+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
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+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
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+ -24 x5 (sub, base reg)
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+ 0 x6 (sub, index reg)
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+
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+ldpsw x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
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+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ 7f799c624bfa7f08 x13 (xor, xfer intreg #1)
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+ 3e7857cc51fd19f0 x23 (xor, xfer intreg #2)
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+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
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+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
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+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
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+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
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+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
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+ -40 x5 (sub, base reg)
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+ 0 x6 (sub, index reg)
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+
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+ldpsw x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
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+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
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+ 01ba3febe99768c0 x13 (xor, xfer intreg #1)
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+ 1cef424f7c21ff9b x23 (xor, xfer intreg #2)
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+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
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+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
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+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
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+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
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+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
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+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
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+ 0 x5 (sub, base reg)
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+ 0 x6 (sub, index reg)
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+
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commit c10b13cb0ec8b797124d8379b7f932f92341bd4b
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Author: sewardj <sewardj@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
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Date: Tue Mar 15 14:24:56 2016 +0000
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arm64: implement LDPSW. Fixes #360425. Initial patch+investigation by Mark Wielaard.
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git-svn-id: svn://svn.valgrind.org/vex/trunk@3212 8f6e269a-dfd6-0310-a8e1-e2731360e62c
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 8da9780..d4fe1b8 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -4804,7 +4804,6 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
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(at-EA)
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x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]
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*/
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-
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UInt insn_30_23 = INSN(30,23);
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if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1)
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|| insn_30_23 == BITS8(0,1,0,1,0,0,1,1)
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@@ -4912,6 +4911,87 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
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}
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}
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+ /* -------- LDPSW (immediate, simm7) (INT REGS) -------- */
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+ /* Does 32 bit transfers which are sign extended to 64 bits.
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+ simm7 is scaled by the (single-register) transfer size
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+
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+ (at-Rn-then-Rn=EA)
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+ 01 101 0001 1 imm7 Rt2 Rn Rt1 LDPSW Rt1,Rt2, [Xn|SP], #imm
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+
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+ (at-EA-then-Rn=EA)
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+ 01 101 0011 1 imm7 Rt2 Rn Rt1 LDPSW Rt1,Rt2, [Xn|SP, #imm]!
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+
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+ (at-EA)
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+ 01 101 0010 1 imm7 Rt2 Rn Rt1 LDPSW Rt1,Rt2, [Xn|SP, #imm]
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+ */
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+ UInt insn_31_22 = INSN(31,22);
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+ if (insn_31_22 == BITS10(0,1,1,0,1,0,0,0,1,1)
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+ || insn_31_22 == BITS10(0,1,1,0,1,0,0,1,1,1)
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+ || insn_31_22 == BITS10(0,1,1,0,1,0,0,1,0,1)) {
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+ UInt bWBack = INSN(23,23);
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+ UInt rT1 = INSN(4,0);
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+ UInt rN = INSN(9,5);
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+ UInt rT2 = INSN(14,10);
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+ Long simm7 = (Long)sx_to_64(INSN(21,15), 7);
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+ if ((bWBack && (rT1 == rN || rT2 == rN) && rN != 31)
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+ || (rT1 == rT2)) {
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+ /* undecodable; fall through */
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+ } else {
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+ if (rN == 31) { /* FIXME generate stack alignment check */ }
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+
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+ // Compute the transfer address TA and the writeback address WA.
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+ IRTemp tRN = newTemp(Ity_I64);
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+ assign(tRN, getIReg64orSP(rN));
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+ IRTemp tEA = newTemp(Ity_I64);
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+ simm7 = 4 * simm7;
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+ assign(tEA, binop(Iop_Add64, mkexpr(tRN), mkU64(simm7)));
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+
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+ IRTemp tTA = newTemp(Ity_I64);
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+ IRTemp tWA = newTemp(Ity_I64);
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+ switch (INSN(24,23)) {
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+ case BITS2(0,1):
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+ assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break;
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+ case BITS2(1,1):
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+ assign(tTA, mkexpr(tEA)); assign(tWA, mkexpr(tEA)); break;
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+ case BITS2(1,0):
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+ assign(tTA, mkexpr(tEA)); /* tWA is unused */ break;
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+ default:
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+ vassert(0); /* NOTREACHED */
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+ }
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+
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+ // 32 bit load, sign extended to 64 bits
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+ putIReg64orZR(rT1, unop(Iop_32Sto64,
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+ loadLE(Ity_I32, binop(Iop_Add64,
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+ mkexpr(tTA),
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+ mkU64(0)))));
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+ putIReg64orZR(rT2, unop(Iop_32Sto64,
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+ loadLE(Ity_I32, binop(Iop_Add64,
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+ mkexpr(tTA),
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+ mkU64(4)))));
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+ if (bWBack)
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+ putIReg64orSP(rN, mkexpr(tEA));
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+
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+ const HChar* fmt_str = NULL;
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+ switch (INSN(24,23)) {
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+ case BITS2(0,1):
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+ fmt_str = "ldpsw %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
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+ break;
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+ case BITS2(1,1):
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+ fmt_str = "ldpsw %s, %s, [%s, #%lld]! (at-EA-then-Rn=EA)\n";
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+ break;
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+ case BITS2(1,0):
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+ fmt_str = "ldpsw %s, %s, [%s, #%lld] (at-Rn)\n";
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+ break;
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+ default:
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+ vassert(0);
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+ }
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+ DIP(fmt_str, nameIReg64orZR(rT1),
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+ nameIReg64orZR(rT2),
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+ nameIReg64orSP(rN), simm7);
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+ return True;
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+ }
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+ }
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+
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/* ---------------- LDR (literal, int reg) ---------------- */
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/* 31 29 23 4
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00 011 000 imm19 Rt LDR Wt, [PC + sxTo64(imm19 << 2)]
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