137 lines
5.3 KiB
Diff
137 lines
5.3 KiB
Diff
commit 9d1d6cd6acc612cd94261956a8a94a6403a5d528
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Author: Will Schmidt <will_schmidt@vnet.ibm.com>
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Date: Tue Jan 4 16:41:00 2022 -0600
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Subject: Assorted changes to protect from side affects from the feature checking code.
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This problem was initially reported by Tulio, he assisted me in
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identifying the underlying issue here.
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This was discovered on a Power10, and occurs since the ISA 3.1 support
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check uses the brh instruction via a hardcoded ".long 0x7f1401b6" asm stanza.
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That encoding writes to r20, and since the stanza does not contain a clobber
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the compiler did not know to save or restore that register upon entry or exit.
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The junk value remaining in r20 subsequently caused a segfault.
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This patch adds clobber masks to the instruction stanzas, as well as
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updates the associated comments to clarify which registers are being
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used.
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As part of this change I've also
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- updated the .long for the cnttzw instruction to write to r20, and
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zeroed the reserved bits from that instruction so it is properly
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decoded by the disassembler.
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- updated the .long for the dadd instruction to write to f0.
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I've inspected the current codegen with these changes in place, and
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confirm that r20 is now saved and restored on entry and exit from the
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machine_get_hwcaps() function.
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diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
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index 0b60ecc0fd44..a860ed67a334 100644
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--- a/coregrind/m_machine.c
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+++ b/coregrind/m_machine.c
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@@ -1244,11 +1244,11 @@ Bool VG_(machine_get_hwcaps)( void )
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/* Check for ISA 3.0 support. */
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have_isa_3_0 = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_isa_3_0 = False;
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} else {
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- __asm__ __volatile__(".long 0x7d205434"); /* cnttzw RT, RB */
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+ __asm__ __volatile__(".long 00x7f140434"::"r20"); /* cnttzw r20,r24 */
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}
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// ISA 3.1 not supported on 32-bit systems
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/* determine dcbz/dcbzl sizes while we still have the signal
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@@ -1356,79 +1356,79 @@ Bool VG_(machine_get_hwcaps)( void )
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/* Altivec insns */
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have_V = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_V = False;
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} else {
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- __asm__ __volatile__(".long 0x10000484"); /*vor 0,0,0*/
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+ __asm__ __volatile__(".long 0x10000484"); /* vor v0,v0,v0 */
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}
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/* General-Purpose optional (fsqrt, fsqrts) */
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have_FX = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_FX = False;
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} else {
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- __asm__ __volatile__(".long 0xFC00002C"); /*fsqrt 0,0*/
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+ __asm__ __volatile__(".long 0xFC00002C"); /* fsqrt f0,f0 */
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}
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/* Graphics optional (stfiwx, fres, frsqrte, fsel) */
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have_GX = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_GX = False;
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} else {
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- __asm__ __volatile__(".long 0xFC000034"); /*frsqrte 0,0*/
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+ __asm__ __volatile__(".long 0xFC000034"); /* frsqrte f0,f0 */
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}
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/* VSX support implies Power ISA 2.06 */
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have_VX = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_VX = False;
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} else {
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- __asm__ __volatile__(".long 0xf0000564"); /* xsabsdp XT,XB */
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+ __asm__ __volatile__(".long 0xf0000564"); /* xsabsdp vs0,vs0 */
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}
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/* Check for Decimal Floating Point (DFP) support. */
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have_DFP = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_DFP = False;
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} else {
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- __asm__ __volatile__(".long 0xee4e8005"); /* dadd FRT,FRA, FRB */
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+ __asm__ __volatile__(".long 0xec0e8005"); /* dadd f0,f14,f16 */
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}
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/* Check for ISA 2.07 support. */
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have_isa_2_07 = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_isa_2_07 = False;
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} else {
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- __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd XT,RA */
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+ __asm__ __volatile__(".long 0x7c000166"); /* mtvsrd f0,r0 */
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}
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/* Check for ISA 3.0 support. */
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have_isa_3_0 = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_isa_3_0 = False;
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} else {
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- __asm__ __volatile__(".long 0x7d205434"); /* cnttzw RT, RB */
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+ __asm__ __volatile__(".long 0x7f140434":::"r20"); /* cnttzw r20,r24 */
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}
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/* Check for ISA 3.1 support. */
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have_isa_3_1 = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_isa_3_1 = False;
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} else {
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- __asm__ __volatile__(".long 0x7f1401b6"); /* brh RA, RS */
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+ __asm__ __volatile__(".long 0x7f1401b6":::"r20"); /* brh r20,r24 */
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}
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/* Check if Host supports scv instruction */
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have_scv_support = True;
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if (VG_MINIMAL_SETJMP(env_unsup_insn)) {
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have_scv_support = False;
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} else {
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/* Set r0 to 13 for the system time call. Don't want to make a random
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system call. */
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- __asm__ __volatile__(".long 0x7c000278"); /* clear r0 */
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- __asm__ __volatile__(".long 0x6009000d"); /* set r0 to 13 */
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- __asm__ __volatile__(".long 0x44000001"); /* scv */
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+ __asm__ __volatile__(".long 0x7c000278"); /* clear r0 with xor r0,r0,r0 */
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+ __asm__ __volatile__(".long 0x6009000d"); /* set r0 to 13 with ori r9,r0,13 */
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+ __asm__ __volatile__(".long 0x44000001"); /* scv 0 */
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}
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/* determine dcbz/dcbzl sizes while we still have the signal
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* handlers registered */
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find_ppc_dcbz_sz(&vai);
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