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valgrind/valgrind-3.13.0-ppc64-vex-fixes.patch
Mark Wielaard 874b124dd3 3.13.0-8 - Add valgrind-3.13.0-ppc64-vex-fixes.patch 
KDE#385334
PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field
PPC64, revert the change to vperm instruction.
KDE#385183
PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions
PPC64, Fix bug in vperm instruction.
KDE#385210
PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16.
KDE#385208
PPC64, Use the vperm code to implement the xxperm inst.
PPC64, Replace body of generate_store_FPRF with C helper function.
PPC64, Add support for the Data Stream Control Register (DSCR)
2017-10-16 23:24:22 +02:00

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commit 7fce2c5269f82a7d063c87335a25de84fc9acc64
Author: Carl Love <carll@us.ibm.com>
Date: Tue Oct 3 12:03:22 2017 -0500
PPC64, Add support for the Data Stream Control Register (DSCR)
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 8230d65..34adf62 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -921,6 +921,7 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
vex_state->guest_TEXASR = 0;
vex_state->guest_PPR = 0x4ULL << 50; // medium priority
vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
+ vex_state->guest_DSCR = 0;
}
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index a8d4926..2467f70 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -296,6 +296,7 @@ static Bool OV32_CA32_supported = False;
#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
#define OFFB_PPR offsetofPPCGuestState(guest_PPR)
#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB)
+#define OFFB_DSCR offsetofPPCGuestState(guest_DSCR)
/*------------------------------------------------------------*/
@@ -459,6 +460,7 @@ typedef enum {
* automatically decrement. Could be added later if
* needed.
*/
+ PPC_GST_DSCR, // Data Stream Control Register
PPC_GST_MAX
} PPC_GST;
@@ -3068,6 +3070,9 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
case PPC_GST_PSPB:
return IRExpr_Get( OFFB_PSPB, ty );
+ case PPC_GST_DSCR:
+ return IRExpr_Get( OFFB_DSCR, ty );
+
default:
vex_printf("getGST(ppc): reg = %u", reg);
vpanic("getGST(ppc)");
@@ -3344,6 +3349,11 @@ static void putGST ( PPC_GST reg, IRExpr* src )
mkU64( 0x1C000000000000) ) ) );
break;
}
+ case PPC_GST_DSCR:
+ vassert( ty_src == Ity_I64 );
+ stmt( IRStmt_Put( OFFB_DSCR, src ) );
+ break;
+
default:
vex_printf("putGST(ppc): reg = %u", reg);
vpanic("putGST(ppc)");
@@ -9407,6 +9417,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_XER ),
/* Signed */False) );
break;
+ case 0x3: // 131
+ DIP("mfspr r%u (DSCR)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_DSCR) );
+ break;
case 0x8:
DIP("mflr r%u\n", rD_addr);
putIReg( rD_addr, getGST( PPC_GST_LR ) );
@@ -9575,6 +9589,10 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
DIP("mtxer r%u\n", rS_addr);
putGST( PPC_GST_XER, mkNarrowTo32(ty, mkexpr(rS)) );
break;
+ case 0x3:
+ DIP("mtspr r%u (DSCR)\n", rS_addr);
+ putGST( PPC_GST_DSCR, mkexpr(rS) );
+ break;
case 0x8:
DIP("mtlr r%u\n", rS_addr);
putGST( PPC_GST_LR, mkexpr(rS) );
diff --git a/VEX/pub/libvex_guest_ppc32.h b/VEX/pub/libvex_guest_ppc32.h
index 816ef5a..bb48ac5 100644
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -252,8 +252,8 @@ typedef
/* 1388 */ ULong guest_PPR; // Program Priority register
/* 1396 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
/* 1400 */ UInt guest_PSPB; // Problem State Priority Boost register
+ /* 1404 */ ULong guest_DSCR; // Data Stream Control register
/* Padding to make it have an 16-aligned size */
- /* 1404 */ UInt padding2;
/* 1408 */ UInt padding3;
/* 1412 */ UInt padding4;
}
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index 02c4020..8c01fa6 100644
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -292,11 +292,12 @@ typedef
/* 1686 */ ULong guest_PPR; // Program Priority register
/* 1694 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
/* 1698 */ UInt guest_PSPB; // Problem State Priority Boost register
+ /* 1702 */ ULong guest_DSCR; // Data Stream Control register
/* Padding to make it have an 16-aligned size */
- /* 1698 */ UInt padding1;
- /* 1702 UInt padding2; */
- /* 1706 UInt padding3; */
+ /* 1710 */ UInt padding1;
+ /* 1714 */ UInt padding2;
+ /* 1718 */ UInt padding3;
}
VexGuestPPC64State;
diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 3ff7c44..1d57e0c 100644
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -194,6 +194,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
if (o == GOF(TFIAR) && sz == 8) return -1;
if (o == GOF(PPR) && sz == 8) return -1;
if (o == GOF(PSPB) && sz == 8) return -1;
+ if (o == GOF(DSCR) && sz == 8) return -1;
// With ISA 2.06, the "Vector-Scalar Floating-point" category
// provides facilities to support vector and scalar binary floating-
diff --git a/memcheck/mc_main.c b/memcheck/mc_main.c
index a9a565b..892e503 100644
--- a/memcheck/mc_main.c
+++ b/memcheck/mc_main.c
@@ -4468,7 +4468,7 @@ static UInt mb_get_origin_for_guest_offset ( ThreadId tid,
static void mc_post_reg_write ( CorePart part, ThreadId tid,
PtrdiffT offset, SizeT size)
{
-# define MAX_REG_WRITE_SIZE 1728
+# define MAX_REG_WRITE_SIZE 1744
UChar area[MAX_REG_WRITE_SIZE];
tl_assert(size <= MAX_REG_WRITE_SIZE);
VG_(memset)(area, V_BITS8_DEFINED, size);
commit acdeb75d2a58f4f3910ddaf9b2bc2ec74378fa3a
Author: Carl Love <carll@us.ibm.com>
Date: Tue Oct 3 12:08:09 2017 -0500
PPC64, Replace body of generate_store_FPRF with C helper function.
The function calculates the floating point condition code values
and stores them into the floating point condition code register.
The function is used by a number of instructions. The calculation
generates a lot of Iops as it much check the operatds for NaN, SNaN,
zero, dnorm, norm and infinity. The large number of Iops exhausts
temporary memory.
diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h
index fe411f7..f3eb956 100644
--- a/VEX/priv/guest_ppc_defs.h
+++ b/VEX/priv/guest_ppc_defs.h
@@ -156,6 +156,7 @@ extern ULong convert_to_zoned_helper( ULong src_hi, ULong src_low,
extern ULong convert_to_national_helper( ULong src, ULong return_upper );
extern ULong convert_from_zoned_helper( ULong src_hi, ULong src_low );
extern ULong convert_from_national_helper( ULong src_hi, ULong src_low );
+extern ULong generate_C_FPCC_helper( ULong size, ULong src_hi, ULong src );
/* --- DIRTY HELPERS --- */
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 34adf62..bf2d071 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -216,6 +216,110 @@ IRExpr* guest_ppc64_spechelper ( const HChar* function_name,
}
+/* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */
+#define I16_EXP_MASK 0x7C00
+#define I16_FRACTION_MASK 0x03FF
+#define I32_EXP_MASK 0x7F800000
+#define I32_FRACTION_MASK 0x007FFFFF
+#define I64_EXP_MASK 0x7FF0000000000000ULL
+#define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL
+#define V128_EXP_MASK 0x7FFF000000000000ULL
+#define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */
+
+ULong generate_C_FPCC_helper( ULong irType, ULong src_hi, ULong src )
+{
+ UInt NaN, inf, zero, norm, dnorm, pos;
+ UInt bit0, bit1, bit2, bit3;
+ UInt sign_bit = 0;
+ ULong exp_mask = 0, exp_part = 0, frac_part = 0;
+ ULong fpcc, c;
+
+ if ( irType == Ity_I16 ) {
+ frac_part = I16_FRACTION_MASK & src;
+ exp_mask = I16_EXP_MASK;
+ exp_part = exp_mask & src;
+ sign_bit = src >> 15;
+
+ } else if ( irType == Ity_I32 ) {
+ frac_part = I32_FRACTION_MASK & src;
+ exp_mask = I32_EXP_MASK;
+ exp_part = exp_mask & src;
+ sign_bit = src >> 31;
+
+ } else if ( irType == Ity_I64 ) {
+ frac_part = I64_FRACTION_MASK & src;
+ exp_mask = I64_EXP_MASK;
+ exp_part = exp_mask & src;
+ sign_bit = src >> 63;
+
+ } else if ( irType == Ity_F128 ) {
+ /* only care if the frac part is zero or non-zero */
+ frac_part = (V128_FRACTION_MASK & src_hi) | src;
+ exp_mask = V128_EXP_MASK;
+ exp_part = exp_mask & src_hi;
+ sign_bit = src_hi >> 63;
+ } else {
+ vassert(0); // Unknown value of irType
+ }
+
+ /* NaN: exponene is all ones, fractional part not zero */
+ if ((exp_part == exp_mask) && (frac_part != 0))
+ NaN = 1;
+ else
+ NaN = 0;
+
+ /* inf: exponent all 1's, fraction part is zero */
+ if ((exp_part == exp_mask) && (frac_part == 0))
+ inf = 1;
+ else
+ inf = 0;
+
+ /* zero: exponent is 0, fraction part is zero */
+ if ((exp_part == 0) && (frac_part == 0))
+ zero = 1;
+ else
+ zero = 0;
+
+ /* norm: exponent is not 0, exponent is not all 1's */
+ if ((exp_part != 0) && (exp_part != exp_mask))
+ norm = 1;
+ else
+ norm = 0;
+
+ /* dnorm: exponent is all 0's, fraction is not 0 */
+ if ((exp_part == 0) && (frac_part != 0))
+ dnorm = 1;
+ else
+ dnorm = 0;
+
+ /* pos: MSB is 1 */
+ if (sign_bit == 0)
+ pos = 1;
+ else
+ pos = 0;
+
+ /* calculate FPCC */
+ /* If the result is NaN then must force bits 1, 2 and 3 to zero
+ * to get correct result.
+ */
+ bit0 = NaN | inf;
+
+ bit1 = (!NaN) & zero;
+ bit2 = (!NaN) & ((pos & dnorm) | (pos & norm) | (pos & inf))
+ & ((!zero) & (!NaN));
+ bit3 = (!NaN) & (((!pos) & dnorm) |((!pos) & norm) | ((!pos) & inf))
+ & ((!zero) & (!NaN));
+
+ fpcc = (bit3 << 3) | (bit2 << 2) | (bit1 << 1) | bit0;
+
+ /* calculate C */
+ c = NaN | ((!pos) & dnorm) | ((!pos) & zero) | (pos & dnorm);
+
+ /* return C in the upper 32-bits and FPCC in the lower 32 bits */
+ return (c <<32) | fpcc;
+}
+
+
/*---------------------------------------------------------------*/
/*--- Misc BCD clean helpers. ---*/
/*---------------------------------------------------------------*/
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 2467f70..0dae368 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -3860,7 +3860,7 @@ static IRExpr * is_Denorm( IRType size, IRTemp src )
setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
- /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
+ /* check exponent is all zeros */
zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
/* check fractional part is not zero */
@@ -3871,8 +3871,11 @@ static IRExpr * is_Denorm( IRType size, IRTemp src )
return mkAND1( zero_exp, not_zero_frac );
}
+#if 0
/* Normalized number has exponent between 1 and max_exp -1, or in other words
the exponent is not zero and not equal to the max exponent value. */
+ Currently not needed since generate_C_FPCC is now done with a C helper.
+ Keep it around, might be useful in the future.
static IRExpr * is_Norm( IRType size, IRTemp src )
{
IRExpr *not_zero_exp, *not_max_exp;
@@ -3919,72 +3922,18 @@ static IRExpr * is_Norm( IRType size, IRTemp src )
return mkAND1( not_zero_exp, not_max_exp );
}
+#endif
-
-static IRExpr * create_FPCC( IRTemp NaN, IRTemp inf,
- IRTemp zero, IRTemp norm,
- IRTemp dnorm, IRTemp pos,
- IRTemp neg ) {
- IRExpr *bit0, *bit1, *bit2, *bit3;
-
- /* If the result is NaN then must force bits 1, 2 and 3 to zero
- * to get correct result.
- */
- bit0 = unop( Iop_1Uto32, mkOR1( mkexpr( NaN ), mkexpr( inf ) ) );
- bit1 = unop( Iop_1Uto32, mkAND1( mkNOT1( mkexpr( NaN ) ), mkexpr( zero ) ) );
- bit2 = unop( Iop_1Uto32,
- mkAND1( mkNOT1( mkexpr( NaN ) ),
- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( pos ),
- mkexpr( dnorm ) ),
- mkAND1( mkexpr( pos ),
- mkexpr( norm ) ) ),
- mkAND1( mkexpr( pos ),
- mkexpr( inf ) ) ),
- mkAND1( mkNOT1 ( mkexpr( zero ) ),
- mkNOT1( mkexpr( NaN ) ) ) ) ) );
- bit3 = unop( Iop_1Uto32,
- mkAND1( mkNOT1( mkexpr( NaN ) ),
- mkAND1( mkOR1( mkOR1( mkAND1( mkexpr( neg ),
- mkexpr( dnorm ) ),
- mkAND1( mkexpr( neg ),
- mkexpr( norm ) ) ),
- mkAND1( mkexpr( neg ),
- mkexpr( inf ) ) ),
- mkAND1( mkNOT1 ( mkexpr( zero ) ),
- mkNOT1( mkexpr( NaN ) ) ) ) ) );
-
- return binop( Iop_Or32,
- binop( Iop_Or32,
- bit0,
- binop( Iop_Shl32, bit1, mkU8( 1 ) ) ),
- binop( Iop_Or32,
- binop( Iop_Shl32, bit2, mkU8( 2 ) ),
- binop( Iop_Shl32, bit3, mkU8( 3 ) ) ) );
-}
-
-static IRExpr * create_C( IRTemp NaN, IRTemp zero,
- IRTemp dnorm, IRTemp pos,
- IRTemp neg )
-{
-
- return unop( Iop_1Uto32,
- mkOR1( mkOR1( mkexpr( NaN ),
- mkAND1( mkexpr( neg ), mkexpr( dnorm ) ) ),
- mkOR1( mkAND1( mkexpr( neg ), mkexpr( zero ) ),
- mkAND1( mkexpr( pos ), mkexpr( dnorm ) ) ) ) );
-}
-
-static void generate_store_FPRF( IRType size, IRTemp src )
+static void generate_store_FPRF( IRType size, IRTemp src,
+ const VexAbiInfo* vbi )
{
- IRExpr *FPCC, *C;
- IRTemp NaN = newTemp( Ity_I1 ), inf = newTemp( Ity_I1 );
- IRTemp dnorm = newTemp( Ity_I1 ), norm = newTemp( Ity_I1 );
- IRTemp pos = newTemp( Ity_I1 ), neg = newTemp( Ity_I1 );
- IRTemp zero = newTemp( Ity_I1 );
- IRTemp sign_bit = newTemp( Ity_I1 );
- IRTemp value;
+ /* This function was originally written using IR code. It has been
+ * replaced with a clean helper due to the large amount of IR code
+ * needed by this function.
+ */
+ IRTemp tmp = newTemp( Ity_I64 );
vassert( ( size == Ity_I16 ) || ( size == Ity_I32 )
|| ( size == Ity_I64 ) || ( size == Ity_F128 ) );
@@ -3993,82 +3942,45 @@ static void generate_store_FPRF( IRType size, IRTemp src )
|| ( typeOfIRExpr(irsb->tyenv, mkexpr( src ) ) == Ity_F128 ) );
if( size == Ity_I16 ) {
- /* The 16-bit floating point value is in the lower 16-bits of
- the 32-bit input value */
- value = newTemp( Ity_I32 );
- assign( value, mkexpr( src ) );
- assign( sign_bit,
- unop ( Iop_32to1,
- binop( Iop_And32,
- binop( Iop_Shr32, mkexpr( value ), mkU8( 15 ) ),
- mkU32( 0x1 ) ) ) );
-
+ assign( tmp,
+ mkIRExprCCall( Ity_I64, 0 /*regparms*/,
+ "generate_store_C_FPCC_helper",
+ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
+ mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
+ mkexpr( src ) ) ) );
} else if( size == Ity_I32 ) {
- value = newTemp( size );
- assign( value, mkexpr( src ) );
- assign( sign_bit,
- unop ( Iop_32to1,
- binop( Iop_And32,
- binop( Iop_Shr32, mkexpr( value ), mkU8( 31 ) ),
- mkU32( 0x1 ) ) ) );
-
+ assign( tmp,
+ mkIRExprCCall( Ity_I64, 0 /*regparms*/,
+ "generate_store_C_FPCC_helper",
+ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
+ mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
+ mkexpr( src ) ) ) );
} else if( size == Ity_I64 ) {
- value = newTemp( size );
- assign( value, mkexpr( src ) );
- assign( sign_bit,
- unop ( Iop_64to1,
- binop( Iop_And64,
- binop( Iop_Shr64, mkexpr( value ), mkU8( 63 ) ),
- mkU64( 0x1 ) ) ) );
-
- } else {
- /* Move the F128 bit pattern to an integer V128 bit pattern */
- value = newTemp( Ity_V128 );
- assign( value,
- binop( Iop_64HLtoV128,
- unop( Iop_ReinterpF64asI64,
- unop( Iop_F128HItoF64, mkexpr( src ) ) ),
- unop( Iop_ReinterpF64asI64,
- unop( Iop_F128LOtoF64, mkexpr( src ) ) ) ) );
-
- size = Ity_V128;
- assign( sign_bit,
- unop ( Iop_64to1,
- binop( Iop_And64,
- binop( Iop_Shr64,
- unop( Iop_V128HIto64, mkexpr( value ) ),
- mkU8( 63 ) ),
- mkU64( 0x1 ) ) ) );
+ assign( tmp,
+ mkIRExprCCall( Ity_I64, 0 /*regparms*/,
+ "generate_store_C_FPCC_helper",
+ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
+ mkIRExprVec_3( mkU64( size ), mkU64( 0 ),
+ mkexpr( src ) ) ) );
+ } else if( size == Ity_F128 ) {
+ assign( tmp,
+ mkIRExprCCall( Ity_I64, 0 /*regparms*/,
+ "generate_store_C_FPCC_helper",
+ fnptr_to_fnentry( vbi, &generate_C_FPCC_helper ),
+ mkIRExprVec_3( mkU64( size ),
+ unop( Iop_ReinterpF64asI64,
+ unop( Iop_F128HItoF64,
+ mkexpr( src ) ) ),
+ unop( Iop_ReinterpF64asI64,
+ unop( Iop_F128LOtoF64,
+ mkexpr( src ) ) ) ) ) );
}
- /* Calculate the floating point result field FPRF */
- assign( NaN, is_NaN( size, value ) );
- assign( inf, is_Inf( size, value ) );
- assign( zero, is_Zero( size, value ) );
- assign( norm, is_Norm( size, value ) );
- assign( dnorm, is_Denorm( size, value ) );
- assign( pos, mkAND1( mkNOT1( mkexpr( sign_bit ) ), mkU1( 1 ) ) );
- assign( neg, mkAND1( mkexpr( sign_bit ), mkU1( 1 ) ) );
-
- /* create the FPRF bit field
- *
- * FPRF field[4:0] type of value
- * 10001 QNaN
- * 01001 - infininity
- * 01000 - Normalized
- * 11000 - Denormalized
- * 10010 - zero
- * 00010 + zero
- * 10100 + Denormalized
- * 00100 + Normalized
- * 00101 + infinity
+ /* C is in the upper 32-bits, FPCC is in the lower 32-bits of the
+ * value returned by the helper function
*/
- FPCC = create_FPCC( NaN, inf, zero, norm, dnorm, pos, neg );
- C = create_C( NaN, zero, dnorm, pos, neg );
-
- /* Write the C and FPCC fields of the FPRF field */
- putC( C );
- putFPCC( FPCC );
+ putC( unop( Iop_64HIto32, mkexpr( tmp) ) );
+ putFPCC( unop( Iop_64to32, mkexpr( tmp) ) );
}
/* This function takes an Ity_I32 input argument interpreted
@@ -18538,7 +18450,8 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 )
* Miscellaneous VSX Scalar Instructions
*/
static Bool
-dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
+dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
+ int allow_isa_3_0 )
{
#define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL
/* XX3-Form and XX2-Form */
@@ -18783,7 +18696,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
putVSReg( XT, mkexpr( result ) );
assign( value, unop( Iop_V128HIto64, mkexpr( result ) ) );
- generate_store_FPRF( Ity_I64, value );
+ generate_store_FPRF( Ity_I64, value, vbi );
return True;
} else if (inst_select == 17) { // xscvdphp
@@ -18798,7 +18711,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2, int allow_isa_3_0 )
assign( value, unop( Iop_64to32, unop( Iop_V128HIto64,
mkexpr( result ) ) ) );
putVSReg( XT, mkexpr( result ) );
- generate_store_FPRF( Ity_I16, value );
+ generate_store_FPRF( Ity_I16, value, vbi );
return True;
} else {
@@ -21475,7 +21388,7 @@ dis_vx_store ( UInt theInstr )
}
static Bool
-dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
+dis_vx_Scalar_Round_to_quad_integer( UInt theInstr, const VexAbiInfo* vbi )
{
/* The ISA 3.0 instructions supported in this function require
* the underlying hardware platform that supports the ISA3.0
@@ -21514,7 +21427,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
DIP("xsrqpix %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC);
assign( vT, binop( Iop_F128toI128S, rm, mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
} /* case 0x005 */
break;
case 0x025: // xsrqpxp VSX Scalar Round Quad-Precision to
@@ -21530,7 +21443,7 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
DIP("xsrqpxp %d,v%d,v%d,%d\n", R, vT_addr, vB_addr, RMC);
assign( vT, binop( Iop_RndF128, rm, mkexpr( vB ) ) );
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
} /* case 0x025 */
break;
default:
@@ -21542,7 +21455,8 @@ dis_vx_Scalar_Round_to_quad_integer( UInt theInstr )
}
static Bool
-dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
+dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr,
+ const VexAbiInfo* vbi )
{
/* The ISA 3.0 instructions supported in this function require
* the underlying hardware platform that supports the ISA 3.0
@@ -21582,7 +21496,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, triop( Iop_AddF128, set_round_to_Oddmode(),
mkexpr( vA ), mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x024: // xsmulqp (VSX Scalar Multiply Quad-Precision[using round to Odd])
@@ -21600,7 +21514,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, triop( Iop_MulF128, set_round_to_Oddmode(), mkexpr( vA ),
mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x184: // xsmaddqp (VSX Scalar Multiply add Quad-Precision[using round to Odd])
@@ -21625,7 +21539,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
qop( Iop_MAddF128, set_round_to_Oddmode(), mkexpr( vA ),
mkexpr( vC ), mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x1A4: // xsmsubqp (VSX Scalar Multiply Subtract Quad-Precision[using round to Odd])
@@ -21649,7 +21563,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
qop( Iop_MSubF128, set_round_to_Oddmode(),
mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x1C4: // xsnmaddqp (VSX Scalar Negative Multiply Add Quad-Precision[using round to Odd])
@@ -21673,7 +21587,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
qop( Iop_NegMAddF128, set_round_to_Oddmode(),
mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x1E4: // xsmsubqp (VSX Scalar Negatve Multiply Subtract Quad-Precision[using round to Odd])
@@ -21697,7 +21611,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
qop( Iop_NegMSubF128, set_round_to_Oddmode(),
mkexpr( vA ), mkexpr( vC ), mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x204: // xssubqp (VSX Scalar Subtract Quad-Precision[using round to Odd])
@@ -21714,7 +21628,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, triop( Iop_SubF128, set_round_to_Oddmode(), mkexpr( vA ),
mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x224: // xsdivqp (VSX Scalar Divide Quad-Precision[using round to Odd])
@@ -21731,7 +21645,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, triop( Iop_DivF128, set_round_to_Oddmode(), mkexpr( vA ),
mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 0x324: // xssqrtqp (VSX Scalar Square root Quad-Precision[using round to Odd])
@@ -21752,7 +21666,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, binop( Iop_SqrtF128, set_round_to_Oddmode(),
mkexpr( vB ) ) );
}
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
} /* end case 27 */
default:
@@ -21783,7 +21697,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( tmp, unop( Iop_ReinterpF64asI64,
unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
assign( vT, unop( Iop_I64UtoF128, mkexpr( tmp ) ) );
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 9: // xsvqpswz VSX Scalar Truncate & Convert Quad-Precision
@@ -21803,7 +21717,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( tmp, unop( Iop_ReinterpF64asI64,
unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
assign( vT, unop( Iop_I64StoF128, mkexpr( tmp ) ) );
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 17: // xsvqpudz VSX Scalar Truncate & Convert Quad-Precision
@@ -21855,7 +21769,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( tmp, unop( Iop_ReinterpF64asI64,
unop( Iop_F128HItoF64, mkexpr( vT ) ) ) );
- generate_store_FPRF( Ity_I64, tmp );
+ generate_store_FPRF( Ity_I64, tmp, vbi );
break;
}
case 22: // xscvdpqp VSX Scalar Convert from Double-Precision
@@ -21866,7 +21780,7 @@ dis_vx_Floating_Point_Arithmetic_quad_precision( UInt theInstr )
assign( vT, unop( Iop_F64toF128,
unop( Iop_F128HItoF64, mkexpr( vB ) ) ) );
- generate_store_FPRF( Ity_F128, vT );
+ generate_store_FPRF( Ity_F128, vT, vbi );
break;
}
case 25: // xsvqpsdz VSX Scalar Truncate & Convert Quad-Precision
@@ -28199,13 +28113,13 @@ DisResult disInstr_PPC_WRK (
UInt vsxOpc2;
if (( opc2hi == 13 ) && ( opc2lo == 5)) { //xvtstdcsp
- if (dis_vxs_misc(theInstr, 0x354, allow_isa_3_0))
+ if (dis_vxs_misc(theInstr, abiinfo, 0x354, allow_isa_3_0))
goto decode_success;
goto decode_failure;
}
if (( opc2hi == 15 ) && ( opc2lo == 5)) { //xvtstdcdp
- if (dis_vxs_misc(theInstr, 0x3D4, allow_isa_3_0))
+ if (dis_vxs_misc(theInstr, abiinfo, 0x3D4, allow_isa_3_0))
goto decode_success;
goto decode_failure;
}
@@ -28221,7 +28135,7 @@ DisResult disInstr_PPC_WRK (
/* This is a special case of the XX1 form where the RA, RB
* fields hold an immediate value.
*/
- if (dis_vxs_misc(theInstr, opc2, allow_isa_3_0)) goto decode_success;
+ if (dis_vxs_misc(theInstr, abiinfo, opc2, allow_isa_3_0)) goto decode_success;
goto decode_failure;
}
@@ -28231,7 +28145,8 @@ DisResult disInstr_PPC_WRK (
case 0x8: case 0x28: case 0x48: case 0xc8: // xxsldwi, xxpermdi, xxmrghw, xxmrglw
case 0x068: case 0xE8: // xxperm, xxpermr
case 0x018: case 0x148: // xxsel, xxspltw
- if (dis_vx_permute_misc(theInstr, vsxOpc2)) goto decode_success;
+ if (dis_vx_permute_misc(theInstr, vsxOpc2 ))
+ goto decode_success;
goto decode_failure;
case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor,
case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc
@@ -28255,7 +28170,7 @@ DisResult disInstr_PPC_WRK (
case 0x354: // xvtstdcsp
case 0x360:case 0x396: // xviexpsp, xsiexpdp
case 0x3D4: case 0x3E0: // xvtstdcdp, xviexpdp
- if (dis_vxs_misc(theInstr, vsxOpc2, allow_isa_3_0))
+ if (dis_vxs_misc(theInstr, abiinfo, vsxOpc2, allow_isa_3_0))
goto decode_success;
goto decode_failure;
case 0x08C: case 0x0AC: // xscmpudp, xscmpodp
@@ -28409,7 +28324,7 @@ DisResult disInstr_PPC_WRK (
case 0x5: // xsrqpi, xsrqpix
case 0x25: // xsrqpxp
if ( !mode64 || !allow_isa_3_0 ) goto decode_failure;
- if ( dis_vx_Scalar_Round_to_quad_integer( theInstr ) )
+ if ( dis_vx_Scalar_Round_to_quad_integer( theInstr, abiinfo ) )
goto decode_success;
goto decode_failure;
default:
@@ -28531,7 +28446,8 @@ DisResult disInstr_PPC_WRK (
case 0x324: // xsabsqp, xsxexpqp,xsnabsqp, xsnegqp, xsxsigqp
if ( inst_select == 27 ) { // xssqrtqp
- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) )
+ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr,
+ abiinfo ) )
goto decode_success;
}
@@ -28566,7 +28482,8 @@ DisResult disInstr_PPC_WRK (
case 0x344: // xscvudqp, xscvsdqp, xscvqpdp, xscvqpdpo, xsvqpdp
// xscvqpswz, xscvqpuwz, xscvqpudz, xscvqpsdz
if ( !mode64 || !allow_isa_3_0 ) goto decode_failure;
- if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr ) )
+ if ( dis_vx_Floating_Point_Arithmetic_quad_precision( theInstr,
+ abiinfo ) )
goto decode_success;
goto decode_failure;
commit a1d03d0d11c0b31a6d9f57baa4d46317fdd5f6ef
Author: Carl Love <carll@us.ibm.com>
Date: Tue Oct 3 15:09:22 2017 -0500
PPC64, Use the vperm code to implement the xxperm inst.
The current xxperm instruction implementation generates a huge
number of Iops to explicitly do the permutation. The code
was changed to use the Iop_Perm8x16 which is much more efficient
so temporary memory doesn't get exhausted.
Bugzilla 385208
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 0dae368..1373d1c 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -22319,15 +22319,17 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
case 0x68: // xxperm (VSX Permute )
case 0xE8: // xxpermr (VSX Permute right-index )
{
- int i;
- IRTemp new_Vt[17];
- IRTemp perm_val[16];
- IRTemp perm_val_gt16[16];
- IRTemp tmp_val[16];
- IRTemp perm_idx[16];
- IRTemp perm_mask = newTemp( Ity_V128 );
- IRTemp val_mask = newTemp( Ity_V128 );
- int dest_shift_amount = 0;
+
+ /* The xxperm instruction performs the same operation as
+ the vperm except the xxperm operates on the VSR register
+ file. while vperm operates on the VR register file.
+ Lets borrow some code here from vperm. The mapping of
+ the source registers is also a little different.
+ */
+ IRTemp a_perm = newTemp(Ity_V128);
+ IRTemp b_perm = newTemp(Ity_V128);
+ IRTemp mask = newTemp(Ity_V128);
+ IRTemp perm_val = newTemp(Ity_V128);
if ( opc2 == 0x68 ) {
DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
@@ -22337,119 +22339,40 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
DIP("xxpermr v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
}
- new_Vt[0] = newTemp( Ity_V128 );
-
assign( vT, getVSReg( XT ) );
- assign( new_Vt[0], binop( Iop_64HLtoV128,
- mkU64( 0x0 ), mkU64( 0x0 ) ) );
- assign( perm_mask, binop( Iop_64HLtoV128,
- mkU64( 0x0 ), mkU64( 0x1F ) ) );
- assign( val_mask, binop( Iop_64HLtoV128,
- mkU64( 0x0 ), mkU64( 0xFF ) ) );
-
- /* For each permute index in XB, the permute list, select the byte
- * from XA indexed by the permute index if the permute index is less
- * then 16. Copy the selected byte to the destination location in
- * the result.
- */
- for ( i = 0; i < 16; i++ ) {
- perm_val_gt16[i] = newTemp( Ity_V128 );
- perm_val[i] = newTemp( Ity_V128 );
- perm_idx[i] = newTemp( Ity_I8 );
- tmp_val[i] = newTemp( Ity_V128 );
- new_Vt[i+1] = newTemp( Ity_V128 );
-
- /* create mask to extract the permute index value from vB,
- * store value in least significant bits of perm_val
- */
- if ( opc2 == 0x68 )
- /* xxperm, the perm value is the index value in XB */
- assign( perm_val[i], binop( Iop_ShrV128,
- binop( Iop_AndV128,
- mkexpr(vB),
- binop( Iop_ShlV128,
- mkexpr( perm_mask ),
- mkU8( (15 - i) * 8 ) ) ),
- mkU8( (15 - i) * 8 ) ) );
+ if ( opc2 == 0x68 ) // xxperm
+ assign( perm_val,
+ binop( Iop_AndV128, mkexpr( vB ),
+ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) );
- else
- /* xxpermr, the perm value is 31 - index value in XB */
- assign( perm_val[i],
- binop( Iop_Sub8x16,
- binop( Iop_64HLtoV128,
- mkU64( 0 ), mkU64( 31 ) ),
- binop( Iop_ShrV128,
- binop( Iop_AndV128,
- mkexpr( vB ),
- binop( Iop_ShlV128,
- mkexpr( perm_mask ),
- mkU8( ( 15 - i ) * 8 ) ) ),
- mkU8( ( 15 - i ) * 8 ) ) ) );
-
- /* Determine if the perm_val[] > 16. If it is, then the value
- * will come from xT otherwise it comes from xA. Either way,
- * create the mask to get the value from the source using the
- * lower 3 bits of perm_val[]. Create a 128 bit mask from the
- * upper bit of perm_val[] to be used to select from xT or xA.
- */
- assign( perm_val_gt16[i],
- binop(Iop_64HLtoV128,
- unop( Iop_1Sto64,
- unop( Iop_64to1,
- unop( Iop_V128to64,
- binop( Iop_ShrV128,
- mkexpr( perm_val[i] ),
- mkU8( 4 ) ) ) ) ),
- unop( Iop_1Sto64,
- unop( Iop_64to1,
- unop( Iop_V128to64,
- binop( Iop_ShrV128,
- mkexpr( perm_val[i] ),
- mkU8( 4 ) ) ) ) ) ) );
-
- assign( perm_idx[i],
- unop(Iop_32to8,
- binop( Iop_Mul32,
- binop( Iop_Sub32,
- mkU32( 15 ),
- unop( Iop_64to32,
- binop( Iop_And64,
- unop( Iop_V128to64,
- mkexpr( perm_val[i] ) ),
- mkU64( 0xF ) ) ) ),
- mkU32( 8 ) ) ) );
-
- dest_shift_amount = ( 15 - i )*8;
-
- /* Use perm_val_gt16 to select value from vA or vT */
- assign( tmp_val[i],
- binop( Iop_ShlV128,
- binop( Iop_ShrV128,
- binop( Iop_OrV128,
- binop( Iop_AndV128,
- mkexpr( vA ),
- binop( Iop_AndV128,
- unop( Iop_NotV128,
- mkexpr( perm_val_gt16[i] ) ),
- binop( Iop_ShlV128,
- mkexpr( val_mask ),
- mkexpr( perm_idx[i] ) ) ) ),
- binop( Iop_AndV128,
- mkexpr( vT ),
- binop( Iop_AndV128,
- mkexpr( perm_val_gt16[i] ),
- binop( Iop_ShlV128,
- mkexpr( val_mask ),
- mkexpr( perm_idx[i] ) ) ) ) ),
- mkexpr( perm_idx[i] ) ),
- mkU8( dest_shift_amount ) ) );
-
- assign( new_Vt[i+1], binop( Iop_OrV128,
- mkexpr( tmp_val[i] ),
- mkexpr( new_Vt[i] ) ) );
- }
- putVSReg( XT, mkexpr( new_Vt[16] ) );
+ else // xxpermr
+ assign( perm_val,
+ binop( Iop_Sub16x8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x1F1F1F1F1F1F1F1F ),
+ mkU64( 0x1F1F1F1F1F1F1F1F ) ),
+ binop( Iop_AndV128, mkexpr( vB ),
+ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
+
+ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
+ IR specifies, and also to hide irrelevant bits from
+ memcheck.
+ */
+ assign( a_perm,
+ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) );
+ assign( b_perm,
+ binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) );
+ assign( mask, binop( Iop_SarN8x16,
+ binop( Iop_ShlN8x16, mkexpr( perm_val ),
+ mkU8( 3 ) ),
+ mkU8( 7 ) ) );
+ // dst = (a & ~mask) | (b & mask)
+ putVSReg( XT, binop( Iop_OrV128,
+ binop( Iop_AndV128, mkexpr( a_perm ),
+ unop( Iop_NotV128, mkexpr( mask ) ) ),
+ binop( Iop_AndV128, mkexpr( b_perm ),
+ mkexpr( mask ) ) ) );
break;
}
commit b0aef250a74804423341b3ce804355037211e330
Author: Carl Love <carll@us.ibm.com>
Date: Tue Oct 3 15:18:09 2017 -0500
PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16.
The current implementation will generate a lot of Iops. The number
of generated Iops can lead to Valgrind running out of temporary space.
See bugzilla https://bugs.kde.org/show_bug.cgi?id=385208 as an example
of the issue. Using Iop_Perm8x16 reduces the number of Iops significantly.
bugzilla 385210
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 1373d1c..1785959 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -24107,107 +24107,40 @@ static Bool dis_av_permute ( UInt theInstr )
}
case 0x3B: { // vpermr (Vector Permute Right-indexed)
- int i;
- IRTemp new_Vt[17];
- IRTemp tmp[16];
- IRTemp index[16];
- IRTemp index_gt16[16];
- IRTemp mask[16];
-
- DIP("vpermr v%d,v%d,v%d,v%d\n", vD_addr, vA_addr, vB_addr, vC_addr);
-
- new_Vt[0] = newTemp( Ity_V128 );
- assign( new_Vt[0], binop( Iop_64HLtoV128,
- mkU64( 0x0 ),
- mkU64( 0x0 ) ) );
-
- for ( i = 0; i < 16; i++ ) {
- index_gt16[i] = newTemp( Ity_V128 );
- mask[i] = newTemp( Ity_V128 );
- index[i] = newTemp( Ity_I32 );
- tmp[i] = newTemp( Ity_V128 );
- new_Vt[i+1] = newTemp( Ity_V128 );
-
- assign( index[i],
- binop( Iop_Sub32,
- mkU32( 31 ),
- unop( Iop_64to32,
- unop( Iop_V128to64,
- binop( Iop_ShrV128,
- binop( Iop_AndV128,
- binop( Iop_ShlV128,
- binop( Iop_64HLtoV128,
- mkU64( 0x0 ),
- mkU64( 0x3F ) ),
- mkU8( (15 - i) * 8 ) ),
- mkexpr( vC ) ),
- mkU8( (15 - i) * 8 ) ) ) ) ) );
-
- /* Determine if index < 16, src byte is vA[index], otherwise
- * vB[31-index]. Check if msb of index is 1 or not.
- */
- assign( index_gt16[i],
- binop( Iop_64HLtoV128,
- unop( Iop_1Sto64,
- unop( Iop_32to1,
- binop( Iop_Shr32,
- mkexpr( index[i] ),
- mkU8( 4 ) ) ) ),
- unop( Iop_1Sto64,
- unop( Iop_32to1,
- binop( Iop_Shr32,
- mkexpr( index[i] ),
- mkU8( 4 ) ) ) ) ) );
- assign( mask[i],
- binop( Iop_ShlV128,
- binop( Iop_64HLtoV128,
- mkU64( 0x0 ),
- mkU64( 0xFF ) ),
- unop( Iop_32to8,
- binop( Iop_Mul32,
- binop( Iop_Sub32,
- mkU32( 15 ),
- binop( Iop_And32,
- mkexpr( index[i] ),
- mkU32( 0xF ) ) ),
- mkU32( 8 ) ) ) ) );
-
- /* Extract the indexed byte from vA and vB using the lower 4-bits
- * of the index. Then use the index_gt16 mask to select vA if the
- * index < 16 or vB if index > 15. Put the selected byte in the
- * least significant byte.
- */
- assign( tmp[i],
- binop( Iop_ShrV128,
- binop( Iop_OrV128,
- binop( Iop_AndV128,
- binop( Iop_AndV128,
- mkexpr( mask[i] ),
- mkexpr( vA ) ),
- unop( Iop_NotV128,
- mkexpr( index_gt16[i] ) ) ),
- binop( Iop_AndV128,
- binop( Iop_AndV128,
- mkexpr( mask[i] ),
- mkexpr( vB ) ),
- mkexpr( index_gt16[i] ) ) ),
- unop( Iop_32to8,
- binop( Iop_Mul32,
- binop( Iop_Sub32,
- mkU32( 15 ),
- binop( Iop_And32,
- mkexpr( index[i] ),
- mkU32( 0xF ) ) ),
- mkU32( 8 ) ) ) ) );
-
- /* Move the selected byte to the position to store in the result */
- assign( new_Vt[i+1], binop( Iop_OrV128,
- binop( Iop_ShlV128,
- mkexpr( tmp[i] ),
- mkU8( (15 - i) * 8 ) ),
- mkexpr( new_Vt[i] ) ) );
- }
- putVReg( vD_addr, mkexpr( new_Vt[16] ) );
+ /* limited to two args for IR, so have to play games... */
+ IRTemp a_perm = newTemp( Ity_V128 );
+ IRTemp b_perm = newTemp( Ity_V128 );
+ IRTemp mask = newTemp( Ity_V128 );
+ IRTemp vC_andF = newTemp( Ity_V128 );
+
+ DIP( "vpermr v%d,v%d,v%d,v%d\n",
+ vD_addr, vA_addr, vB_addr, vC_addr);
+ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
+ IR specifies, and also to hide irrelevant bits from
+ memcheck.
+ */
+
+ assign( vC_andF,
+ binop( Iop_Sub16x8,
+ binop( Iop_64HLtoV128,
+ mkU64( 0x1F1F1F1F1F1F1F1F ),
+ mkU64( 0x1F1F1F1F1F1F1F1F ) ),
+ binop( Iop_AndV128, mkexpr( vC ),
+ unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
+ assign( a_perm,
+ binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) );
+ assign( b_perm,
+ binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) );
+ // mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0
+ assign( mask, binop(Iop_SarN8x16,
+ binop( Iop_ShlN8x16, mkexpr( vC_andF ),
+ mkU8( 3 ) ), mkU8( 7 ) ) );
+ // dst = (a & ~mask) | (b & mask)
+ putVReg( vD_addr, binop( Iop_OrV128,
+ binop( Iop_AndV128, mkexpr( a_perm ),
+ unop( Iop_NotV128, mkexpr( mask ) ) ),
+ binop( Iop_AndV128, mkexpr( b_perm ),
+ mkexpr( mask ) ) ) );
return True;
}
commit f0c4da68ca9e8c99f55965d8e074273a33ab916d
Author: Carl Love <cel@us.ibm.com>
Date: Tue Oct 3 10:49:48 2017 -0500
PPC64, Fix bug in vperm instruction.
The ISA says:
Let the source vector be the concatenation of the
contents of VR[VRA] followed by the contents of
VR[VRB].
For each integer value i from 0 to 15, do the following.
Let index be the value specified by bits 3:7 of byte
element i of VR[VRC].
So, the index value is 5-bits wide ([3:7]), not 4-bits wide.
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 1785959..97664c2 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -24047,12 +24047,12 @@ static Bool dis_av_permute ( UInt theInstr )
IRTemp vC_andF = newTemp(Ity_V128);
DIP("vperm v%d,v%d,v%d,v%d\n",
vD_addr, vA_addr, vB_addr, vC_addr);
- /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
+ /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
IR specifies, and also to hide irrelevant bits from
memcheck */
assign( vC_andF,
binop(Iop_AndV128, mkexpr(vC),
- unop(Iop_Dup8x16, mkU8(0xF))) );
+ unop(Iop_Dup8x16, mkU8(0x1F))) );
assign( a_perm,
binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) );
assign( b_perm,
commit 5398a9f9cb9db6805df03e43258e65fa799a7caa
Author: Carl Love <carll@us.ibm.com>
Date: Wed Oct 4 10:24:36 2017 -0500
PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions.
These are Power 9 instructions.
Add test cases for the new instructions to test_isa_3_0.c
Bugzilla 385183.
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 97664c2..6b2157d 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -3629,18 +3629,22 @@ static IRExpr * fp_exp_part( IRType size, IRTemp src )
/* 16-bit floating point number is stored in the lower 16-bits of 32-bit value */
#define I16_EXP_MASK 0x7C00
#define I16_FRACTION_MASK 0x03FF
+#define I16_MSB_FRACTION_MASK 0x0200
#define I32_EXP_MASK 0x7F800000
#define I32_FRACTION_MASK 0x007FFFFF
+#define I32_MSB_FRACTION_MASK 0x00400000
#define I64_EXP_MASK 0x7FF0000000000000ULL
#define I64_FRACTION_MASK 0x000FFFFFFFFFFFFFULL
+#define I64_MSB_FRACTION_MASK 0x0008000000000000ULL
#define V128_EXP_MASK 0x7FFF000000000000ULL
#define V128_FRACTION_MASK 0x0000FFFFFFFFFFFFULL /* upper 64-bit fractional mask */
+#define V128_MSB_FRACTION_MASK 0x0000800000000000ULL /* upper 64-bit fractional mask */
void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
- IRTemp *zero );
+ IRTemp *msb_frac_mask, IRTemp *zero );
void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
- IRTemp *zero ) {
+ IRTemp *msb_frac_mask, IRTemp *zero ) {
vassert( ( size == Ity_I16 ) || ( size == Ity_I32 )
|| ( size == Ity_I64 ) || ( size == Ity_V128 ) );
@@ -3649,37 +3653,45 @@ void setup_value_check_args( IRType size, IRTemp *exp_mask, IRTemp *frac_mask,
/* The 16-bit floating point value is in the lower 16-bits of
the 32-bit input value */
*frac_mask = newTemp( Ity_I32 );
+ *msb_frac_mask = newTemp( Ity_I32 );
*exp_mask = newTemp( Ity_I32 );
*zero = newTemp( Ity_I32 );
assign( *exp_mask, mkU32( I16_EXP_MASK ) );
assign( *frac_mask, mkU32( I16_FRACTION_MASK ) );
+ assign( *msb_frac_mask, mkU32( I16_MSB_FRACTION_MASK ) );
assign( *zero, mkU32( 0 ) );
} else if( size == Ity_I32 ) {
*frac_mask = newTemp( Ity_I32 );
+ *msb_frac_mask = newTemp( Ity_I32 );
*exp_mask = newTemp( Ity_I32 );
*zero = newTemp( Ity_I32 );
assign( *exp_mask, mkU32( I32_EXP_MASK ) );
assign( *frac_mask, mkU32( I32_FRACTION_MASK ) );
+ assign( *msb_frac_mask, mkU32( I32_MSB_FRACTION_MASK ) );
assign( *zero, mkU32( 0 ) );
} else if( size == Ity_I64 ) {
*frac_mask = newTemp( Ity_I64 );
+ *msb_frac_mask = newTemp( Ity_I64 );
*exp_mask = newTemp( Ity_I64 );
*zero = newTemp( Ity_I64 );
assign( *exp_mask, mkU64( I64_EXP_MASK ) );
assign( *frac_mask, mkU64( I64_FRACTION_MASK ) );
+ assign( *msb_frac_mask, mkU64( I64_MSB_FRACTION_MASK ) );
assign( *zero, mkU64( 0 ) );
} else {
/* V128 is converted to upper and lower 64 bit values, */
/* uses 64-bit operators and temps */
*frac_mask = newTemp( Ity_I64 );
+ *msb_frac_mask = newTemp( Ity_I64 );
*exp_mask = newTemp( Ity_I64 );
*zero = newTemp( Ity_I64 );
assign( *exp_mask, mkU64( V128_EXP_MASK ) );
/* upper 64-bit fractional mask */
assign( *frac_mask, mkU64( V128_FRACTION_MASK ) );
+ assign( *msb_frac_mask, mkU64( V128_MSB_FRACTION_MASK ) );
assign( *zero, mkU64( 0 ) );
}
}
@@ -3801,9 +3813,10 @@ static IRExpr *fractional_part_compare( IRType size, IRTemp src,
static IRExpr * is_Inf( IRType size, IRTemp src )
{
IRExpr *max_exp, *zero_frac;
- IRTemp exp_mask, frac_mask, zero;
+ IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+ &zero );
/* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
@@ -3818,9 +3831,10 @@ static IRExpr * is_Inf( IRType size, IRTemp src )
static IRExpr * is_Zero( IRType size, IRTemp src )
{
IRExpr *zero_exp, *zero_frac;
- IRTemp exp_mask, frac_mask, zero;
+ IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+ &zero );
/* check the exponent is all zeros, i.e. (exp AND exp_mask) = zero */
zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
@@ -3837,9 +3851,10 @@ static IRExpr * is_Zero( IRType size, IRTemp src )
static IRExpr * is_NaN( IRType size, IRTemp src )
{
IRExpr *max_exp, *not_zero_frac;
- IRTemp exp_mask, frac_mask, zero;
+ IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+ &zero );
/* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
@@ -3852,13 +3867,37 @@ static IRExpr * is_NaN( IRType size, IRTemp src )
return mkAND1( max_exp, not_zero_frac );
}
+static IRExpr * is_sNaN( IRType size, IRTemp src )
+{
+ IRExpr *max_exp, *not_zero_frac, *msb_zero;
+ IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
+
+ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+ &zero );
+
+ /* check exponent is all ones, i.e. (exp AND exp_mask) = exp_mask */
+ max_exp = exponent_compare( size, src, exp_mask, mkexpr( exp_mask ) );
+
+ /* Most significant fractional bit is zero for sNaN */
+ msb_zero = fractional_part_compare ( size, src, msb_frac_mask,
+ mkexpr( zero ) );
+
+ /* check fractional part is not zero */
+ not_zero_frac = unop( Iop_Not1,
+ fractional_part_compare( size, src, frac_mask,
+ mkexpr( zero ) ) );
+
+ return mkAND1( msb_zero, mkAND1( max_exp, not_zero_frac ) );
+}
+
/* Denormalized number has a zero exponent and non zero fraction. */
static IRExpr * is_Denorm( IRType size, IRTemp src )
{
IRExpr *zero_exp, *not_zero_frac;
- IRTemp exp_mask, frac_mask, zero;
+ IRTemp exp_mask, frac_mask, msb_frac_mask, zero;
- setup_value_check_args( size, &exp_mask, &frac_mask, &zero );
+ setup_value_check_args( size, &exp_mask, &frac_mask, &msb_frac_mask,
+ &zero );
/* check exponent is all zeros */
zero_exp = exponent_compare( size, src, exp_mask, mkexpr( zero ) );
@@ -19712,6 +19751,216 @@ dis_vxs_misc( UInt theInstr, const VexAbiInfo* vbi, UInt opc2,
}
/*
+ * VSX vector miscellaneous instructions
+ */
+
+static Bool
+dis_vx_misc ( UInt theInstr, UInt opc2 )
+{
+ /* XX3-Form */
+ UChar XT = ifieldRegXT ( theInstr );
+ UChar XA = ifieldRegXA ( theInstr );
+ UChar XB = ifieldRegXB ( theInstr );
+ IRTemp vA = newTemp( Ity_V128 );
+ IRTemp vB = newTemp( Ity_V128 );
+ IRTemp src1 = newTemp(Ity_I64);
+ IRTemp src2 = newTemp(Ity_I64);
+ IRTemp result_mask = newTemp(Ity_I64);
+ IRTemp cmp_mask = newTemp(Ity_I64);
+ IRTemp nan_mask = newTemp(Ity_I64);
+ IRTemp snan_mask = newTemp(Ity_I64);
+ IRTemp word_result = newTemp(Ity_I64);
+ IRTemp check_result = newTemp(Ity_I64);
+ IRTemp xT = newTemp( Ity_V128 );
+ IRTemp nan_cmp_value = newTemp(Ity_I64);
+ UInt trap_enabled = 0; /* 0 - trap enabled is False */
+
+ assign( vA, getVSReg( XA ) );
+ assign( vB, getVSReg( XB ) );
+ assign( xT, getVSReg( XT ) );
+
+ assign(src1, unop( Iop_V128HIto64, mkexpr( vA ) ) );
+ assign(src2, unop( Iop_V128HIto64, mkexpr( vB ) ) );
+
+ assign( nan_mask,
+ binop( Iop_Or64,
+ unop( Iop_1Sto64, is_NaN( Ity_I64, src1 ) ),
+ unop( Iop_1Sto64, is_NaN( Ity_I64, src2 ) ) ) );
+
+ if ( trap_enabled == 0 )
+ /* Traps on invalid operation are assumed not enabled, assign
+ result of comparison to xT.
+ */
+ assign( snan_mask, mkU64( 0 ) );
+
+ else
+ assign( snan_mask,
+ binop( Iop_Or64,
+ unop( Iop_1Sto64, is_sNaN( Ity_I64, src1 ) ),
+ unop( Iop_1Sto64, is_sNaN( Ity_I64, src2 ) ) ) );
+
+ assign (result_mask, binop( Iop_Or64,
+ mkexpr( snan_mask ),
+ mkexpr( nan_mask ) ) );
+
+ switch (opc2) {
+ case 0xC: //xscmpeqdp
+ {
+ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
+ /* extract double-precision floating point source values from
+ double word 0 */
+
+ /* result of Iop_CmpF64 is 0x40 if operands are equal,
+ mask is all 1's if equal. */
+
+ assign( cmp_mask,
+ unop( Iop_1Sto64,
+ unop(Iop_32to1,
+ binop(Iop_Shr32,
+ binop( Iop_CmpF64,
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src1 ) ),
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src2 ) ) ),
+ mkU8( 6 ) ) ) ) );
+
+ assign( word_result,
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( cmp_mask ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+ binop( Iop_And64,
+ unop( Iop_Not64, mkexpr( cmp_mask ) ),
+ mkU64( 0x0 ) ) ) );
+ assign( nan_cmp_value, mkU64( 0 ) );
+ break;
+ }
+
+ case 0x2C: //xscmpgtdp
+ {
+ DIP("xscmpgtdp v%d,v%d,v%d\n", XT, XA, XB);
+ /* Test for src1 > src2 */
+
+ /* Result of Iop_CmpF64 is 0x1 if op1 < op2, set mask to all 1's. */
+ assign( cmp_mask,
+ unop( Iop_1Sto64,
+ unop(Iop_32to1,
+ binop(Iop_CmpF64,
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src2 ) ),
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src1 ) ) ) ) ) );
+ assign( word_result,
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( cmp_mask ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+ binop( Iop_And64,
+ unop( Iop_Not64, mkexpr( cmp_mask ) ),
+ mkU64( 0x0 ) ) ) );
+ assign( nan_cmp_value, mkU64( 0 ) );
+ break;
+ }
+
+ case 0x4C: //xscmpgedp
+ {
+ DIP("xscmpeqdp v%d,v%d,v%d\n", XT, XA, XB);
+ /* compare src 1 >= src 2 */
+ /* result of Iop_CmpF64 is 0x40 if operands are equal,
+ mask is all 1's if equal. */
+ assign( cmp_mask,
+ unop( Iop_1Sto64,
+ unop(Iop_32to1,
+ binop( Iop_Or32,
+ binop( Iop_Shr32,
+ binop(Iop_CmpF64, /* EQ test */
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src1 ) ),
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src2 ) ) ),
+ mkU8( 6 ) ),
+ binop(Iop_CmpF64, /* src2 < src 1 test */
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src2 ) ),
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src1 ) ) ) ) ) ) );
+ assign( word_result,
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( cmp_mask ),
+ mkU64( 0xFFFFFFFFFFFFFFFF ) ),
+ binop( Iop_And64,
+ unop( Iop_Not64, mkexpr( cmp_mask ) ),
+ mkU64( 0x0 ) ) ) );
+ assign( nan_cmp_value, mkU64( 0 ) );
+ break;
+ }
+
+ case 0x220: //xsmincdp
+ {
+ DIP("xsmincdp v%d,v%d,v%d\n", XT, XA, XB);
+ /* extract double-precision floating point source values from
+ double word 0 */
+
+ /* result of Iop_CmpF64 is 0x1 if src1 less then src2, */
+ assign( cmp_mask,
+ unop( Iop_1Sto64,
+ unop( Iop_32to1,
+ binop(Iop_CmpF64,
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src1 ) ),
+ unop( Iop_ReinterpI64asF64,
+ mkexpr( src2 ) ) ) ) ) );
+ assign( word_result,
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( cmp_mask ), mkexpr( src1 ) ),
+ binop( Iop_And64,
+ unop( Iop_Not64, mkexpr( cmp_mask ) ),
+ mkexpr( src2 ) ) ) );
+ assign( nan_cmp_value, mkexpr( src2 ) );
+ break;
+ }
+
+ default:
+ vex_printf( "dis_vx_misc(ppc)(opc2)\n" );
+ return False;
+ }
+
+ /* If either argument is NaN, result is src2. If either argument is
+ SNaN, we are supposed to generate invalid operation exception.
+ Currently don't support generating exceptions. In case of an
+ trap enabled invalid operation (SNaN) XT is not changed. The
+ snan_mask is setup appropriately for trap enabled or not.
+ */
+ assign( check_result,
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( snan_mask ),
+ unop( Iop_V128HIto64, mkexpr( xT ) ) ),
+ binop( Iop_And64, unop( Iop_Not64,
+ mkexpr( snan_mask ) ),
+ binop( Iop_Or64,
+ binop( Iop_And64, mkexpr( nan_mask ),
+ mkexpr( nan_cmp_value ) ),
+ binop( Iop_And64,
+ unop( Iop_Not64,
+ mkexpr( nan_mask ) ),
+ mkU64( 0 ) ) ) ) ) );
+
+ /* If SNaN is true, then the result is unchanged if a trap-enabled
+ Invalid Operation occurs. Result mask already setup for trap-enabled
+ case.
+ */
+ putVSReg( XT,
+ binop( Iop_64HLtoV128,
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ unop( Iop_Not64, mkexpr( result_mask ) ),
+ mkexpr( word_result ) ),
+ binop( Iop_And64,
+ mkexpr( result_mask ),
+ mkexpr( check_result ) ) ),
+ mkU64( 0 ) ) );
+ return True;
+}
+
+/*
* VSX Logical Instructions
*/
static Bool
@@ -27319,12 +27568,15 @@ static struct vsx_insn vsx_xx3[] = {
{ 0x0, "xsaddsp" },
{ 0x4, "xsmaddasp" },
{ 0x9, "xsmaddmsp" },
+ { 0xC, "xscmpeqdp" },
{ 0x20, "xssubsp" },
{ 0x24, "xsmaddmsp" },
+ { 0x2C, "xscmpgtdp" },
{ 0x3A, "xxpermr" },
{ 0x40, "xsmulsp" },
{ 0x44, "xsmsubasp" },
{ 0x48, "xxmrghw" },
+ { 0x4C, "xscmpgedp" },
{ 0x60, "xsdivsp" },
{ 0x64, "xsmsubmsp" },
{ 0x68, "xxperm" },
@@ -27371,6 +27623,7 @@ static struct vsx_insn vsx_xx3[] = {
{ 0x1f4, "xvtdivdp" },
{ 0x204, "xsnmaddasp" },
{ 0x208, "xxland" },
+ { 0x220, "xsmincdp" },
{ 0x224, "xsnmaddmsp" },
{ 0x228, "xxlandc" },
{ 0x244, "xsnmsubasp" },
@@ -28004,9 +28257,13 @@ DisResult disInstr_PPC_WRK (
if (dis_vx_permute_misc(theInstr, vsxOpc2 ))
goto decode_success;
goto decode_failure;
+ case 0xC: case 0x2C: case 0x4C: // xscmpeqdp, xscmpgtdp, xscmpgedp
+ case 0x220: //xsmincdp
+ if (dis_vx_misc(theInstr, vsxOpc2)) goto decode_success;
+ goto decode_failure;
case 0x268: case 0x248: case 0x288: // xxlxor, xxlor, xxlnor,
- case 0x208: case 0x228: case 0x2A8: // xxland, xxlandc, xxlorc
- case 0x2C8: case 0x2E8: // xxlnand, xxleqv
+ case 0x208: case 0x228: // xxland, xxlandc
+ case 0x2A8: case 0x2C8: case 0x2E8: // xxlorc, xxlnand, xxleqv
if (dis_vx_logic(theInstr, vsxOpc2)) goto decode_success;
goto decode_failure;
case 0x0ec: // xscmpexpdp
diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
index 6e4e7dc..4b07f8b 100644
--- a/none/tests/ppc64/test_isa_3_0.c
+++ b/none/tests/ppc64/test_isa_3_0.c
@@ -1172,8 +1172,28 @@ static void test_xscmpexpdp(void) {
};
}
-static test_list_t testgroup_vector_scalar_compare_exp_double[] = {
+static void test_xscmpeqdp(void) {
+ __asm__ __volatile__ ("xscmpeqdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xscmpgtdp(void) {
+ __asm__ __volatile__ ("xscmpgtdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xscmpgedp(void) {
+ __asm__ __volatile__ ("xscmpgedp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static void test_xsmincdp(void) {
+ __asm__ __volatile__ ("xsmincdp %x0, %x1, %x2 " : "+wa" (vec_xt): "ww" (vec_xa), "ww" (vec_xb));
+}
+
+static test_list_t testgroup_vector_scalar_compare_double[] = {
{ &test_xscmpexpdp , "xscmpexpdp " },
+ { &test_xscmpeqdp , "xscmpeqdp " },
+ { &test_xscmpgtdp , "xscmpgtdp " },
+ { &test_xscmpgedp , "xscmpgedp " },
+ { &test_xsmincdp , "xsmincdp " },
{ NULL , NULL },
};
@@ -2301,8 +2321,8 @@ static test_group_table_t all_tests[] = {
PPC_MISC | PPC_TWO_ARGS,
},
{
- testgroup_vector_scalar_compare_exp_double,
- "ppc vector scalar compare exponents doubles",
+ testgroup_vector_scalar_compare_double,
+ "ppc vector scalar compare doubles",
PPC_ALTIVEC_DOUBLE | PPC_COMPARE | PPC_COMPARE_ARGS,
},
{
@@ -3125,8 +3145,16 @@ static void testfunction_vector_scalar_two_quad (const char* instruction_name,
}
}
+/* helper macro. Use below to limit output to only dword[0] for the inputs
+ * to the instructions listed here. */
+#define instruction_only_uses_dword0_inputs(instruction_name) \
+ ((strncmp(instruction_name, "xscmpeqdp",9) == 0) || \
+ (strncmp(instruction_name, "xscmpgtdp",9) == 0) || \
+ (strncmp(instruction_name, "xscmpgedp",9) == 0) || \
+ (strncmp(instruction_name, "xsmincdp",8) == 0) )
+
static void
-testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
+testfunction_vector_scalar_compare_double (const char* instruction_name,
test_func_t test_function,
unsigned int ignore_test_flags){
int i,j;
@@ -3154,11 +3182,15 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
*/
SET_CR_ZERO
SET_FPSCR_ZERO
-
- printf("%s %016lx %016lx %016lx %016lx",
- instruction_name,
- vec_xa[0], vec_xa[1],
- vec_xb[0], vec_xb[1]);
+ if (instruction_only_uses_dword0_inputs(instruction_name)) {
+ printf("%s %016lx %016lx",
+ instruction_name, vec_xa[1], vec_xb[1]);
+ } else {
+ printf("%s %016lx %016lx %016lx %016lx",
+ instruction_name,
+ vec_xa[0], vec_xa[1],
+ vec_xb[0], vec_xb[1]);
+ }
if (verbose) printf(" cr#%d ", x_index);
@@ -3166,6 +3198,10 @@ testfunction_vector_scalar_compare_exp_double (const char* instruction_name,
(*test_function)();
+ if (instruction_only_uses_dword0_inputs(instruction_name)) {
+ printf("%016lx %016lx", vec_xt[0], vec_xt[1]);
+ }
+
dissect_fpscr(local_fpscr);
dissect_fpscr_result_value_class(local_fpscr);
dissect_cr_rn(local_cr, x_index);
@@ -4094,7 +4130,7 @@ static void do_tests ( insn_sel_flags_t seln_flags)
break;
case PPC_COMPARE_ARGS:
- group_function = &testfunction_vector_scalar_compare_exp_double;
+ group_function = &testfunction_vector_scalar_compare_double;
break;
default:
diff --git a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
index c4ad35f..7d3c94c 100644
--- a/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
+++ b/none/tests/ppc64/test_isa_3_0_altivec.stdout.exp-LE
@@ -53311,8 +53311,8 @@ stxvb16x 00101f0000101f02 00101f0800101f10 [ 0001020304050607 5555555555555555 0
00101f0800101f10 00101f0000101f02 [ 101f1000081f1000 021f1000001f1000 0000000000000000 ffffffffffffffff ]
All done. Tested 135 different instructions
-ppc vector scalar compare exponents doubles:
-Test instruction group [ppc vector scalar compare exponents doubles]
+ppc vector scalar compare doubles:
+Test instruction group [ppc vector scalar compare doubles]
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 0000000000000000 => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 0000000000000000 00007fffffffffff => FPCC-FE(EQ)
xscmpexpdp 0000000000000000 0000000000000000 00007fffffffffff 00007fffffffffff => FPCC-FE(EQ)
@@ -54275,7 +54275,3855 @@ xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff0000000000000
xscmpexpdp fff07fffffffffff fff07fffffffffff fff0000000000000 fff07fffffffffff => FPCC-FU(SO)
xscmpexpdp fff07fffffffffff fff07fffffffffff fff07fffffffffff fff07fffffffffff => FPCC-FU(SO)
-All done. Tested 136 different instructions
+xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8000000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0000000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 00007fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 00007fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff0000000000000 => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 0ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff0000000000000 fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff07fffffffffff => 0000000000000000 ffffffffffffffff FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 7ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 80007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 8ff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff fff07fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 00007fffffffffff => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xscmpeqdp 0ff07fffffffffff 0ff0000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
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+xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 8000000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 80007fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 8ff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 8ff07fffffffffff => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff0000000000000 fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 0000000000000000 => 0000000000000000 0000000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 00007fffffffffff => 0000000000000000 00007fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 0ff0000000000000 => 0000000000000000 0ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 0ff07fffffffffff => 0000000000000000 0ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff0000000000000 => 0000000000000000 7ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 7ff07fffffffffff => 0000000000000000 7ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8000000000000000 => 0000000000000000 8000000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 80007fffffffffff => 0000000000000000 80007fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8ff0000000000000 => 0000000000000000 8ff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff 8ff07fffffffffff => 0000000000000000 8ff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff0000000000000 => 0000000000000000 fff0000000000000 FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+xsmincdp fff07fffffffffff fff07fffffffffff => 0000000000000000 fff07fffffffffff FPCC-FU(SO)
+
+All done. Tested 140 different instructions
ppc vector scalar test data class tests:
Test instruction group [ppc vector scalar test data class tests]
xststdcqp 0000000000000000, 0000000000000000 => 0505050505050505, 0a0a0a0a0a0a0a0a
@@ -55453,7 +59301,7 @@ xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 000000000000
xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, 0000000000000000
xvtstdcdp 0000000000000000, ffff7fffffffffff => 0000000000000000, ffffffffffffffff
-All done. Tested 141 different instructions
+All done. Tested 145 different instructions
ppc vector scalar tests against float double two args :
Test instruction group [ppc vector scalar tests against float double two args ]
xsiexpdp r14 = 0x0, r15 = 0x0 0000000000000000 ffff7fffffffffff => 0000000000000000 0000000000000000
@@ -56261,4 +60109,4 @@ xvcvsphp vec_xb[1] = 0x7f8000007f800000, vec_xb[0] = 0xffffffffffffffff 7f800
xvcvsphp vec_xb[1] = 0x7fffff007fffff, vec_xb[0] = 0xffffffffffffffff 007fffff007fffff ffffffffffffffff => 0000000000000000 0000ffff0000ffff
xvcvsphp vec_xb[1] = 0x0, vec_xb[0] = 0xffffffffffffffff 0000000000000000 ffffffffffffffff => 0000000000000000 0000ffff0000ffff
-All done. Tested 146 different instructions
+All done. Tested 150 different instructions
commit c618e707d3e24853cd1e0b71deb981f2dc4ae8d4
Author: Carl Love <carll@us.ibm.com>
Date: Wed Oct 4 10:54:07 2017 -0500
PPC64, revert the change to vperm instruction.
The patch was in my git tree with the patch I intended to apply.
I didn't realize the patch was in the tree. Git applied both
patches. Still investigating the vperm change to see if it is
really needed.
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 6b2157d..b5b0d03 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -24296,12 +24296,12 @@ static Bool dis_av_permute ( UInt theInstr )
IRTemp vC_andF = newTemp(Ity_V128);
DIP("vperm v%d,v%d,v%d,v%d\n",
vD_addr, vA_addr, vB_addr, vC_addr);
- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
+ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
IR specifies, and also to hide irrelevant bits from
memcheck */
assign( vC_andF,
binop(Iop_AndV128, mkexpr(vC),
- unop(Iop_Dup8x16, mkU8(0x1F))) );
+ unop(Iop_Dup8x16, mkU8(0xF))) );
assign( a_perm,
binop(Iop_Perm8x16, mkexpr(vA), mkexpr(vC_andF)) );
assign( b_perm,
commit 856d45eb7e3661a61ace32be2cfa10bf198620c8
Author: Carl Love <carll@us.ibm.com>
Date: Thu Oct 5 12:19:59 2017 -0500
PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field
The implementation of the vpermr, xxperm, xxpermr violate this by
using a mask of 0x1F. Fix the code and the corresponding comments
to met the definition for Iop_Perm8x16. Use Iop_Dup8x16 to generate
vector value for subtraction.
Bugzilla 385334.
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index b5b0d03..f63146e 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -22579,6 +22579,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
IRTemp b_perm = newTemp(Ity_V128);
IRTemp mask = newTemp(Ity_V128);
IRTemp perm_val = newTemp(Ity_V128);
+ IRTemp vB_adj = newTemp( Ity_V128 );
if ( opc2 == 0x68 ) {
DIP("xxperm v%d,v%d,v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
@@ -22591,29 +22592,27 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
assign( vT, getVSReg( XT ) );
if ( opc2 == 0x68 ) // xxperm
- assign( perm_val,
- binop( Iop_AndV128, mkexpr( vB ),
- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) );
+ assign( vB_adj, mkexpr( vB ) );
else // xxpermr
- assign( perm_val,
+ assign( vB_adj,
binop( Iop_Sub16x8,
- binop( Iop_64HLtoV128,
- mkU64( 0x1F1F1F1F1F1F1F1F ),
- mkU64( 0x1F1F1F1F1F1F1F1F ) ),
- binop( Iop_AndV128, mkexpr( vB ),
- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
+ unop( Iop_Dup8x16, mkU8( 0x1F ) ),
+ mkexpr( vB ) ) );
- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
+ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
IR specifies, and also to hide irrelevant bits from
memcheck.
*/
+ assign( perm_val,
+ binop( Iop_AndV128, mkexpr( vB_adj ),
+ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) );
assign( a_perm,
binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( perm_val ) ) );
assign( b_perm,
binop( Iop_Perm8x16, mkexpr( vT ), mkexpr( perm_val ) ) );
assign( mask, binop( Iop_SarN8x16,
- binop( Iop_ShlN8x16, mkexpr( perm_val ),
+ binop( Iop_ShlN8x16, mkexpr( vB_adj ),
mkU8( 3 ) ),
mkU8( 7 ) ) );
// dst = (a & ~mask) | (b & mask)
@@ -24361,28 +24360,29 @@ static Bool dis_av_permute ( UInt theInstr )
IRTemp b_perm = newTemp( Ity_V128 );
IRTemp mask = newTemp( Ity_V128 );
IRTemp vC_andF = newTemp( Ity_V128 );
+ IRTemp vC_adj = newTemp( Ity_V128 );
DIP( "vpermr v%d,v%d,v%d,v%d\n",
vD_addr, vA_addr, vB_addr, vC_addr);
- /* Limit the Perm8x16 steering values to 0 .. 31 as that is what
+ /* Limit the Perm8x16 steering values to 0 .. 15 as that is what
IR specifies, and also to hide irrelevant bits from
memcheck.
*/
+ assign( vC_adj,
+ binop( Iop_Sub16x8,
+ unop( Iop_Dup8x16, mkU8( 0x1F ) ),
+ mkexpr( vC ) ) );
assign( vC_andF,
- binop( Iop_Sub16x8,
- binop( Iop_64HLtoV128,
- mkU64( 0x1F1F1F1F1F1F1F1F ),
- mkU64( 0x1F1F1F1F1F1F1F1F ) ),
- binop( Iop_AndV128, mkexpr( vC ),
- unop( Iop_Dup8x16, mkU8( 0x1F ) ) ) ) );
+ binop( Iop_AndV128, mkexpr( vC_adj),
+ unop( Iop_Dup8x16, mkU8( 0xF ) ) ) );
assign( a_perm,
binop( Iop_Perm8x16, mkexpr( vA ), mkexpr( vC_andF ) ) );
assign( b_perm,
binop( Iop_Perm8x16, mkexpr( vB ), mkexpr( vC_andF ) ) );
// mask[i8] = (vC[i8]_4 == 1) ? 0xFF : 0x0
assign( mask, binop(Iop_SarN8x16,
- binop( Iop_ShlN8x16, mkexpr( vC_andF ),
+ binop( Iop_ShlN8x16, mkexpr( vC_adj ),
mkU8( 3 ) ), mkU8( 7 ) ) );
// dst = (a & ~mask) | (b & mask)
putVReg( vD_addr, binop( Iop_OrV128,
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