3.9.0-12.svn20140319r13879 - Add valgrind-3.9.0-mpx.patch (#1087933)
This commit is contained in:
Mark Wielaard
parent
d74c103f67
commit
7ca9bdde11
211
valgrind-3.9.0-mpx.patch
Normal file
211
valgrind-3.9.0-mpx.patch
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@ -0,0 +1,211 @@
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diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
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index 40da6bf..fba7084 100644
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--- a/VEX/priv/guest_amd64_toIR.c
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+++ b/VEX/priv/guest_amd64_toIR.c
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@@ -767,10 +767,10 @@ static Bool have66orF2orF3 ( Prefix pfx )
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return toBool( ! haveNo66noF2noF3(pfx) );
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}
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-/* Return True iff pfx has 66 or F2 set */
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-static Bool have66orF2 ( Prefix pfx )
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+/* Return True iff pfx has 66 or F3 set */
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+static Bool have66orF3 ( Prefix pfx )
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{
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- return toBool((pfx & (PFX_66|PFX_F2)) > 0);
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+ return toBool((pfx & (PFX_66|PFX_F3)) > 0);
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}
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/* Clear all the segment-override bits in a prefix. */
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@@ -4266,8 +4266,12 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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modrm = getUChar(delta);
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if (epartIsReg(modrm)) {
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- /* F2/XACQ and F3/XREL are always invalid in the non-mem case. */
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- if (haveF2orF3(pfx)) goto unhandledR;
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+ /* F2/XACQ and F3/XREL are always invalid in the non-mem case.
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+ F2/CALL and F2/JMP may have bnd prefix. */
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+ if (haveF2orF3(pfx)
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+ && ! (haveF2(pfx)
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+ && (gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4)))
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+ goto unhandledR;
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assign(t1, getIRegE(sz,pfx,modrm));
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switch (gregLO3ofRM(modrm)) {
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case 0: /* INC */
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@@ -4287,6 +4291,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 2: /* call Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledR;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, getIRegE(sz,pfx,modrm));
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@@ -4302,6 +4307,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 4: /* jmp Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledR;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, getIRegE(sz,pfx,modrm));
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@@ -4334,11 +4340,14 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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showSz ? nameISize(sz) : ' ',
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nameIRegE(sz, pfx, modrm));
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} else {
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- /* Decide if F2/XACQ or F3/XREL might be valid. */
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+ /* Decide if F2/XACQ, F3/XREL, F2/CALL or F2/JMP might be valid. */
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Bool validF2orF3 = haveF2orF3(pfx) ? False : True;
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if ((gregLO3ofRM(modrm) == 0/*INC*/ || gregLO3ofRM(modrm) == 1/*DEC*/)
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&& haveF2orF3(pfx) && !haveF2andF3(pfx) && haveLOCK(pfx)) {
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validF2orF3 = True;
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+ } else if ((gregLO3ofRM(modrm) == 2 || gregLO3ofRM(modrm) == 4)
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+ && (haveF2(pfx) && !haveF3(pfx))) {
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+ validF2orF3 = True;
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}
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if (!validF2orF3) goto unhandledM;
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/* */
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@@ -4375,6 +4384,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 2: /* call Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledM;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, loadLE(Ity_I64,mkexpr(addr)));
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@@ -4390,6 +4400,7 @@ ULong dis_Grp5 ( VexAbiInfo* vbi,
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case 4: /* JMP Ev */
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/* Ignore any sz value and operate as if sz==8. */
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if (!(sz == 4 || sz == 8)) goto unhandledM;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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sz = 8;
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t3 = newTemp(Ity_I64);
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assign(t3, loadLE(Ity_I64,mkexpr(addr)));
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@@ -19716,7 +19727,8 @@ Long dis_ESC_NONE (
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case 0x7F: { /* JGb/JNLEb (jump greater) */
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Long jmpDelta;
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const HChar* comment = "";
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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jmpDelta = getSDisp8(delta);
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vassert(-128 <= jmpDelta && jmpDelta < 128);
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d64 = (guest_RIP_bbstart+delta+1) + jmpDelta;
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@@ -20369,7 +20381,8 @@ Long dis_ESC_NONE (
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}
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case 0xC2: /* RET imm16 */
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- if (have66orF2orF3(pfx)) goto decode_failure;
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+ if (have66orF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = getUDisp16(delta);
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delta += 2;
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dis_ret(dres, vbi, d64);
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@@ -20377,8 +20390,9 @@ Long dis_ESC_NONE (
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return delta;
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case 0xC3: /* RET */
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- if (have66orF2(pfx)) goto decode_failure;
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+ if (have66(pfx)) goto decode_failure;
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/* F3 is acceptable on AMD. */
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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dis_ret(dres, vbi, 0);
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DIP(haveF3(pfx) ? "rep ; ret\n" : "ret\n");
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return delta;
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@@ -20782,7 +20796,8 @@ Long dis_ESC_NONE (
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}
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case 0xE8: /* CALL J4 */
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = getSDisp32(delta); delta += 4;
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d64 += (guest_RIP_bbstart+delta);
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/* (guest_RIP_bbstart+delta) == return-to addr, d64 == call-to addr */
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@@ -20805,9 +20820,10 @@ Long dis_ESC_NONE (
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return delta;
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case 0xE9: /* Jv (jump, 16/32 offset) */
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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if (sz != 4)
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goto decode_failure; /* JRS added 2004 July 11 */
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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d64 = (guest_RIP_bbstart+delta+sz) + getSDisp(sz,delta);
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delta += sz;
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if (resteerOkFn(callback_opaque,d64)) {
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@@ -21241,7 +21257,8 @@ Long dis_ESC_0F (
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case 0x8F: { /* JGb/JNLEb (jump greater) */
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Long jmpDelta;
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const HChar* comment = "";
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- if (haveF2orF3(pfx)) goto decode_failure;
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+ if (haveF3(pfx)) goto decode_failure;
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+ if (haveF2(pfx)) DIP("bnd ; "); /* MPX bnd prefix. */
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jmpDelta = getSDisp32(delta);
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d64 = (guest_RIP_bbstart+delta+4) + jmpDelta;
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delta += 4;
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@@ -21332,6 +21349,66 @@ Long dis_ESC_0F (
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}
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return delta;
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+ case 0x1A:
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+ case 0x1B: { /* Future MPX instructions, currently NOPs.
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+ BNDMK b, m F3 0F 1B
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+ BNDCL b, r/m F3 0F 1A
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+ BNDCU b, r/m F2 0F 1A
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+ BNDCN b, r/m F2 0F 1B
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+ BNDMOV b, b/m 66 0F 1A
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+ BNDMOV b/m, b 66 0F 1B
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+ BNDLDX b, mib 0F 1A
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+ BNDSTX mib, b 0F 1B */
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+
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+ /* All instructions have two operands. One operand is always the
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+ bnd register number (bnd0-bnd3, other register numbers are
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+ ignored when MPX isn't enabled, but should generate an
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+ exeception if MPX is enabled) given by gregOfRexRM. The other
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+ operand is either a ModRM:reg, ModRM:r/m or a SIB encoded
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+ address, all of which can be decoded by using either
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+ eregOfRexRM or disAMode. */
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+
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+ modrm = getUChar(delta);
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+ int bnd = gregOfRexRM(pfx,modrm);
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+ const HChar *oper;
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+ if (epartIsReg(modrm)) {
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+ oper = nameIReg64 (eregOfRexRM(pfx,modrm));
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+ delta += 1;
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+ } else {
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+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
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+ delta += alen;
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+ oper = dis_buf;
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+ }
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+
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+ if (haveF3no66noF2 (pfx)) {
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+ if (opc == 0x1B) {
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+ DIP ("bndmk %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1A */ {
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+ DIP ("bndcl %s, %%bnd%d\n", oper, bnd);
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+ }
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+ } else if (haveF2no66noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndcu %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndcn %s, %%bnd%d\n", oper, bnd);
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+ }
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+ } else if (have66noF2noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndmov %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndmov %%bnd%d, %s\n", bnd, oper);
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+ }
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+ } else if (haveNo66noF2noF3 (pfx)) {
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+ if (opc == 0x1A) {
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+ DIP ("bndldx %s, %%bnd%d\n", oper, bnd);
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+ } else /* opc == 0x1B */ {
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+ DIP ("bndstx %%bnd%d, %s\n", bnd, oper);
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+ }
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+ } else goto decode_failure;
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+
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+ return delta;
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+ }
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+
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case 0xA2: { /* CPUID */
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/* Uses dirty helper:
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void amd64g_dirtyhelper_CPUID ( VexGuestAMD64State* )
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@ -6,7 +6,7 @@
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Summary: Tool for finding memory management bugs in programs
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Summary: Tool for finding memory management bugs in programs
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Name: %{?scl_prefix}valgrind
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Name: %{?scl_prefix}valgrind
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Version: 3.9.0
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Version: 3.9.0
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Release: 11.svn%{?svn_date}r%{?svn_rev}%{?dist}
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Release: 12.svn%{?svn_date}r%{?svn_rev}%{?dist}
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Epoch: 1
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Epoch: 1
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License: GPLv2+
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License: GPLv2+
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URL: http://www.valgrind.org/
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URL: http://www.valgrind.org/
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@ -57,6 +57,9 @@ Patch4: valgrind-3.9.0-ldso-supp.patch
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# KDE#327943 - s390x missing index/strchr suppression for ld.so bad backtrace?
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# KDE#327943 - s390x missing index/strchr suppression for ld.so bad backtrace?
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Patch5: valgrind-3.9.0-s390x-ld-supp.patch
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Patch5: valgrind-3.9.0-s390x-ld-supp.patch
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# KDE#333666 - No MPX (bndmov) instruction support in VEX
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Patch6: valgrind-3.9.0-mpx.patch
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%if %{build_multilib}
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%if %{build_multilib}
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# Ensure glibc{,-devel} is installed for both multilib arches
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# Ensure glibc{,-devel} is installed for both multilib arches
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BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so
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BuildRequires: /lib/libc.so.6 /usr/lib/libc.so /lib64/libc.so.6 /usr/lib64/libc.so
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@ -161,6 +164,8 @@ Valgrind User Manual for details.
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%patch5 -p1
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%patch5 -p1
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%endif
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%endif
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%patch6 -p1
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%build
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%build
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# We need to use the software collection compiler and binutils if available.
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# We need to use the software collection compiler and binutils if available.
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# The configure checks might otherwise miss support for various newer
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# The configure checks might otherwise miss support for various newer
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@ -319,6 +324,9 @@ echo ===============END TESTING===============
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%endif
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%endif
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%changelog
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%changelog
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* Thu May 8 2014 Mark Wielaard <mjw@redhat.com> 3.9.0-12.svn20140319r13879
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- Add valgrind-3.9.0-mpx.patch (#1087933)
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* Wed Mar 19 2014 Mark Wielaard <mjw@redhat.com> - 3.9.0-11.svn20140319r13879
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* Wed Mar 19 2014 Mark Wielaard <mjw@redhat.com> - 3.9.0-11.svn20140319r13879
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- Update to upstream svn r13879. arm64 make check now builds.
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- Update to upstream svn r13879. arm64 make check now builds.
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