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3.11.0-1 - Upgrade to valgrind 3.11.0 final

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- Drop patches included upstream
  - valgrind-3.11.0-ppc-dfp-guard.patch
  - valgrind-3.11.0-ppc-ppr.patch
  - valgrind-3.11.0-ppc-mbar.patch
  - valgrind-3.11.0-glibc-futex-message.patch
  - valgrind-3.11.0-arm64-libvex_test.patch
  - valgrind-3.11.0-arm-warnings.patch
  - valgrind-3.11.0-arm-no-cast-align.patch
  - valgrind-3.11.0-ppc-vbit-test.patch
- Add arm64 syscall patches
  - valgrind-3.11.0-arm64-xattr.patch
  - valgrind-3.11.0-arm64-sigpending.patch
This commit is contained in:
Mark Wielaard 2015-09-23 14:48:38 +02:00
parent 5f750d2c3b
commit 115cfda8ea
13 changed files with 106 additions and 3347 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
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@ -22,3 +22,4 @@
/valgrind-3.10.1-svn20150817r15561.tar.bz2 /valgrind-3.10.1-svn20150817r15561.tar.bz2
/valgrind-3.10.1-svn20150825r15589.tar.bz2 /valgrind-3.10.1-svn20150825r15589.tar.bz2
/valgrind-3.11.0.TEST1.tar.bz2 /valgrind-3.11.0.TEST1.tar.bz2
/valgrind-3.11.0.tar.bz2

2
sources
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@ -1 +1 @@
6a858b4a1e98db8c82bc6bc9c760873b valgrind-3.11.0.TEST1.tar.bz2 4ea62074da73ae82e0162d6550d3f129 valgrind-3.11.0.tar.bz2

2558
valgrind-3.11.0-arm-no-cast-align.patch
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File diff suppressed because it is too large Load Diff

97
valgrind-3.11.0-arm-warnings.patch
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@ -1,97 +0,0 @@
commit e697c535392ce5b9644f4b5039420a333da1fe3f
Author: florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date: Sun Sep 13 20:27:17 2015 +0000
Fix various compiler warnings for the arm architecture.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15650 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/coregrind/m_debuginfo/readexidx.c b/coregrind/m_debuginfo/readexidx.c
index 2dd89cf..06a9a5f 100644
--- a/coregrind/m_debuginfo/readexidx.c
+++ b/coregrind/m_debuginfo/readexidx.c
@@ -205,7 +205,7 @@ typedef
/* Helper function for fishing bits out of the EXIDX representation. */
-static void* Prel31ToAddr(const void* addr)
+static const void* Prel31ToAddr(const void* addr)
{
UInt offset32 = *(const UInt*)addr;
// sign extend offset32[30:0] to 64 bits -- copy bit 30 to positions
@@ -215,7 +215,7 @@ static void* Prel31ToAddr(const void* addr)
offset64 |= 0xFFFFFFFF80000000ULL;
else
offset64 &= 0x000000007FFFFFFFULL;
- return ((UChar*)addr) + (UWord)offset64;
+ return ((const UChar*)addr) + (UWord)offset64;
}
@@ -242,9 +242,9 @@ ExExtractResult ExtabEntryExtract ( MemoryRange* mr_exidx,
buf[(*buf_used)++] = (_byte); } while (0)
# define GET_EX_U32(_lval, _addr, _mr) \
- do { if (!MemoryRange__covers((_mr), (void*)(_addr), 4)) \
+ do { if (!MemoryRange__covers((_mr), (const void*)(_addr), 4)) \
return ExInBufOverflow; \
- (_lval) = *(UInt*)(_addr); } while (0)
+ (_lval) = *(const UInt*)(_addr); } while (0)
# define GET_EXIDX_U32(_lval, _addr) \
GET_EX_U32(_lval, _addr, mr_exidx)
@@ -263,7 +263,7 @@ ExExtractResult ExtabEntryExtract ( MemoryRange* mr_exidx,
UInt pers; // personality number
UInt extra; // number of extra data words required
UInt extra_allowed; // number of extra data words allowed
- UInt* extbl_data; // the handler entry, if not inlined
+ const UInt* extbl_data; // the handler entry, if not inlined
if (data & ARM_EXIDX_COMPACT) {
// The handler table entry has been inlined into the index table entry.
@@ -283,7 +283,7 @@ ExExtractResult ExtabEntryExtract ( MemoryRange* mr_exidx,
// The index table entry is a pointer to the handler entry. Note
// that Prel31ToAddr will read the given address, but we already
// range-checked above.
- extbl_data = (UInt*)(Prel31ToAddr(&entry->data));
+ extbl_data = Prel31ToAddr(&entry->data);
GET_EXTAB_U32(data, extbl_data);
if (!(data & ARM_EXIDX_COMPACT)) {
// This denotes a "generic model" handler. That will involve
@@ -941,7 +941,7 @@ void ML_(read_exidx) ( /*MOD*/DebugInfo* di,
VG_(printf)("BEGIN ML_(read_exidx) exidx_img=[%p, +%lu) "
"extab_img=[%p, +%lu) text_last_svma=%lx text_bias=%lx\n",
exidx_img, exidx_size, extab_img, extab_size,
- text_last_svma, text_bias);
+ text_last_svma, (UWord)text_bias);
Bool ok;
MemoryRange mr_exidx, mr_extab;
ok = MemoryRange__init(&mr_exidx, exidx_img, exidx_size);
diff --git a/coregrind/m_sigframe/sigframe-arm-linux.c b/coregrind/m_sigframe/sigframe-arm-linux.c
index 2f7781a..185367c 100644
--- a/coregrind/m_sigframe/sigframe-arm-linux.c
+++ b/coregrind/m_sigframe/sigframe-arm-linux.c
@@ -248,7 +248,6 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
struct vg_sig_private *priv;
Addr sp;
UInt frame_size;
- struct vki_sigcontext *mc;
Int sigNo;
Bool has_siginfo = isRT;
@@ -259,14 +258,12 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
if (has_siginfo) {
struct rt_sigframe *frame = (struct rt_sigframe *)sp;
frame_size = sizeof(*frame);
- mc = &frame->sig.uc.uc_mcontext;
priv = &frame->sig.vp;
vg_assert(priv->magicPI == 0x31415927);
tst->sig_mask = frame->sig.uc.uc_sigmask;
} else {
struct sigframe *frame = (struct sigframe *)sp;
frame_size = sizeof(*frame);
- mc = &frame->uc.uc_mcontext;
priv = &frame->vp;
vg_assert(priv->magicPI == 0x31415927);
tst->sig_mask = frame->uc.uc_sigmask;

23
valgrind-3.11.0-arm64-libvex_test.patch
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@ -1,23 +0,0 @@
commit b2a2361e9f8b23364819a010f01a51634ab00066
Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date: Wed Sep 9 13:40:23 2015 +0000
libvex_test: Use arm64_[di]MinLine_lg2_szB values that make libvex happy.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15647 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/none/tests/libvex_test.c b/none/tests/libvex_test.c
index 5718e54..57184c0 100644
--- a/none/tests/libvex_test.c
+++ b/none/tests/libvex_test.c
@@ -221,6 +221,10 @@ int main(int argc, char **argv)
// Use some values that makes AMD64 happy.
vta.abiinfo_both.guest_stack_redzone_size = 128;
+ // Use some values that makes ARM64 happy.
+ vta.archinfo_guest.arm64_dMinLine_lg2_szB = 6;
+ vta.archinfo_guest.arm64_iMinLine_lg2_szB = 6;
+
// Prepare first for a translation where guest == host
// We will translate the get_guest_arch function
vta.arch_guest = guest_arch;

28
valgrind-3.11.0-arm64-sigpending.patch Normal file
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@ -0,0 +1,28 @@
commit b78a32e41a8b5918c706b0ac1b8fbe02fcec854b
Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date: Wed Sep 23 12:15:36 2015 +0000
Bug 353084 arm64 doesn't support sigpending system call.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15676 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
index 6cf3ba5..8d3027d 100644
--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
@@ -959,6 +959,7 @@ static SyscallTableEntry syscall_main_table[] = {
LINX_(__NR_rt_sigsuspend, sys_rt_sigsuspend), // 133
LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 134
LINXY(__NR_rt_sigprocmask, sys_rt_sigprocmask), // 135
+ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 136
LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait), // 137
LINXY(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo), // 138
PLAX_(__NR_rt_sigreturn, sys_rt_sigreturn), // 139
@@ -1231,7 +1232,6 @@ static SyscallTableEntry syscall_main_table[] = {
//ZZ LINXY(__NR_prctl, sys_prctl), // 172
//ZZ LINXY(__NR_rt_sigaction, sys_rt_sigaction), // 174
//ZZ
-//ZZ LINXY(__NR_rt_sigpending, sys_rt_sigpending), // 176
//ZZ LINXY(__NR_rt_sigtimedwait, sys_rt_sigtimedwait),// 177
//ZZ
//ZZ LINX_(__NR_chown, sys_chown16), // 182

54
valgrind-3.11.0-arm64-xattr.patch Normal file
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@ -0,0 +1,54 @@
commit 9f20263f224cf85a81b16fe1570439cecf5ef48b
Author: mjw <mjw@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date: Wed Sep 23 11:51:47 2015 +0000
Bug 353083 arm64 doesn't implement various xattr system calls.
This enables setxattr, lsetxattr, fsetxattr, fgetxattr, removexattr,
lremovexattr, fremovexattr, listxattr, llistxattr and flistxattr on
arm64-linux.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15675 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/coregrind/m_syswrap/syswrap-arm64-linux.c b/coregrind/m_syswrap/syswrap-arm64-linux.c
index 6661d1d..6cf3ba5 100644
--- a/coregrind/m_syswrap/syswrap-arm64-linux.c
+++ b/coregrind/m_syswrap/syswrap-arm64-linux.c
@@ -855,8 +855,18 @@ PRE(sys_rt_sigreturn)
// (unknown).
static SyscallTableEntry syscall_main_table[] = {
+ LINX_(__NR_setxattr, sys_setxattr), // 5
+ LINX_(__NR_lsetxattr, sys_lsetxattr), // 6
+ LINX_(__NR_fsetxattr, sys_fsetxattr), // 7
LINXY(__NR_getxattr, sys_getxattr), // 8
LINXY(__NR_lgetxattr, sys_lgetxattr), // 9
+ LINXY(__NR_fgetxattr, sys_fgetxattr), // 10
+ LINXY(__NR_listxattr, sys_listxattr), // 11
+ LINXY(__NR_llistxattr, sys_llistxattr), // 12
+ LINXY(__NR_flistxattr, sys_flistxattr), // 13
+ LINX_(__NR_removexattr, sys_removexattr), // 14
+ LINX_(__NR_lremovexattr, sys_lremovexattr), // 15
+ LINX_(__NR_fremovexattr, sys_fremovexattr), // 16
GENXY(__NR_getcwd, sys_getcwd), // 17
LINXY(__NR_eventfd2, sys_eventfd2), // 19
LINXY(__NR_epoll_create1, sys_epoll_create1), // 20
@@ -1267,18 +1277,6 @@ static SyscallTableEntry syscall_main_table[] = {
//ZZ // GENX_(222, sys_ni_syscall), // 222
//ZZ // PLAXY(223, sys_syscall223), // 223 // sys_bproc?
//ZZ
-//ZZ LINX_(__NR_setxattr, sys_setxattr), // 226
-//ZZ LINX_(__NR_lsetxattr, sys_lsetxattr), // 227
-//ZZ LINX_(__NR_fsetxattr, sys_fsetxattr), // 228
-//ZZ
-//ZZ LINXY(__NR_fgetxattr, sys_fgetxattr), // 231
-//ZZ LINXY(__NR_listxattr, sys_listxattr), // 232
-//ZZ LINXY(__NR_llistxattr, sys_llistxattr), // 233
-//ZZ LINXY(__NR_flistxattr, sys_flistxattr), // 234
-//ZZ
-//ZZ LINX_(__NR_removexattr, sys_removexattr), // 235
-//ZZ LINX_(__NR_lremovexattr, sys_lremovexattr), // 236
-//ZZ LINX_(__NR_fremovexattr, sys_fremovexattr), // 237
//ZZ LINXY(__NR_tkill, sys_tkill), // 238 */Linux
//ZZ LINXY(__NR_sendfile64, sys_sendfile64), // 239
//ZZ

14
valgrind-3.11.0-glibc-futex-message.patch
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@ -1,14 +0,0 @@
diff --git a/tests/filter_libc b/tests/filter_libc
index 5d8e0ac..9a508b0 100755
--- a/tests/filter_libc
+++ b/tests/filter_libc
@@ -36,6 +36,9 @@ while (<>)
s/(at.*)__builtin_vec_delete/$1...operator delete[].../;
s/(at.*)operator delete\[\]\(void\*\)/$1...operator delete[].../;
+ # Some glibc versions complain about unexpected futex syscall errors.
+ s/The futex facility returned an unexpected error code.//;
+
print;
}

31
valgrind-3.11.0-ppc-dfp-guard.patch
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@ -1,31 +0,0 @@
commit e90d8b4d1ebeccc098a701962111dcdc4d68b1ff
Author: florian <florian@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
Date: Mon Sep 14 19:36:29 2015 +0000
ppc: The functions dis_dfp_fmt_conv and dis_dfp_exponent_test
should only be executed in case DFP is supported. Add missing
guards.
git-svn-id: svn://svn.valgrind.org/vex/trunk@3188 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 1f28da6..bc0bdcb 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -19172,6 +19172,7 @@ DisResult disInstr_PPC_WRK (
case 0x322: // POWER 7 inst, dcffix - DFP convert from fixed
if (!allow_VX)
goto decode_failure;
+ if (!allow_DFP) goto decode_noDFP;
if (dis_dfp_fmt_conv( theInstr ))
goto decode_success;
goto decode_failure;
@@ -19598,6 +19599,7 @@ DisResult disInstr_PPC_WRK (
goto decode_success;
goto decode_failure;
case 0xA2: // dtstexq - DFP Test exponent Quad
+ if (!allow_DFP) goto decode_noDFP;
if (dis_dfp_exponent_test( theInstr ) )
goto decode_success;
goto decode_failure;

49
valgrind-3.11.0-ppc-mbar.patch
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@ -1,49 +0,0 @@
commit cbc52cfe6658f89f6857febf2b1e5c9edab7f397
Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
Date: Wed Sep 16 23:01:04 2015 +0000
Add support for the Power PC mbar instruction.
This patch fixes bugzilla 352768.
git-svn-id: svn://svn.valgrind.org/vex/trunk@3190 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index a0ee34a..6a0b6d8 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -6369,6 +6369,7 @@ static Bool dis_memsync ( UInt theInstr )
UInt b11to25 = IFIELD(theInstr, 11, 15);
UChar flag_L = ifieldRegDS(theInstr);
UInt b11to20 = IFIELD(theInstr, 11, 10);
+ UInt M0 = IFIELD(theInstr, 11, 5);
UChar rD_addr = ifieldRegDS(theInstr);
UChar rS_addr = rD_addr;
UChar rA_addr = ifieldRegA(theInstr);
@@ -6399,12 +6400,20 @@ static Bool dis_memsync ( UInt theInstr )
/* X-Form */
case 0x1F:
switch (opc2) {
- case 0x356: // eieio (Enforce In-Order Exec of I/O, PPC32 p394)
- if (b11to25 != 0 || b0 != 0) {
- vex_printf("dis_memsync(ppc)(eiei0,b11to25|b0)\n");
- return False;
+ case 0x356: // eieio or mbar (Enforce In-Order Exec of I/O, PPC32 p394)
+ if (M0 == 0) {
+ if (b11to20 != 0 || b0 != 0) {
+ vex_printf("dis_memsync(ppc)(eieio,b11to20|b0)\n");
+ return False;
+ }
+ DIP("eieio\n");
+ } else {
+ if (b11to20 != 0 || b0 != 0) {
+ vex_printf("dis_memsync(ppc)(mbar,b11to20|b0)\n");
+ return False;
+ }
+ DIP("mbar %d\n", M0);
}
- DIP("eieio\n");
/* Insert a memory fence, just to be on the safe side. */
stmt( IRStmt_MBE(Imbe_Fence) );
break;

261
valgrind-3.11.0-ppc-ppr.patch
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@ -1,261 +0,0 @@
commit 85d259b468099f38b5241241b92fee07530b53d9
Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
Date: Wed Sep 16 22:26:59 2015 +0000
Add support for the Power PC Program Priority Register
Added the Program Priority Register (PPR), support to read and write it
via the mfspr and mtspr instructions as well as the special OR instruction
No Op instructions. The setting of the PPR is dependent on the value in
the Problem State Priority Boost register. Basic support for this register
was added. Not all of the PSPB register functionality was added.
This patch fixes bugzilla 352769.
git-svn-id: svn://svn.valgrind.org/vex/trunk@3189 8f6e269a-dfd6-0310-a8e1-e2731360e62c
diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
index 00137e4..08a0753 100644
--- a/VEX/priv/guest_ppc_helpers.c
+++ b/VEX/priv/guest_ppc_helpers.c
@@ -521,6 +521,8 @@ void LibVEX_GuestPPC32_initialise ( /*OUT*/VexGuestPPC32State* vex_state )
vex_state->guest_IP_AT_SYSCALL = 0;
vex_state->guest_SPRG3_RO = 0;
+ vex_state->guest_PPR = 0x4ULL << 50; // medium priority
+ vex_state->guest_PSPB = 0x100; // an arbitrary non-zero value to start with
vex_state->padding1 = 0;
vex_state->padding2 = 0;
@@ -691,6 +693,8 @@ void LibVEX_GuestPPC64_initialise ( /*OUT*/VexGuestPPC64State* vex_state )
vex_state->guest_TFHAR = 0;
vex_state->guest_TFIAR = 0;
vex_state->guest_TEXASR = 0;
+ vex_state->guest_PPR = 0x4ULL << 50; // medium priority
+ vex_state->guest_PSPB = 0x00; // an arbitrary non-zero value to start with
}
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index bc0bdcb..a0ee34a 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -288,6 +288,8 @@ static void* fnptr_to_fnentry( const VexAbiInfo* vbi, void* f )
#define OFFB_TEXASR offsetofPPCGuestState(guest_TEXASR)
#define OFFB_TEXASRU offsetofPPCGuestState(guest_TEXASRU)
#define OFFB_TFIAR offsetofPPCGuestState(guest_TFIAR)
+#define OFFB_PPR offsetofPPCGuestState(guest_PPR)
+#define OFFB_PSPB offsetofPPCGuestState(guest_PSPB)
/*------------------------------------------------------------*/
@@ -438,6 +440,14 @@ typedef enum {
PPC_GST_TFIAR, // Transactional Failure Instruction Address Register
PPC_GST_TEXASR, // Transactional EXception And Summary Register
PPC_GST_TEXASRU, // Transactional EXception And Summary Register Upper
+ PPC_GST_PPR, // Program Priority register
+ PPC_GST_PPR32, // Upper 32-bits of Program Priority register
+ PPC_GST_PSPB, /* Problem State Priority Boost register, Note, the
+ * register is initialized to a non-zero value. Currently
+ * Valgrind is not supporting the register value to
+ * automatically decrement. Could be added later if
+ * needed.
+ */
PPC_GST_MAX
} PPC_GST;
@@ -2747,6 +2757,15 @@ static IRExpr* /* :: Ity_I32/64 */ getGST ( PPC_GST reg )
case PPC_GST_TFIAR:
return IRExpr_Get( OFFB_TFIAR, ty );
+ case PPC_GST_PPR:
+ return IRExpr_Get( OFFB_PPR, ty );
+
+ case PPC_GST_PPR32:
+ return unop( Iop_64HIto32, IRExpr_Get( OFFB_PPR, ty ) );
+
+ case PPC_GST_PSPB:
+ return IRExpr_Get( OFFB_PSPB, ty );
+
default:
vex_printf("getGST(ppc): reg = %u", reg);
vpanic("getGST(ppc)");
@@ -2926,6 +2945,95 @@ static void putGST ( PPC_GST reg, IRExpr* src )
vassert( ty_src == Ity_I64 );
stmt( IRStmt_Put( OFFB_TFHAR, src ) );
break;
+
+ case PPC_GST_PPR32:
+ case PPC_GST_PPR:
+ {
+ /* The Program Priority Register (PPR) stores the priority in
+ * bits [52:50]. The user setable priorities are:
+ *
+ * 001 very low
+ * 010 low
+ * 011 medium low
+ * 100 medium
+ * 101 medium high
+ *
+ * If the argument is not between 0b001 and 0b100 the priority is set
+ * to 0b100. The priority can only be set to 0b101 if the the Problem
+ * State Boost Register is non-zero. The value of the PPR is not
+ * changed if the input is not valid.
+ */
+
+ IRTemp not_valid = newTemp(Ity_I64);
+ IRTemp has_perm = newTemp(Ity_I64);
+ IRTemp new_src = newTemp(Ity_I64);
+ IRTemp PSPB_val = newTemp(Ity_I64);
+ IRTemp value = newTemp(Ity_I64);
+
+ vassert(( ty_src == Ity_I64 ) || ( ty_src == Ity_I32 ));
+ assign( PSPB_val, binop( Iop_32HLto64,
+ mkU32( 0 ),
+ IRExpr_Get( OFFB_PSPB, Ity_I32 ) ) );
+ if( reg == PPC_GST_PPR32 ) {
+ vassert( ty_src == Ity_I32 );
+ assign( value, binop( Iop_32HLto64,
+ mkU32(0),
+ binop( Iop_And32,
+ binop( Iop_Shr32, src, mkU8( 18 ) ),
+ mkU32( 0x7 ) ) ) );
+ } else {
+ vassert( ty_src == Ity_I64 );
+ assign( value, binop( Iop_And64,
+ binop( Iop_Shr64, src, mkU8( 50 ) ),
+ mkU64( 0x7 ) ) );
+ }
+ assign( has_perm,
+ binop( Iop_And64,
+ unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64,
+ mkexpr( PSPB_val ),
+ mkU64( 0 ) ) ),
+ unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64,
+ mkU64( 0x5 ),
+ mkexpr( value ) ) ) ) );
+ assign( not_valid,
+ binop( Iop_Or64,
+ unop( Iop_1Sto64,
+ binop( Iop_CmpEQ64,
+ mkexpr( value ),
+ mkU64( 0 ) ) ),
+ unop( Iop_1Sto64,
+ binop( Iop_CmpLT64U,
+ mkU64( 0x5 ),
+ mkexpr( value ) ) ) ) );
+ assign( new_src,
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ unop( Iop_Not64,
+ mkexpr( not_valid ) ),
+ src ),
+ binop( Iop_And64,
+ mkexpr( not_valid ),
+ binop( Iop_Or64,
+ binop( Iop_And64,
+ mkexpr( has_perm),
+ binop( Iop_Shl64,
+ mkexpr( value ),
+ mkU8( 50 ) ) ),
+ binop( Iop_And64,
+ IRExpr_Get( OFFB_PPR, ty ),
+ unop( Iop_Not64,
+ mkexpr( has_perm )
+ ) ) ) ) ) );
+
+ /* make sure we only set the valid bit field [52:50] */
+ stmt( IRStmt_Put( OFFB_PPR,
+ binop( Iop_And64,
+ mkexpr( new_src ),
+ mkU64( 0x1C000000000000) ) ) );
+ break;
+ }
default:
vex_printf("putGST(ppc): reg = %u", reg);
vpanic("putGST(ppc)");
@@ -7131,6 +7239,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
DIP("mfspr r%u (TEXASRU)\n", rD_addr);
putIReg( rD_addr, getGST( PPC_GST_TEXASRU) );
break;
+ case 0x9F: // 159
+ DIP("mfspr r%u (PSPB)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_PSPB) );
+ break;
+ case 0x380: // 896
+ DIP("mfspr r%u (PPR)\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_PPR) );
+ break;
+ case 0x382: // 898
+ DIP("mfspr r%u (PPR)32\n", rD_addr);
+ putIReg( rD_addr, getGST( PPC_GST_PPR32) );
+ break;
case 0x100:
DIP("mfvrsave r%u\n", rD_addr);
putIReg( rD_addr, mkWidenFrom32(ty, getGST( PPC_GST_VRSAVE ),
@@ -7287,6 +7407,18 @@ static Bool dis_proc_ctl ( const VexAbiInfo* vbi, UInt theInstr )
DIP("mtspr r%u (TEXASR)\n", rS_addr);
putGST( PPC_GST_TEXASR, mkexpr(rS) );
break;
+ case 0x9F: // 159
+ DIP("mtspr r%u (PSPB)\n", rS_addr);
+ putGST( PPC_GST_PSPB, mkexpr(rS) );
+ break;
+ case 0x380: // 896
+ DIP("mtspr r%u (PPR)\n", rS_addr);
+ putGST( PPC_GST_PPR, mkexpr(rS) );
+ break;
+ case 0x382: // 898
+ DIP("mtspr r%u (PPR32)\n", rS_addr);
+ putGST( PPC_GST_PPR32, mkexpr(rS) );
+ break;
default:
vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR);
return False;
diff --git a/pub/libvex_guest_ppc32.h b/pub/libvex_guest_ppc32.h
index 2489d55..5bebef8 100644
--- a/VEX/pub/libvex_guest_ppc32.h
+++ b/VEX/pub/libvex_guest_ppc32.h
@@ -241,11 +241,12 @@ typedef
/* 1360 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
/* 1368 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
/* 1376 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
- /* 1384 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
-
+ /* 1384 */ ULong guest_PPR; // Program Priority register
+ /* 1392 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1396 */ UInt guest_PSPB; // Problem State Priority Boost register
/* Padding to make it have an 16-aligned size */
- /* 1388 */ UInt padding2;
-
+ /* 1400 */ UInt padding2;
+ /* 1404 */ UInt padding3;
}
VexGuestPPC32State;
diff --git a/VEX/pub/libvex_guest_ppc64.h b/VEX/pub/libvex_guest_ppc64.h
index dea2bba..f3310cb 100644
--- a/VEX/pub/libvex_guest_ppc64.h
+++ b/VEX/pub/libvex_guest_ppc64.h
@@ -282,12 +282,14 @@ typedef
/* 1656 */ ULong guest_TFHAR; // Transaction Failure Handler Address Register
/* 1664 */ ULong guest_TEXASR; // Transaction EXception And Summary Register
/* 1672 */ ULong guest_TFIAR; // Transaction Failure Instruction Address Register
- /* 1680 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1680 */ ULong guest_PPR; // Program Priority register
+ /* 1688 */ UInt guest_TEXASRU; // Transaction EXception And Summary Register Upper
+ /* 1692 */ UInt guest_PSPB; // Problem State Priority Boost register
/* Padding to make it have an 16-aligned size */
- /* 1684 */ UInt padding1;
- /* 1688 */ UInt padding2;
- /* 1692 */ UInt padding3;
+ /* 1696 UInt padding1; currently not needed */
+ /* 1700 UInt padding2; currently not needed */
+ /* 1708 UInt padding3; currently not needed */
}
VexGuestPPC64State;

282
valgrind-3.11.0-ppc-vbit-test.patch
View File

@ -1,282 +0,0 @@
commit f559672f0691e8a9913ef573f5ab507401646159
Author: carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date: Wed Sep 16 23:33:40 2015 +0000
Add Power PC ISA check to the vbit-test
The support for the Valgrind Iops is dependent on the Power processor
support for various instructions. The instructions supported by a
given Power processor is based on the version of the ISA. The patch
add a check to the vbit-test to ensure it does not try to test an Iop
that generates an instruction on the host that is not supported.
This patch fixes bugzilla 352765.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15653 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index d0e3b58..9e9f017 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -1143,6 +1143,38 @@ get_irop(IROp op)
return p->amd64 ? p : NULL;
#endif
#ifdef __powerpc__
+#define MIN_POWER_ISA "../../../tests/min_power_isa"
+
+ switch (op) {
+ case Iop_DivS64E:
+ case Iop_DivU64E:
+ case Iop_DivU32E:
+ case Iop_DivS32E:
+ case Iop_F64toI64U:
+ case Iop_F64toI32U:
+ case Iop_I64UtoF64:
+ case Iop_I64UtoF32:
+ case Iop_I64StoD64: {
+ int rc;
+ /* IROps require a processor that supports ISA 2.06 or newer */
+ rc = system(MIN_POWER_ISA " 2.06 ");
+ rc /= 256;
+ /* MIN_POWER_ISA returns 0 if underlying HW supports the
+ * specified ISA or newer. Returns 1 if the HW does not support
+ * the specified ISA. Returns 2 on error.
+ */
+ if (rc == 1) return NULL;
+ if (rc > 2) {
+ panic(" ERROR, min_power_isa() return code is invalid.\n");
+ }
+ }
+ break;
+
+ /* Other */
+ default:
+ break;
+ }
+
#ifdef __powerpc64__
return p->ppc64 ? p : NULL;
#else
diff --git a/tests/Makefile.am b/tests/Makefile.am
index 708c28e..9c0cc3a 100644
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
@@ -1,6 +1,26 @@
include $(top_srcdir)/Makefile.tool-tests.am
+if HAS_ISA_2_05
+ISA_2_05_FLAG = -DHAS_ISA_2_05
+else
+ISA_2_05_FLAG =
+endif
+
+if HAS_ISA_2_06
+ISA_2_06_FLAG = -DHAS_ISA_2_06
+else
+ISA_2_06_FLAG =
+endif
+
+if HAS_ISA_2_07
+ISA_2_07_FLAG = -DHAS_ISA_2_07
+else
+ISA_2_07_FLAG =
+endif
+
+min_power_isa_FLAGS = $(ISA_2_05_FLAG) $(ISA_2_06_FLAG) $(ISA_2_07_FLAG)
+
dist_noinst_SCRIPTS = \
check_headers_and_includes \
check_makefile_consistency \
@@ -29,7 +49,8 @@ check_PROGRAMS = \
s390x_features \
mips_features \
power_insn_available \
- is_ppc64_BE
+ is_ppc64_BE \
+ min_power_isa
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
@@ -40,3 +61,4 @@ else
x86_amd64_features_CFLAGS = $(AM_CFLAGS)
endif
+min_power_isa_CFLAGS = $(min_power_isa_FLAGS)
diff --git a/tests/min_power_isa.c b/tests/min_power_isa.c
new file mode 100644
index 0000000..efcf526
--- /dev/null
+++ b/tests/min_power_isa.c
@@ -0,0 +1,65 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* main() */
+int main(int argc, char **argv)
+{
+ /* This program is passed in a minimum ISA that the underlying hardwre
+ * needs to support. If the HW supports this ISA or newer, return 0
+ * for supported. Otherwise, return 1 for not supported. Return 2 for
+ * usage error.
+ *
+ * First argument is required, it must be an ISA version number.
+ * Second argument "-debug" is optional. If passed, then the defined ISA
+ * values are printed.
+ */
+ char *min_isa;
+ int isa_level = 0;
+ int debug = 0;
+
+ /* set the isa_level set by the Make */
+
+ if ((argc == 3) && (strcmp(argv[2], "-debug") == 0)) {
+ debug = 1;
+
+ } else if (argc != 2) {
+ fprintf(stderr, "usage: min_power_ISA <ISA> [-debug]\n" );
+ exit(2);
+ }
+
+ min_isa = argv[1];
+
+#ifdef HAS_ISA_2_05
+ if (debug) printf("HAS_ISA_2_05 is set\n");
+ isa_level = 5;
+#endif
+
+#ifdef HAS_ISA_2_06
+ if (debug) printf("HAS_ISA_2_06 is set\n");
+ isa_level = 6;
+#endif
+
+#ifdef HAS_ISA_2_07
+ if (debug) printf("HAS_ISA_2_07 is set\n");
+ isa_level = 7;
+#endif
+
+ /* return 0 for supported (success), 1 for not supported (failure) */
+ if (strcmp (min_isa, "2.05") == 0) {
+ return !(isa_level >= 5);
+
+ } else if (strcmp (min_isa, "2.06") == 0) {
+ return !(isa_level >= 6);
+
+ } else if (strcmp (min_isa, "2.07") == 0) {
+ return !(isa_level >= 7);
+
+ } else {
+ fprintf(stderr, "ERROR: invalid ISA version. Valid versions numbers are:\n" );
+ fprintf(stderr, " 2.05, 2.06, 2.07\n" );
+ exit(2);
+ }
+
+ return 1;
+}
Only in valgrind-3.11.0.TEST1: autom4te.cache
diff -ur valgrind-3.11.0.TEST1.orig/tests/Makefile.in valgrind-3.11.0.TEST1/tests/Makefile.in
--- valgrind-3.11.0.TEST1.orig/tests/Makefile.in 2015-09-18 22:39:24.604895071 +0200
+++ valgrind-3.11.0.TEST1/tests/Makefile.in 2015-09-18 22:39:41.996861793 +0200
@@ -117,7 +117,7 @@
check_PROGRAMS = arch_test$(EXEEXT) os_test$(EXEEXT) true$(EXEEXT) \
x86_amd64_features$(EXEEXT) s390x_features$(EXEEXT) \
mips_features$(EXEEXT) power_insn_available$(EXEEXT) \
- is_ppc64_BE$(EXEEXT)
+ is_ppc64_BE$(EXEEXT) min_power_isa$(EXEEXT)
subdir = tests
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
@@ -133,6 +133,11 @@
is_ppc64_BE_SOURCES = is_ppc64_BE.c
is_ppc64_BE_OBJECTS = is_ppc64_BE.$(OBJEXT)
is_ppc64_BE_LDADD = $(LDADD)
+min_power_isa_SOURCES = min_power_isa.c
+min_power_isa_OBJECTS = min_power_isa-min_power_isa.$(OBJEXT)
+min_power_isa_LDADD = $(LDADD)
+min_power_isa_LINK = $(CCLD) $(min_power_isa_CFLAGS) $(CFLAGS) \
+ $(AM_LDFLAGS) $(LDFLAGS) -o $@
mips_features_SOURCES = mips_features.c
mips_features_OBJECTS = mips_features.$(OBJEXT)
mips_features_LDADD = $(LDADD)
@@ -187,12 +192,12 @@
am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
-SOURCES = arch_test.c is_ppc64_BE.c mips_features.c os_test.c \
- power_insn_available.c s390x_features.c true.c \
- x86_amd64_features.c
-DIST_SOURCES = arch_test.c is_ppc64_BE.c mips_features.c os_test.c \
- power_insn_available.c s390x_features.c true.c \
+SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c mips_features.c \
+ os_test.c power_insn_available.c s390x_features.c true.c \
x86_amd64_features.c
+DIST_SOURCES = arch_test.c is_ppc64_BE.c min_power_isa.c \
+ mips_features.c os_test.c power_insn_available.c \
+ s390x_features.c true.c x86_amd64_features.c
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
@@ -583,6 +588,13 @@
# automake; see comments in Makefile.all.am for more detail.
AM_CCASFLAGS = $(AM_CPPFLAGS)
@VGCONF_OS_IS_DARWIN_TRUE@noinst_DSYMS = $(check_PROGRAMS)
+@HAS_ISA_2_05_FALSE@ISA_2_05_FLAG =
+@HAS_ISA_2_05_TRUE@ISA_2_05_FLAG = -DHAS_ISA_2_05
+@HAS_ISA_2_06_FALSE@ISA_2_06_FLAG =
+@HAS_ISA_2_06_TRUE@ISA_2_06_FLAG = -DHAS_ISA_2_06
+@HAS_ISA_2_07_FALSE@ISA_2_07_FLAG =
+@HAS_ISA_2_07_TRUE@ISA_2_07_FLAG = -DHAS_ISA_2_07
+min_power_isa_FLAGS = $(ISA_2_05_FLAG) $(ISA_2_06_FLAG) $(ISA_2_07_FLAG)
dist_noinst_SCRIPTS = \
check_headers_and_includes \
check_makefile_consistency \
@@ -605,6 +617,7 @@
@VGCONF_OS_IS_DARWIN_FALSE@x86_amd64_features_CFLAGS = $(AM_CFLAGS)
@VGCONF_OS_IS_DARWIN_TRUE@x86_amd64_features_CFLAGS = $(AM_CFLAGS) -mdynamic-no-pic
+min_power_isa_CFLAGS = $(min_power_isa_FLAGS)
all: all-am
.SUFFIXES:
@@ -654,6 +667,10 @@
@rm -f is_ppc64_BE$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(is_ppc64_BE_OBJECTS) $(is_ppc64_BE_LDADD) $(LIBS)
+min_power_isa$(EXEEXT): $(min_power_isa_OBJECTS) $(min_power_isa_DEPENDENCIES) $(EXTRA_min_power_isa_DEPENDENCIES)
+ @rm -f min_power_isa$(EXEEXT)
+ $(AM_V_CCLD)$(min_power_isa_LINK) $(min_power_isa_OBJECTS) $(min_power_isa_LDADD) $(LIBS)
+
mips_features$(EXEEXT): $(mips_features_OBJECTS) $(mips_features_DEPENDENCIES) $(EXTRA_mips_features_DEPENDENCIES)
@rm -f mips_features$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(mips_features_OBJECTS) $(mips_features_LDADD) $(LIBS)
@@ -686,6 +703,7 @@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arch_test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is_ppc64_BE.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/min_power_isa-min_power_isa.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mips_features.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/os_test.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/power_insn_available.Po@am__quote@
@@ -709,6 +727,20 @@
@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'`
+min_power_isa-min_power_isa.o: min_power_isa.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(min_power_isa_CFLAGS) $(CFLAGS) -MT min_power_isa-min_power_isa.o -MD -MP -MF $(DEPDIR)/min_power_isa-min_power_isa.Tpo -c -o min_power_isa-min_power_isa.o `test -f 'min_power_isa.c' || echo '$(srcdir)/'`min_power_isa.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/min_power_isa-min_power_isa.Tpo $(DEPDIR)/min_power_isa-min_power_isa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='min_power_isa.c' object='min_power_isa-min_power_isa.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(min_power_isa_CFLAGS) $(CFLAGS) -c -o min_power_isa-min_power_isa.o `test -f 'min_power_isa.c' || echo '$(srcdir)/'`min_power_isa.c
+
+min_power_isa-min_power_isa.obj: min_power_isa.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(min_power_isa_CFLAGS) $(CFLAGS) -MT min_power_isa-min_power_isa.obj -MD -MP -MF $(DEPDIR)/min_power_isa-min_power_isa.Tpo -c -o min_power_isa-min_power_isa.obj `if test -f 'min_power_isa.c'; then $(CYGPATH_W) 'min_power_isa.c'; else $(CYGPATH_W) '$(srcdir)/min_power_isa.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/min_power_isa-min_power_isa.Tpo $(DEPDIR)/min_power_isa-min_power_isa.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='min_power_isa.c' object='min_power_isa-min_power_isa.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(min_power_isa_CFLAGS) $(CFLAGS) -c -o min_power_isa-min_power_isa.obj `if test -f 'min_power_isa.c'; then $(CYGPATH_W) 'min_power_isa.c'; else $(CYGPATH_W) '$(srcdir)/min_power_isa.c'; fi`
+
x86_amd64_features-x86_amd64_features.o: x86_amd64_features.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(x86_amd64_features_CFLAGS) $(CFLAGS) -MT x86_amd64_features-x86_amd64_features.o -MD -MP -MF $(DEPDIR)/x86_amd64_features-x86_amd64_features.Tpo -c -o x86_amd64_features-x86_amd64_features.o `test -f 'x86_amd64_features.c' || echo '$(srcdir)/'`x86_amd64_features.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/x86_amd64_features-x86_amd64_features.Tpo $(DEPDIR)/x86_amd64_features-x86_amd64_features.Po

53
valgrind.spec
View File

@ -3,7 +3,7 @@
Summary: Tool for finding memory management bugs in programs Summary: Tool for finding memory management bugs in programs
Name: %{?scl_prefix}valgrind Name: %{?scl_prefix}valgrind
Version: 3.11.0 Version: 3.11.0
Release: 0.4.TEST1%{?dist} Release: 1%{?dist}
Epoch: 1 Epoch: 1
License: GPLv2+ License: GPLv2+
URL: http://www.valgrind.org/ URL: http://www.valgrind.org/
@ -44,7 +44,7 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
%define _find_debuginfo_dwz_opts %{nil} %define _find_debuginfo_dwz_opts %{nil}
%undefine _include_minidebuginfo %undefine _include_minidebuginfo
Source0: http://www.valgrind.org/downloads/valgrind-%{version}.TEST1.tar.bz2 Source0: http://www.valgrind.org/downloads/valgrind-%{version}.tar.bz2
# Needs investigation and pushing upstream # Needs investigation and pushing upstream
Patch1: valgrind-3.9.0-cachegrind-improvements.patch Patch1: valgrind-3.9.0-cachegrind-improvements.patch
@ -55,29 +55,11 @@ Patch2: valgrind-3.9.0-helgrind-race-supp.patch
# Make ld.so supressions slightly less specific. # Make ld.so supressions slightly less specific.
Patch3: valgrind-3.9.0-ldso-supp.patch Patch3: valgrind-3.9.0-ldso-supp.patch
# Suppress glibc futex warning messages in testsuite. # KDE#353083 arm64 doesn't implement various xattr system calls.
Patch4: valgrind-3.11.0-glibc-futex-message.patch Patch4: valgrind-3.11.0-arm64-xattr.patch
# Fix libvex_test on arm64 # KDE#353084 arm64 doesn't support sigpending system call.
Patch5: valgrind-3.11.0-arm64-libvex_test.patch Patch5: valgrind-3.11.0-arm64-sigpending.patch
# Fix some compiler warnings on arm
Patch6: valgrind-3.11.0-arm-warnings.patch
# Don't use -Wcast-align on arm
Patch7: valgrind-3.11.0-arm-no-cast-align.patch
# ppc vbit test fix
Patch8: valgrind-3.11.0-ppc-vbit-test.patch
# VEXr3188 guard dis_dfp_fmt_conv and dis_dfp_exponent_test with allow_DFP
Patch9: valgrind-3.11.0-ppc-dfp-guard.patch
# KDE#352769 Power PC program priority register (PPR) is not supported
Patch10: valgrind-3.11.0-ppc-ppr.patch
# KDE#352768 The mbar instruction is missing from the Power PC support
Patch11: valgrind-3.11.0-ppc-mbar.patch
%if %{build_multilib} %if %{build_multilib}
# Ensure glibc{,-devel} is installed for both multilib arches # Ensure glibc{,-devel} is installed for both multilib arches
@ -181,19 +163,13 @@ See the section on Debugging MPI Parallel Programs with Valgrind in the
Valgrind User Manual for details. Valgrind User Manual for details.
%prep %prep
%setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version}.TEST1 %setup -q -n %{?scl:%{pkg_name}}%{!?scl:%{name}}-%{version}
%patch1 -p1 %patch1 -p1
%patch2 -p1 %patch2 -p1
%patch3 -p1 %patch3 -p1
%patch4 -p1 %patch4 -p1
%patch5 -p1 %patch5 -p1
%patch6 -p1
%patch7 -p1
%patch8 -p1
%patch9 -p1
%patch10 -p1
%patch11 -p1
%build %build
# We need to use the software collection compiler and binutils if available. # We need to use the software collection compiler and binutils if available.
@ -369,6 +345,21 @@ echo ===============END TESTING===============
%endif %endif
%changelog %changelog
* Wed Sep 23 2015 Mark Wielaard <mjw@redhat.com> - 3.11.0-1
- Upgrade to valgrind 3.11.0 final
- Drop patches included upstream
- valgrind-3.11.0-ppc-dfp-guard.patch
- valgrind-3.11.0-ppc-ppr.patch
- valgrind-3.11.0-ppc-mbar.patch
- valgrind-3.11.0-glibc-futex-message.patch
- valgrind-3.11.0-arm64-libvex_test.patch
- valgrind-3.11.0-arm-warnings.patch
- valgrind-3.11.0-arm-no-cast-align.patch
- valgrind-3.11.0-ppc-vbit-test.patch
- Add arm64 syscall patches
- valgrind-3.11.0-arm64-xattr.patch
- valgrind-3.11.0-arm64-sigpending.patch
* Sat Sep 19 2015 Mark Wielaard <mjw@redhat.com> - 3.11.0-0.4.TEST1 * Sat Sep 19 2015 Mark Wielaard <mjw@redhat.com> - 3.11.0-0.4.TEST1
- Add valgrind-3.11.0-ppc-dfp-guard.patch - Add valgrind-3.11.0-ppc-dfp-guard.patch
- Add valgrind-3.11.0-ppc-ppr.patch - Add valgrind-3.11.0-ppc-ppr.patch