48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
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commit b7d65cab4f3e9a6f66a496e723e53ed736c4d2e7
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Author: Mark Wielaard <mark@klomp.org>
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Date: Sun Dec 9 00:55:42 2018 +0100
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Implement ppc64 lxvd2x as 128-bit load with double word swap for ppc64le.
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This makes it possible for memcheck to know which part of the 128bit
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vector is defined, even if the load is partly beyond an addressable block.
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Partially resolves bug 386945.
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index a81dace..7af4973 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -20590,16 +20590,22 @@ dis_vx_load ( UInt theInstr )
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}
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case 0x34C: // lxvd2x
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{
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- IROp addOp = ty == Ity_I64 ? Iop_Add64 : Iop_Add32;
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- IRExpr * high, *low;
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- ULong ea_off = 8;
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- IRExpr* high_addr;
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+ IRExpr *t128;
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DIP("lxvd2x %d,r%u,r%u\n", XT, rA_addr, rB_addr);
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- high = load( Ity_I64, mkexpr( EA ) );
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- high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
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- : mkU32( ea_off ) );
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- low = load( Ity_I64, high_addr );
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- putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
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+ t128 = load( Ity_V128, mkexpr( EA ) );
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+
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+ /* The data in the vec register should be in big endian order.
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+ So if we just did a little endian load then swap around the
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+ high and low double words. */
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+ if (host_endness == VexEndnessLE) {
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+ IRTemp high = newTemp(Ity_I64);
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+ IRTemp low = newTemp(Ity_I64);
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+ assign( high, unop(Iop_V128HIto64, t128) );
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+ assign( low, unop(Iop_V128to64, t128) );
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+ t128 = binop( Iop_64HLtoV128, mkexpr (low), mkexpr (high) );
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+ }
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+
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+ putVSReg( XT, t128 );
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break;
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}
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case 0x14C: // lxvdsx
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