valgrind/valgrind-3.8.1-ppc-32-mode-64-bit-instr.patch

commit 12053bd517d2c5ab55de4ffaa4833ef9a865d8d5
Author: carll <carll@8f6e269a-dfd6-0310-a8e1-e2731360e62c>
Date:   Mon Oct 29 20:23:41 2012 +0000

    Valgrind, ppc:  Fix missing checks for 64-bit instructions operating in 32-bit mode, Bugzilla 308573
    
    A number of the POWER instructions are only intended to run on 64-bit
    hardware.  These instructions will give a SIGILL instruction on 32-bit
    hardware.  The check for 32-bit mode on some of these instructions is
    missing.  Although, the 64-bit hardware will execute these instructions
    on 64-bit hardware without generating a SIGILL the use of these
    instructions in 32-bit mode on 64-bit hardware is typically indicative of
    a programming error. There are cases where these instructions are used
    to determine if the code is running on 32-bit hardware or not.  In these
    cases, the instruction needs to generate a SIGILL for the error handler
    to properly determine the hardware is running in 32-bit mode.
    
    This patch adds the 32-bit mode check for those 64-bit instructions that
    do not have the check.  If the check fails, the instruction is flagged
    as an unsupported instruction and a SIGILL message is generated.
    
    This patch fixes the bug reported in:
    Bug 308573 - Internal Valgrind error on 64-bit instruction executed in
    32-bit mode
    
    Note, there is an accompaning fix to memcheck/tests/ppc32/power_ISA2_05.c
    to only execute the 64-bit instruction prtyd test in 64-bit mode.
    
    Carl Love  cel@us.ibm.com
    
    git-svn-id: svn://svn.valgrind.org/vex/trunk@2558 8f6e269a-dfd6-0310-a8e1-e2731360e62c

diff --git a/priv/guest_ppc_toIR.c b/priv/guest_ppc_toIR.c
index 800f8ef..565bfe5 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -16653,6 +16653,7 @@ DisResult disInstr_PPC_WRK (
 
    /* 64bit Integer Rotate Instructions */
    case 0x1E: // rldcl, rldcr, rldic, rldicl, rldicr, rldimi
+      if (!mode64) goto decode_failure;
       if (dis_int_rot( theInstr )) goto decode_success;
       goto decode_failure;
 
@@ -16687,7 +16688,12 @@ DisResult disInstr_PPC_WRK (
       goto decode_failure;
 
    /* Trap Instructions */
-   case 0x02: case 0x03: // tdi, twi
+   case 0x02:    // tdi
+      if (!mode64) goto decode_failure;
+      if (dis_trapi(theInstr, &dres)) goto decode_success;
+      goto decode_failure;
+
+   case 0x03:   // twi
       if (dis_trapi(theInstr, &dres)) goto decode_success;
       goto decode_failure;
 
@@ -17288,7 +17294,12 @@ DisResult disInstr_PPC_WRK (
          goto decode_failure;
 
          /* 64bit Integer Parity Instructions */
-      case 0xba: case 0x9a: // prtyd, prtyw
+      case 0xba: // prtyd
+         if (!mode64) goto decode_failure;
+         if (dis_int_parity( theInstr )) goto decode_success;
+         goto decode_failure;
+
+      case 0x9a: // prtyw
          if (dis_int_parity( theInstr )) goto decode_success;
          goto decode_failure;
 
@@ -17333,9 +17344,13 @@ DisResult disInstr_PPC_WRK (
          goto decode_failure;
 
       /* Integer Load and Store with Byte Reverse Instructions */
-      case 0x316: case 0x216: case 0x396: // lhbrx, lwbrx, sthbrx
-      case 0x296: case 0x214:             // stwbrx, ldbrx
-      case 0x294:                         // stdbrx
+      case 0x214: case 0x294: // ldbrx, stdbrx
+         if (!mode64) goto decode_failure;
+         if (dis_int_ldst_rev( theInstr )) goto decode_success;
+         goto decode_failure;
+
+      case 0x216: case 0x316: case 0x296:    // lwbrx, lhbrx, stwbrx
+      case 0x396:                            // sthbrx
          if (dis_int_ldst_rev( theInstr )) goto decode_success;
          goto decode_failure;
          
@@ -17385,7 +17400,12 @@ DisResult disInstr_PPC_WRK (
 //zz          goto decode_failure;
 
       /* Trap Instructions */
-      case 0x004: case 0x044:             // tw,   td
+      case 0x004:             // tw
+         if (dis_trap(theInstr, &dres)) goto decode_success;
+         goto decode_failure;
+
+      case 0x044:             // td
+         if (!mode64) goto decode_failure;
          if (dis_trap(theInstr, &dres)) goto decode_success;
          goto decode_failure;
 
@@ -17479,6 +17499,7 @@ DisResult disInstr_PPC_WRK (
     	  goto decode_failure;
 
       case 0x0FC: // bpermd
+         if (!mode64) goto decode_failure;
          if (dis_int_logic( theInstr )) goto decode_success;
          goto decode_failure;
 
commit 1fe353c602722e727fe4497037d2b9c1d646b9b7
Author: carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9>
Date:   Mon Oct 29 20:39:18 2012 +0000

    Valgrind, ppc:  Fix test for 32-bit testsuite.
    
    The 32-bit testsuite executes the 64-bit class instruction prtyd.  This
    instruction should not be tested in 32-bit mode.  The change also updates
    the expected output for the test.  Note, 32-bit HW will generate a SIGILL
    when the prtyd instruction is executed.  However, the 64-bit HW executing
    a 32-bit application does execute the instruction but only the lower 32-bits
    of the result are valid.  In general, the 64-bit class instructions should
    not be executed in 32-bit binaries.
    
    This fix accompanies the VEX fix in revision 2558 to add the 64-bit mode test
    to make sure the 64-bit class instructions are only executed in 64-bit mode.
    The VEX bugzilla is:
    
    Bug 308573 - Internal Valgrind error on 64-bit instruction executed in
    32-bit mode
    
    Carl Love cel@us.ibm.com
    
    git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13091 a5019735-40e9-0310-863c-91ae7b9d1cf9

diff --git a/memcheck/tests/ppc32/power_ISA2_05.c b/memcheck/tests/ppc32/power_ISA2_05.c
index f85b547..0cc60f6 100644
--- a/memcheck/tests/ppc32/power_ISA2_05.c
+++ b/memcheck/tests/ppc32/power_ISA2_05.c
@@ -29,9 +29,11 @@ void test_parity_instrs()
 
    for (i = 0; i < 50; i++) {
       word = base256(i);
+#ifdef __powerpc64__
       long_word = word;
       __asm__ volatile ("prtyd %0, %1":"=r" (parity):"r"(long_word));
       printf("prtyd (%x) => parity=%x\n", i, parity);
+#endif
       __asm__ volatile ("prtyw %0, %1":"=r" (parity):"r"(word));
       printf("prtyw (%x) => parity=%x\n", i, parity);
    }
diff --git a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
index 5513960..e4975fb 100644
--- a/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
+++ b/memcheck/tests/ppc32/power_ISA2_05.stdout.exp
@@ -20,103 +20,53 @@ stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
 lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
 stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
 lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
-prtyd (0) => parity=0
 prtyw (0) => parity=0
-prtyd (1) => parity=1
 prtyw (1) => parity=1
-prtyd (2) => parity=0
 prtyw (2) => parity=0
-prtyd (3) => parity=1
 prtyw (3) => parity=1
-prtyd (4) => parity=0
 prtyw (4) => parity=0
-prtyd (5) => parity=1
 prtyw (5) => parity=1
-prtyd (6) => parity=0
 prtyw (6) => parity=0
-prtyd (7) => parity=1
 prtyw (7) => parity=1
-prtyd (8) => parity=0
 prtyw (8) => parity=0
-prtyd (9) => parity=1
 prtyw (9) => parity=1
-prtyd (a) => parity=0
 prtyw (a) => parity=0
-prtyd (b) => parity=1
 prtyw (b) => parity=1
-prtyd (c) => parity=0
 prtyw (c) => parity=0
-prtyd (d) => parity=1
 prtyw (d) => parity=1
-prtyd (e) => parity=0
 prtyw (e) => parity=0
-prtyd (f) => parity=1
 prtyw (f) => parity=1
-prtyd (10) => parity=0
 prtyw (10) => parity=0
-prtyd (11) => parity=1
 prtyw (11) => parity=1
-prtyd (12) => parity=0
 prtyw (12) => parity=0
-prtyd (13) => parity=1
 prtyw (13) => parity=1
-prtyd (14) => parity=0
 prtyw (14) => parity=0
-prtyd (15) => parity=1
 prtyw (15) => parity=1
-prtyd (16) => parity=0
 prtyw (16) => parity=0
-prtyd (17) => parity=1
 prtyw (17) => parity=1
-prtyd (18) => parity=0
 prtyw (18) => parity=0
-prtyd (19) => parity=1
 prtyw (19) => parity=1
-prtyd (1a) => parity=0
 prtyw (1a) => parity=0
-prtyd (1b) => parity=1
 prtyw (1b) => parity=1
-prtyd (1c) => parity=0
 prtyw (1c) => parity=0
-prtyd (1d) => parity=1
 prtyw (1d) => parity=1
-prtyd (1e) => parity=0
 prtyw (1e) => parity=0
-prtyd (1f) => parity=1
 prtyw (1f) => parity=1
-prtyd (20) => parity=0
 prtyw (20) => parity=0
-prtyd (21) => parity=1
 prtyw (21) => parity=1
-prtyd (22) => parity=0
 prtyw (22) => parity=0
-prtyd (23) => parity=1
 prtyw (23) => parity=1
-prtyd (24) => parity=0
 prtyw (24) => parity=0
-prtyd (25) => parity=1
 prtyw (25) => parity=1
-prtyd (26) => parity=0
 prtyw (26) => parity=0
-prtyd (27) => parity=1
 prtyw (27) => parity=1
-prtyd (28) => parity=0
 prtyw (28) => parity=0
-prtyd (29) => parity=1
 prtyw (29) => parity=1
-prtyd (2a) => parity=0
 prtyw (2a) => parity=0
-prtyd (2b) => parity=1
 prtyw (2b) => parity=1
-prtyd (2c) => parity=0
 prtyw (2c) => parity=0
-prtyd (2d) => parity=1
 prtyw (2d) => parity=1
-prtyd (2e) => parity=0
 prtyw (2e) => parity=0
-prtyd (2f) => parity=1
 prtyw (2f) => parity=1
-prtyd (30) => parity=0
 prtyw (30) => parity=0
-prtyd (31) => parity=1
 prtyw (31) => parity=1