From 21a2cd973c5f94032c4c99007e3ef820ca272fe1 Mon Sep 17 00:00:00 2001 From: Andrew Lukoshko Date: Fri, 12 Sep 2025 08:16:27 +0000 Subject: [PATCH] import Fedora uboot-tools-2025.07-2.0.riscv64.fc42 --- .gitignore | 1 + Initial-MNT-Reform2-support.patch | 980 +++++ Rebase-to-upstream-6.15.5-rockchip-DTs.patch | 3467 +++++++++++++++++ USB-PD-TCPM-improvements.patch | 717 ++++ aarch64-boards | 106 + disable-VBE-by-default.patch | 32 + ...gic-to-get-a-GPT-entry-into-a-helper.patch | 127 + ...the-part_get_gpt_pte-helper-function.patch | 60 + ...add-EFI_PARTITION_INFO_PROTOCOL-supp.patch | 152 + ...-basic-partition-info-check-to-block.patch | 95 + enable-bootmenu-by-default.patch | 49 + improve-riscv64-configs.patch | 116 + p3450-fix-board.patch | 139 + riscv64-boards | 4 + ...hip-Enable-preboot-start-for-pci-usb.patch | 783 ++++ sources | 1 + ...ios_linux.h-Fix-build-error-on-ppc64.patch | 198 + uboot-tools.spec | 432 ++ ...ll-options-for-EFI-System-Partitions.patch | 57 + ...DT-from-any-partition-on-boot-device.patch | 87 + ...-SetVariableRT-with-volotile-storage.patch | 33 + uefi-enable-https-boot-by-default.patch | 81 + ..._location-for-finding-the-DT-on-disk.patch | 202 + 23 files changed, 7919 insertions(+) create mode 100644 .gitignore create mode 100644 Initial-MNT-Reform2-support.patch create mode 100644 Rebase-to-upstream-6.15.5-rockchip-DTs.patch create mode 100644 USB-PD-TCPM-improvements.patch create mode 100644 aarch64-boards create mode 100644 disable-VBE-by-default.patch create mode 100644 disk-efi-Move-logic-to-get-a-GPT-entry-into-a-helper.patch create mode 100644 disk-efi-expose-the-part_get_gpt_pte-helper-function.patch create mode 100644 efi_loader-disk-add-EFI_PARTITION_INFO_PROTOCOL-supp.patch create mode 100644 efi_selftest-Add-basic-partition-info-check-to-block.patch create mode 100644 enable-bootmenu-by-default.patch create mode 100644 improve-riscv64-configs.patch create mode 100644 p3450-fix-board.patch create mode 100644 riscv64-boards create mode 100644 rockchip-Enable-preboot-start-for-pci-usb.patch create mode 100644 sources create mode 100644 tools-termios_linux.h-Fix-build-error-on-ppc64.patch create mode 100644 uboot-tools.spec create mode 100644 uefi-Add-all-options-for-EFI-System-Partitions.patch create mode 100644 uefi-distro-load-FDT-from-any-partition-on-boot-device.patch create mode 100644 uefi-enable-SetVariableRT-with-volotile-storage.patch create mode 100644 uefi-enable-https-boot-by-default.patch create mode 100644 uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..c03a7d4 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +u-boot-2025.07.tar.bz2 diff --git a/Initial-MNT-Reform2-support.patch b/Initial-MNT-Reform2-support.patch new file mode 100644 index 0000000..c91d3fe --- /dev/null +++ b/Initial-MNT-Reform2-support.patch @@ -0,0 +1,980 @@ +From bcce96109c2fc3e8ed9e2ba12f1cbff43c0bd3c5 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 20 Jun 2025 17:45:02 +0100 +Subject: [PATCH 1/2] Initial MNT Reform2 support + +--- + arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi | 20 + + board/rockchip/evb_rk3588/MAINTAINERS | 6 + + configs/mnt-reform2-rk3588_defconfig | 93 ++++ + .../rockchip/rk3588-firefly-icore-3588q.dtsi | 443 ++++++++++++++++++ + .../src/arm64/rockchip/rk3588-mnt-reform2.dts | 336 +++++++++++++ + 5 files changed, 898 insertions(+) + create mode 100644 arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi + create mode 100644 configs/mnt-reform2-rk3588_defconfig + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi + create mode 100644 dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts + +diff --git a/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi b/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi +new file mode 100644 +index 00000000000..afd33dd3248 +--- /dev/null ++++ b/arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk3588-u-boot.dtsi" ++ ++&fspim2_pins { ++ bootph-pre-ram; ++ bootph-some-ram; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++}; ++ ++&sfc { ++ flash@0 { ++ bootph-pre-ram; ++ bootph-some-ram; ++ }; ++}; +diff --git a/board/rockchip/evb_rk3588/MAINTAINERS b/board/rockchip/evb_rk3588/MAINTAINERS +index 1232f05a387..24cf13c3c48 100644 +--- a/board/rockchip/evb_rk3588/MAINTAINERS ++++ b/board/rockchip/evb_rk3588/MAINTAINERS +@@ -29,6 +29,12 @@ F: configs/generic-rk3588_defconfig + F: arch/arm/dts/rk3588-generic.dts + F: arch/arm/dts/rk3588-generic-u-boot.dtsi + ++MNT-REFORM2-RK3588 ++M: Peter Robinson ++S: Maintained ++F: configs/mnt-reform2-rk3588_defconfig ++F: arch/arm/dts/rk3588-mnt-reform2-u-boot.dtsi ++ + ORANGEPI-5-RK3588 + M: Jonas Karlman + S: Maintained +diff --git a/configs/mnt-reform2-rk3588_defconfig b/configs/mnt-reform2-rk3588_defconfig +new file mode 100644 +index 00000000000..e12c48af70a +--- /dev/null ++++ b/configs/mnt-reform2-rk3588_defconfig +@@ -0,0 +1,93 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3588-mnt-reform2" ++CONFIG_ROCKCHIP_RK3588=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_TARGET_EVB_RK3588=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_SF_DEFAULT_BUS=5 ++CONFIG_DEBUG_UART_BASE=0xFEB50000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-mnt-reform2" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_HS400_ES_SUPPORT=y ++CONFIG_SPL_MMC_HS400_ES_SUPPORT=y ++CONFIG_MMC_HS400_SUPPORT=y ++CONFIG_SPL_MMC_HS400_SUPPORT=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_PHYLIB=y ++CONFIG_RTL8169=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_PHY_ROCKCHIP_USBDP=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_ROCKCHIP_SPI=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ERRNO_STR=y +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi +new file mode 100644 +index 00000000000..6726eeb4925 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi +@@ -0,0 +1,443 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include ++#include ++ ++#include "rk3588.dtsi" ++ ++/ { ++ compatible = "firefly,icore-3588q", "rockchip,rk3588"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ }; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_big0_s0>; ++}; ++ ++&cpu_b2 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_b3 { ++ cpu-supply = <&vdd_cpu_big1_s0>; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_lit_s0>; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0m2_xfer>; ++ status = "okay"; ++ ++ vdd_cpu_big0_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-name = "vdd_cpu_big0_s0"; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_big1_s0: regulator@43 { ++ compatible = "rockchip,rk8603", "rockchip,rk8602"; ++ reg = <0x43>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <1050000>; ++ regulator-name = "vdd_cpu_big1_s0"; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1m2_xfer>; ++ status = "okay"; ++ ++ vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { ++ compatible = "rockchip,rk8602"; ++ reg = <0x42>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-name = "vdd_npu_s0"; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ no-sdio; ++ no-sd; ++ non-removable; ++ max-frequency = <150000000>; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&spi2 { ++ assigned-clocks = <&cru CLK_SPI2>; ++ assigned-clock-rates = <200000000>; ++ num-cs = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; ++ status = "okay"; ++ ++ pmic@0 { ++ compatible = "rockchip,rk806"; ++ reg = <0x0>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, ++ <&rk806_dvs2_null>, <&rk806_dvs3_null>; ++ spi-max-frequency = <1000000>; ++ system-power-controller; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc5v0_sys>; ++ vcc6-supply = <&vcc5v0_sys>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc5v0_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ vcc10-supply = <&vcc5v0_sys>; ++ vcc11-supply = <&vcc_2v0_pldo_s3>; ++ vcc12-supply = <&vcc5v0_sys>; ++ vcc13-supply = <&vcc_1v1_nldo_s3>; ++ vcc14-supply = <&vcc_1v1_nldo_s3>; ++ vcca-supply = <&vcc5v0_sys>; ++ ++ rk806_dvs1_null: dvs1-null-pins { ++ pins = "gpio_pwrctrl1"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs2_null: dvs2-null-pins { ++ pins = "gpio_pwrctrl2"; ++ function = "pin_fun0"; ++ }; ++ ++ rk806_dvs3_null: dvs3-null-pins { ++ pins = "gpio_pwrctrl3"; ++ function = "pin_fun0"; ++ }; ++ ++ regulators { ++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_gpu_s0"; ++ regulator-enable-ramp-delay = <400>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_cpu_lit_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_log_s0: dcdc-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <750000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_log_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <550000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_vdenc_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_ddr_s0: dcdc-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <675000>; ++ regulator-max-microvolt = <950000>; ++ regulator-ramp-delay = <12500>; ++ regulator-name = "vdd_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ vdd2_ddr_s3: dcdc-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vdd2_ddr_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_2v0_pldo_s3: dcdc-reg7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2000000>; ++ regulator-max-microvolt = <2000000>; ++ regulator-name = "vdd_2v0_pldo_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <2000000>; ++ }; ++ }; ++ ++ vcc_3v3_s3: dcdc-reg8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vddq_ddr_s0: dcdc-reg9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vddq_ddr_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s3: dcdc-reg10 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avcc_1v8_s0: pldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "avcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8_s0: pldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ avdd_1v2_s0: pldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "avdd_1v2_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3_s0: pldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_3v3_s0"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vccio_sd_s0: pldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ pldo6_s3: pldo-reg6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pldo6_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdd_0v75_s3: nldo-reg1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s3"; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <750000>; ++ }; ++ }; ++ ++ vdd_ddr_pll_s0: nldo-reg2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_ddr_pll_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <850000>; ++ }; ++ }; ++ ++ avdd_0v75_s0: nldo-reg3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "avdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v85_s0: nldo-reg4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <850000>; ++ regulator-max-microvolt = <850000>; ++ regulator-name = "vdd_0v85_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_0v75_s0: nldo-reg5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "vdd_0v75_s0"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2m0_xfer>; ++ status = "okay"; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts +new file mode 100644 +index 00000000000..78a4e896f66 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts +@@ -0,0 +1,336 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. ++ * Copyright (c) 2024 MNT Research GmbH ++ */ ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "rk3588-firefly-icore-3588q.dtsi" ++ ++/ { ++ model = "MNT Reform 2 with RCORE RK3588 Module"; ++ compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; ++ chassis-type = "laptop"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ mmc1 = &sdmmc; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ brightness-levels = <0 8 16 32 64 128 160 200 255>; ++ default-brightness-level = <128>; ++ enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pwms = <&pwm8 0 10000 0>; ++ }; ++ ++ gmac0_clkin: external-gmac0-clock { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <125000000>; ++ clock-output-names = "gmac0_clkin"; ++ }; ++ ++ pcie30_avdd1v8: regulator-pcie30-avdd1v8 { ++ compatible = "regulator-fixed"; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "pcie30_avdd1v8"; ++ vin-supply = <&avcc_1v8_s0>; ++ }; ++ ++ pcie30_avdd0v75: regulator-pcie30-avdd0v75 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <750000>; ++ regulator-name = "pcie30_avdd0v75"; ++ vin-supply = <&avdd_0v75_s0>; ++ }; ++ ++ vcc12v_dcin: regulator-vcc12v-dcin { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-name = "vcc12v_dcin"; ++ }; ++ ++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_1v1_nldo_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_pcie30"; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc5v0_host: regulator-vcc5v0-host { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_host"; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_sys"; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc5v0_usb: regulator-vcc5v0-usb { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-name = "vcc5v0_usb"; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++}; ++ ++&combphy0_ps { ++ status = "okay"; ++}; ++ ++&gmac0 { ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy>; ++ phy-mode = "rgmii-id"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus ++ &gmac0_clkinout ++ ð_phy_reset>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu_s0>; ++ sram-supply = <&vdd_gpu_mem_s0>; ++ status = "okay"; ++}; ++ ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp2: endpoint { ++ remote-endpoint = <&vp2_out_hdmi0>; ++ }; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&i2c6 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6m0_xfer>; ++ status = "okay"; ++ ++ rtc@68 { ++ compatible = "nxp,pcf8523"; ++ reg = <0x68>; ++ }; ++}; ++ ++&mdio0 { ++ rgmii_phy: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ }; ++}; ++ ++&pcie2x1l2 { ++ pinctrl-0 = <&pcie2_0_rst>; ++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x4 { ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie3_reset>; ++ reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ dp { ++ dp1_hpd: dp1-hpd { ++ rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie2 { ++ pcie2_0_rst: pcie2-0-rst { ++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pcie3 { ++ pcie3_reset: pcie3-reset { ++ rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ eth_phy { ++ eth_phy_reset: eth-phy-reset { ++ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm8 { ++ pinctrl-0 = <&pwm8m2_pins>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&avcc_1v8_s0>; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <40000000>; ++ no-1-8-v; ++ no-mmc; ++ no-sdio; ++ vmmc-supply = <&vcc3v3_pcie30>; ++ vqmmc-supply = <&vcc3v3_pcie30>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ ++&u2phy2 { ++ status = "okay"; ++}; ++ ++&u2phy2_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&u2phy3 { ++ status = "okay"; ++}; ++ ++&u2phy3_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usbdp_phy0 { ++ status = "okay"; ++}; ++ ++&usbdp_phy1 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp2 { ++ vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp2>; ++ }; ++}; +-- +2.50.0 + +From e4eae92727e9c87b2fc8769666347c4b715dc81a Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 20 Jun 2025 17:56:32 +0100 +Subject: [PATCH 2/2] mnt: drop hdptxphy0 + +--- + dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts +index 78a4e896f66..c76dd271d1d 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-mnt-reform2.dts +@@ -157,10 +157,6 @@ + }; + }; + +-&hdptxphy0 { +- status = "okay"; +-}; +- + &i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; +-- +2.50.0 + diff --git a/Rebase-to-upstream-6.15.5-rockchip-DTs.patch b/Rebase-to-upstream-6.15.5-rockchip-DTs.patch new file mode 100644 index 0000000..ecb69d5 --- /dev/null +++ b/Rebase-to-upstream-6.15.5-rockchip-DTs.patch @@ -0,0 +1,3467 @@ +From c0f3a6ff6c7a7cfe857b4cda1b6f3615e25842d8 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 20 Jun 2025 13:29:43 +0100 +Subject: [PATCH] Rebase to upstream 6.15.5 rockchip DTs + +Signed-off-by: Peter Robinson +--- + .../arm64/rockchip/px30-engicam-common.dtsi | 3 +- + .../arm64/rockchip/px30-engicam-ctouch2.dtsi | 2 +- + .../px30-engicam-px30-core-edimm2.2.dts | 2 +- + .../arm64/rockchip/px30-ringneck-haikou.dts | 2 + + .../src/arm64/rockchip/px30-ringneck.dtsi | 4 - + .../src/arm64/rockchip/rk3308-roc-cc.dts | 2 +- + .../src/arm64/rockchip/rk3318-a95x-z2.dts | 4 +- + .../src/arm64/rockchip/rk3328-rock-pi-e.dts | 8 + + .../src/arm64/rockchip/rk3399-nanopi4.dtsi | 2 +- + .../src/arm64/rockchip/rk3399-puma-haikou.dts | 34 ++- + .../src/arm64/rockchip/rk3399-puma.dtsi | 58 +++-- + .../src/arm64/rockchip/rk3399-roc-pc-plus.dts | 2 +- + .../src/arm64/rockchip/rk3399-rock-pi-4.dtsi | 2 +- + dts/upstream/src/arm64/rockchip/rk3528.dtsi | 3 +- + .../rockchip/rk3566-bigtreetech-cb2.dtsi | 2 +- + .../src/arm64/rockchip/rk3566-pinenote.dtsi | 2 + + .../src/arm64/rockchip/rk3566-quartz64-a.dts | 8 +- + .../src/arm64/rockchip/rk3566-quartz64-b.dts | 8 +- + .../src/arm64/rockchip/rk3566-rock-3c.dts | 1 + + .../src/arm64/rockchip/rk3568-nanopi-r5s.dtsi | 5 +- + .../src/arm64/rockchip/rk3568-qnap-ts433.dts | 2 + + .../src/arm64/rockchip/rk3568-rock-3a.dts | 14 -- + .../src/arm64/rockchip/rk356x-base.dtsi | 44 ++-- + .../arm64/rockchip/rk3576-armsom-sige5.dts | 52 +++- + .../src/arm64/rockchip/rk3576-evb1-v10.dts | 47 ++++ + dts/upstream/src/arm64/rockchip/rk3576.dtsi | 192 ++++++++++++++- + .../src/arm64/rockchip/rk3588-armsom-lm7.dtsi | 4 + + .../arm64/rockchip/rk3588-armsom-sige7.dts | 75 ++++++ + .../src/arm64/rockchip/rk3588-base.dtsi | 117 +++++++-- + .../arm64/rockchip/rk3588-coolpi-cm5-evb.dts | 2 +- + .../rockchip/rk3588-coolpi-cm5-genbook.dts | 2 +- + .../src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 4 + + .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 + + .../rockchip/rk3588-edgeble-neu6a-io.dtsi | 47 ++++ + .../src/arm64/rockchip/rk3588-evb1-v10.dts | 50 +++- + .../src/arm64/rockchip/rk3588-extra.dtsi | 186 +++++++++++++++ + .../src/arm64/rockchip/rk3588-fet3588-c.dtsi | 4 + + .../rockchip/rk3588-firefly-core-3588j.dtsi | 4 + + .../rockchip/rk3588-firefly-itx-3588j.dts | 2 +- + .../rk3588-friendlyelec-cm3588-nas.dts | 2 +- + .../rockchip/rk3588-friendlyelec-cm3588.dtsi | 8 + + .../src/arm64/rockchip/rk3588-h96-max-v58.dts | 30 ++- + .../src/arm64/rockchip/rk3588-jaguar.dts | 224 +++++++++++++++++- + .../src/arm64/rockchip/rk3588-nanopc-t6.dtsi | 6 +- + .../src/arm64/rockchip/rk3588-ok3588-c.dts | 4 + + .../rockchip/rk3588-orangepi-5-compact.dtsi | 11 +- + .../arm64/rockchip/rk3588-orangepi-5-max.dts | 67 +++++- + .../arm64/rockchip/rk3588-orangepi-5-plus.dts | 56 ++++- + .../src/arm64/rockchip/rk3588-orangepi-5.dtsi | 6 +- + .../src/arm64/rockchip/rk3588-quartzpro64.dts | 6 +- + .../src/arm64/rockchip/rk3588-rock-5-itx.dts | 53 +++++ + .../src/arm64/rockchip/rk3588-rock-5b.dts | 83 ++++++- + .../arm64/rockchip/rk3588-tiger-haikou.dts | 4 +- + .../src/arm64/rockchip/rk3588-tiger.dtsi | 5 +- + .../src/arm64/rockchip/rk3588-toybrick-x0.dts | 4 + + .../src/arm64/rockchip/rk3588-turing-rk1.dtsi | 6 + + dts/upstream/src/arm64/rockchip/rk3588j.dtsi | 53 ++--- + .../src/arm64/rockchip/rk3588s-coolpi-4b.dts | 31 ++- + .../src/arm64/rockchip/rk3588s-evb1-v10.dts | 6 +- + .../arm64/rockchip/rk3588s-gameforce-ace.dts | 6 +- + .../rockchip/rk3588s-indiedroid-nova.dts | 8 +- + .../arm64/rockchip/rk3588s-khadas-edge2.dts | 4 + + .../src/arm64/rockchip/rk3588s-nanopi-r6.dtsi | 6 +- + .../src/arm64/rockchip/rk3588s-odroid-m2.dts | 6 +- + .../arm64/rockchip/rk3588s-orangepi-5.dtsi | 16 +- + .../src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +- + .../src/arm64/rockchip/rk3588s-rock-5c.dts | 42 +++- + 67 files changed, 1569 insertions(+), 196 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi +index 1edfd643b25..a334ef0629d 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-common.dtsi +@@ -31,7 +31,7 @@ + }; + + vcc3v3_btreg: vcc3v3-btreg { +- compatible = "regulator-gpio"; ++ compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable_h>; +@@ -39,7 +39,6 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +- states = <3300000 0x0>; + }; + + vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod { +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +index 80db778c968..b60e68faa83 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +@@ -26,5 +26,5 @@ + }; + + &vcc3v3_btreg { +- enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +index 165d09ccb94..5886b802c52 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts ++++ b/dts/upstream/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +@@ -39,5 +39,5 @@ + }; + + &vcc3v3_btreg { +- enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + }; +diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts +index 1a59e8b1dc4..91cf4cd3fae 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/px30-ringneck-haikou.dts +@@ -154,6 +154,8 @@ + }; + + &i2c3 { ++ status = "okay"; ++ + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; +diff --git a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi +index e80412abec0..142244d5270 100644 +--- a/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi ++++ b/dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi +@@ -325,10 +325,6 @@ + }; + }; + +-&i2c3 { +- status = "okay"; +-}; +- + &i2s0_8ch { + rockchip,trcm-sync-tx-only; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts +index 629121de5a1..5e718194899 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3308-roc-cc.dts +@@ -147,7 +147,7 @@ + + &pwm5 { + status = "okay"; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm5_pin_pull_down>; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +index a94114fb7cc..96c27fc5005 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3318-a95x-z2.dts +@@ -274,13 +274,13 @@ + + &pwm0 { + pinctrl-0 = <&pwm0_pin_pull_up>; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + status = "okay"; + }; + + &pwm1 { + pinctrl-0 = <&pwm1_pin_pull_up>; +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts +index 6310b58de77..a4bdd87d072 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3328-rock-pi-e.dts +@@ -428,10 +428,18 @@ + status = "okay"; + }; + ++&u2phy_otg { ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; + ++&usb20_otg { ++ status = "okay"; ++}; ++ + &usbdrd3 { + dr_mode = "host"; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi +index b169be06d4d..c8eb5481f43 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-nanopi4.dtsi +@@ -603,7 +603,7 @@ + }; + + &pwm2 { +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts +index 947bbd62a6b..70979079923 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3399-puma-haikou.dts +@@ -149,8 +149,15 @@ + }; + }; + ++&gmac { ++ status = "okay"; ++}; ++ + &hdmi { +- ddc-i2c-bus = <&i2c3>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { + status = "okay"; + }; + +@@ -186,9 +193,22 @@ + }; + }; + +-&i2c6 { ++&i2c7 { ++ eeprom@50 { ++ reg = <0x50>; ++ compatible = "atmel,24c01"; ++ pagesize = <8>; ++ size = <128>; ++ vcc-supply = <&vcc3v3_baseboard>; ++ }; ++}; ++ ++&i2s0 { ++ status = "okay"; ++}; ++ ++&i2s2 { + status = "okay"; +- clock-frequency = <400000>; + }; + + &pcie_phy { +@@ -292,14 +312,6 @@ + status = "okay"; + }; + +-&usb_host0_ehci { +- status = "okay"; +-}; +- +-&usb_host0_ohci { +- status = "okay"; +-}; +- + &vopb { + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +index 995b30a7aae..587e89d7fc5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-puma.dtsi +@@ -60,16 +60,6 @@ + vin-supply = <&vcc5v0_sys>; + }; + +- vcc5v0_host: regulator-vcc5v0-host { +- compatible = "regulator-fixed"; +- gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; +- pinctrl-names = "default"; +- pinctrl-0 = <&vcc5v0_host_en>; +- regulator-name = "vcc5v0_host"; +- regulator-always-on; +- vin-supply = <&vcc5v0_sys>; +- }; +- + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -183,7 +173,6 @@ + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x10>; + rx_delay = <0x23>; +- status = "okay"; + }; + + &gpu { +@@ -389,6 +378,14 @@ + }; + }; + ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++}; ++ ++&i2c6 { ++ clock-frequency = <400000>; ++}; ++ + &i2c7 { + status = "okay"; + clock-frequency = <400000>; +@@ -439,7 +436,6 @@ + pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; +- status = "okay"; + }; + + /* +@@ -521,10 +517,10 @@ + }; + }; + +- usb2 { +- vcc5v0_host_en: vcc5v0-host-en { ++ usb { ++ cy3304_reset: cy3304-reset { + rockchip,pins = +- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ <4 RK_PA3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + +@@ -589,11 +585,6 @@ + u2phy1_otg: otg-port { + status = "okay"; + }; +- +- u2phy1_host: host-port { +- phy-supply = <&vcc5v0_host>; +- status = "okay"; +- }; + }; + + &usbdrd3_1 { +@@ -603,12 +594,27 @@ + &usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +-}; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cy3304_reset>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hub_2_0: hub@1 { ++ compatible = "usb4b4,6502", "usb4b4,6506"; ++ reg = <1>; ++ peer-hub = <&hub_3_0>; ++ reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ vdd-supply = <&vcc1v2_phy>; ++ vdd2-supply = <&vcc3v3_sys>; + +-&usb_host1_ehci { +- status = "okay"; +-}; ++ }; + +-&usb_host1_ohci { +- status = "okay"; ++ hub_3_0: hub@2 { ++ compatible = "usb4b4,6500", "usb4b4,6504"; ++ reg = <2>; ++ peer-hub = <&hub_2_0>; ++ reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; ++ vdd-supply = <&vcc1v2_phy>; ++ vdd2-supply = <&vcc3v3_sys>; ++ }; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts +index e2e9279fa26..8e3858cf988 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3399-roc-pc-plus.dts +@@ -112,7 +112,7 @@ + + &i2c1 { + es8388: es8388@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + #sound-dai-cells = <0>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +index 541dca12bf1..046dbe32901 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +@@ -43,7 +43,7 @@ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; +- clock-names = "lpo"; ++ clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi +index 26c3559d6a6..7f1ffd6003f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi +@@ -404,9 +404,10 @@ + + uart3: serial@ffa08000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; ++ reg = <0x0 0xffa08000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; +- reg = <0x0 0xffa08000 0x0 0x100>; ++ interrupts = ; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +index a4835147176..e7ba477e75f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +@@ -775,7 +775,7 @@ + rockchip,default-sample-phase = <90>; + status = "okay"; + +- sdio-wifi@1 { ++ wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio2>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi +index 2d3ae154482..3613661417b 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3566-pinenote.dtsi +@@ -9,6 +9,8 @@ + #include "rk3566.dtsi" + + / { ++ chassis-type = "tablet"; ++ + aliases { + mmc0 = &sdhci; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts +index 98e75df8b15..3c127c5c260 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-a.dts +@@ -265,8 +265,12 @@ + }; + + &gmac1 { +- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>, ++ <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts +index 24928a12944..5707321a114 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-quartz64-b.dts +@@ -173,8 +173,12 @@ + }; + + &gmac1 { +- assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; +- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, ++ <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, ++ <&cru SCLK_GMAC1>, ++ <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +index 53e71528e4c..6224d72813e 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-rock-3c.dts +@@ -636,6 +636,7 @@ + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; ++ vcc-supply = <&vcc_1v8>; + }; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi b/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi +index 00c479aa187..a28b4af10d1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3568-nanopi-r5s.dtsi +@@ -486,9 +486,12 @@ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; ++ mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; +- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +index 7bd32d230ad..b80d628c426 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts +@@ -619,6 +619,8 @@ + bus-width = <8>; + max-frequency = <200000000>; + non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts +index ac79140a9ec..44cfdfeed66 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3568-rock-3a.dts +@@ -778,20 +778,6 @@ + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +- +- bluetooth { +- compatible = "brcm,bcm43438-bt"; +- clocks = <&rk809 1>; +- clock-names = "lpo"; +- device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; +- host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; +- shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; +- pinctrl-names = "default"; +- pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; +- vbat-supply = <&vcc3v3_sys>; +- vddio-supply = <&vcc_1v8>; +- /* vddio comes from regulator on module, use IO bank voltage instead */ +- }; + }; + + &uart2 { +diff --git a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +index e5539062911..fd2214b6fad 100644 +--- a/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk356x-base.dtsi +@@ -174,6 +174,18 @@ + method = "smc"; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ scmi_shmem: shmem@10f000 { ++ compatible = "arm,scmi-shmem"; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ no-map; ++ }; ++ }; ++ + timer { + compatible = "arm,armv8-timer"; + interrupts = , +@@ -199,19 +211,6 @@ + #clock-cells = <0>; + }; + +- sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x0 0x0010f000 0x100>; +- +- scmi_shmem: sram@0 { +- compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; +- }; +- }; +- + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; +@@ -284,6 +283,18 @@ + mbi-alias = <0x0 0xfd410000>; + mbi-ranges = <296 24>; + msi-controller; ++ ranges; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ dma-noncoherent; ++ ++ its: msi-controller@fd440000 { ++ compatible = "arm,gic-v3-its"; ++ reg = <0x0 0xfd440000 0 0x20000>; ++ dma-noncoherent; ++ msi-controller; ++ #msi-cells = <1>; ++ }; + }; + + usb_host0_ehci: usb@fd800000 { +@@ -957,7 +968,7 @@ + num-ib-windows = <6>; + num-ob-windows = <2>; + max-link-speed = <2>; +- msi-map = <0x0 &gic 0x0 0x1000>; ++ msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; +@@ -1032,6 +1043,11 @@ + status = "disabled"; + }; + ++ /* ++ * Testing showed that the HWRNG found in RK3566 produces unacceptably ++ * low quality of random data, so the HWRNG isn't enabled for all RK356x ++ * SoC variants despite its presence. ++ */ + rng: rng@fe388000 { + compatible = "rockchip,rk3568-rng"; + reg = <0x0 0xfe388000 0x0 0x4000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts +index 7c7331936a7..314067ba6f3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3576-armsom-sige5.dts +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include "rk3576.dtsi" + +@@ -26,6 +27,17 @@ + stdout-path = "serial0:1500000n8"; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds: leds { + compatible = "gpio-leds"; + +@@ -182,8 +194,7 @@ + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk +- ð0m0_rgmii_bus +- ðm0_clk0_25m_out>; ++ ð0m0_rgmii_bus>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +@@ -214,6 +225,26 @@ + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdptxphy { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + +@@ -579,7 +610,7 @@ + reg = <0x51>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; +- interrupts = ; ++ interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; +@@ -656,3 +687,18 @@ + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts +index 782ca000a64..e368691fd28 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include "rk3576.dtsi" + + / { +@@ -57,6 +58,17 @@ + }; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds: leds { + compatible = "gpio-leds"; + +@@ -270,6 +282,26 @@ + status = "okay"; + }; + ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdptxphy { ++ status = "okay"; ++}; ++ + &i2c1 { + status = "okay"; + +@@ -729,3 +761,18 @@ + dr_mode = "host"; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi +index 29b47799849..3824242f8ae 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi +@@ -111,7 +111,7 @@ + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <120>; +@@ -124,7 +124,7 @@ + reg = <0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -135,7 +135,7 @@ + reg = <0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -146,7 +146,7 @@ + reg = <0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; +- clocks = <&scmi_clk ARMCLK_L>; ++ clocks = <&scmi_clk SCMI_ARMCLK_L>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -157,7 +157,7 @@ + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <320>; +@@ -170,7 +170,7 @@ + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -181,7 +181,7 @@ + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -192,7 +192,7 @@ + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; +- clocks = <&scmi_clk ARMCLK_B>; ++ clocks = <&scmi_clk SCMI_ARMCLK_B>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; +@@ -393,6 +393,11 @@ + }; + }; + ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ }; ++ + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; +@@ -620,6 +625,11 @@ + }; + }; + ++ hdptxphy_grf: syscon@26032000 { ++ compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; ++ reg = <0x0 0x26032000 0x0 0x100>; ++ }; ++ + vo1_grf: syscon@26036000 { + compatible = "rockchip,rk3576-vo1-grf", "syscon"; + reg = <0x0 0x26036000 0x0 0x100>; +@@ -922,7 +932,7 @@ + gpu: gpu@27800000 { + compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; + reg = <0x0 0x27800000 0x0 0x200000>; +- assigned-clocks = <&scmi_clk CLK_GPU>; ++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <198000000>; + clocks = <&cru CLK_GPU>; + clock-names = "core"; +@@ -937,6 +947,109 @@ + status = "disabled"; + }; + ++ vop: vop@27d00000 { ++ compatible = "rockchip,rk3576-vop"; ++ reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; ++ reg-names = "vop", "gamma-lut"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "sys", ++ "vp0", ++ "vp1", ++ "vp2"; ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VP0>, ++ <&cru DCLK_VP1>, ++ <&cru DCLK_VP2>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2"; ++ iommus = <&vop_mmu>; ++ power-domains = <&power RK3576_PD_VOP>; ++ rockchip,grf = <&sys_grf>; ++ rockchip,pmu = <&pmu>; ++ status = "disabled"; ++ ++ vop_out: ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vp0: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ }; ++ ++ vp1: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ }; ++ ++ vp2: port@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ }; ++ }; ++ }; ++ ++ vop_mmu: iommu@27d07e00 { ++ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; ++ reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power RK3576_PD_VOP>; ++ status = "disabled"; ++ }; ++ ++ hdmi: hdmi@27da0000 { ++ compatible = "rockchip,rk3576-dw-hdmi-qp"; ++ reg = <0x0 0x27da0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX0>, ++ <&cru CLK_HDMITX0_EARC>, ++ <&cru CLK_HDMITX0_REF>, ++ <&cru MCLK_SAI6_8CH>, ++ <&cru CLK_HDMITXHDP>, ++ <&cru HCLK_VO0_ROOT>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; ++ power-domains = <&power RK3576_PD_VO0>; ++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&ioc_grf>; ++ rockchip,vo-grf = <&vo0_grf>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ + qos_hdcp1: qos@27f02000 { + compatible = "rockchip,rk3576-qos", "syscon"; + reg = <0x0 0x27f02000 0x0 0x20>; +@@ -1221,6 +1334,42 @@ + }; + }; + ++ ufshc: ufshc@2a2d0000 { ++ compatible = "rockchip,rk3576-ufshc"; ++ reg = <0x0 0x2a2d0000 0x0 0x10000>, ++ <0x0 0x2b040000 0x0 0x10000>, ++ <0x0 0x2601f000 0x0 0x1000>, ++ <0x0 0x2603c000 0x0 0x1000>, ++ <0x0 0x2a2e0000 0x0 0x10000>; ++ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; ++ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, ++ <&cru CLK_REF_UFS_CLKOUT>; ++ clock-names = "core", "pclk", "pclk_mphy", "ref_out"; ++ assigned-clocks = <&cru CLK_REF_OSC_MPHY>; ++ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; ++ interrupts = ; ++ power-domains = <&power RK3576_PD_USB>; ++ pinctrl-0 = <&ufs_refclk>; ++ pinctrl-names = "default"; ++ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, ++ <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; ++ reset-names = "biu", "sys", "ufs", "grf"; ++ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; ++ status = "disabled"; ++ }; ++ ++ sfc1: spi@2a300000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0x2a300000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ power-domains = <&power RK3576_PD_SDGMAC>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + sdmmc: mmc@2a310000 { + compatible = "rockchip,rk3576-dw-mshc"; + reg = <0x0 0x2a310000 0x0 0x4000>; +@@ -1260,6 +1409,18 @@ + status = "disabled"; + }; + ++ sfc0: spi@2a340000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0x2a340000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ power-domains = <&power RK3576_PD_NVM>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; +@@ -1795,6 +1956,19 @@ + status = "disabled"; + }; + ++ hdptxphy: hdmiphy@2b000000 { ++ compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0x2b000000 0x0 0x2000>; ++ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; ++ clock-names = "ref", "apb"; ++ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, ++ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; ++ reset-names = "apb", "init", "cmn", "lane"; ++ rockchip,grf = <&hdptxphy_grf>; ++ #phy-cells = <0>; ++ status = "disabled"; ++ }; ++ + sram: sram@3ff88000 { + compatible = "mmio-sram"; + reg = <0x0 0x3ff88000 0x0 0x78000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +index a3138d2d384..e44125e9a8f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +@@ -114,6 +114,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +index 08f09053a06..ae9274365be 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-armsom-sige7.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3588.dtsi" + + / { +@@ -33,6 +34,17 @@ + "Headphone", "Headphones"; + }; + ++ hdmi0-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi0_con_in: endpoint { ++ remote-endpoint = <&hdmi0_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -164,6 +176,30 @@ + status = "okay"; + }; + ++&hdmi0 { ++ status = "okay"; ++}; ++ ++&hdmi0_in { ++ hdmi0_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi0>; ++ }; ++}; ++ ++&hdmi0_out { ++ hdmi0_out_con: endpoint { ++ remote-endpoint = <&hdmi0_con_in>; ++ }; ++}; ++ ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -258,6 +294,10 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ + /* phy1 - right ethernet port */ + &pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; +@@ -268,6 +308,22 @@ + &pcie2x1l1 { + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; ++ ++ pcie@0,0 { ++ reg = <0x300000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ranges; ++ device_type = "pci"; ++ bus-range = <0x30 0x3f>; ++ ++ wifi: wifi@0,0 { ++ compatible = "pci14e4,449d"; ++ reg = <0x310000 0 0 0 0>; ++ clocks = <&hym8563>; ++ clock-names = "lpo"; ++ }; ++ }; + }; + + /* phy0 - left ethernet port */ +@@ -286,6 +342,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -723,3 +783,18 @@ + dr_mode = "host"; + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi0_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +index 2623afa7963..c52af310c70 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-base.dtsi +@@ -358,11 +358,6 @@ + }; + + firmware { +- optee: optee { +- compatible = "linaro,optee-tz"; +- method = "smc"; +- }; +- + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; +@@ -382,6 +377,22 @@ + }; + }; + ++ hdmi0_sound: hdmi0-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi0"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi0>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s5_8ch>; ++ }; ++ }; ++ + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; +@@ -428,16 +439,15 @@ + #clock-cells = <0>; + }; + +- pmu_sram: sram@10f000 { +- compatible = "mmio-sram"; +- reg = <0x0 0x0010f000 0x0 0x100>; +- ranges = <0 0x0 0x0010f000 0x100>; +- #address-cells = <1>; +- #size-cells = <1>; ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; + +- scmi_shmem: sram@0 { ++ scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; +- reg = <0x0 0x100>; ++ reg = <0x0 0x0010f000 0x0 0x100>; ++ no-map; + }; + }; + +@@ -864,7 +874,7 @@ + }; + }; + /* These power domains are grouped by VD_GPU */ +- power-domain@RK3588_PD_GPU { ++ pd_gpu: power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, +@@ -1261,14 +1271,16 @@ + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, +- <&cru PCLK_VOP_ROOT>; ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", +- "pclk_vop"; ++ "pclk_vop", ++ "pll_hdmiphy0"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; +@@ -1318,6 +1330,21 @@ + status = "disabled"; + }; + ++ spdif_tx2: spdif-tx@fddb0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; ++ dma-names = "tx"; ++ dmas = <&dmac1 6>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; +@@ -1335,6 +1362,21 @@ + status = "disabled"; + }; + ++ spdif_tx3: spdif-tx@fdde0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF3_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; ++ dma-names = "tx"; ++ dmas = <&dmac1 7>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; +@@ -1385,7 +1427,7 @@ + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; +- phys = <&hdptxphy_hdmi0>; ++ phys = <&hdptxphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda>; +@@ -1394,6 +1436,7 @@ + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; + status = "disabled"; + + ports { +@@ -2024,12 +2067,47 @@ + status = "disabled"; + }; + ++ spdif_tx0: spdif-tx@fe4e0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4e0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF0_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; ++ dma-names = "tx"; ++ dmas = <&dmac0 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif0m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spdif_tx1: spdif-tx@fe4f0000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfe4f0000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 5>; ++ interrupts = ; ++ pinctrl-0 = <&spdif1m0_tx>; ++ pinctrl-names = "default"; ++ power-domains = <&power RK3588_PD_AUDIO>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + interrupt-controller; ++ dma-noncoherent; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; +@@ -2041,6 +2119,7 @@ + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2048,6 +2127,7 @@ + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; ++ dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; +@@ -2815,11 +2895,12 @@ + #dma-cells = <1>; + }; + +- hdptxphy_hdmi0: phy@fed60000 { ++ hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; ++ #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +index 9d525c8ff72..9eda6972266 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +@@ -129,7 +129,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +index bc6b43a7715..6dc10da5215 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +@@ -166,7 +166,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +index 71ed680621b..cc37f082ade 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +@@ -277,6 +277,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +index 5e72d0eff0e..8a783dc64c0 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +@@ -126,6 +126,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_user_en: led_user_en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +index 7125790bbed..08920344a4b 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +@@ -4,12 +4,24 @@ + */ + + #include ++#include + + / { + chosen { + stdout-path = "serial2:1500000n8"; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; +@@ -81,6 +93,26 @@ + status = "okay"; + }; + ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c6 { + status = "okay"; + +@@ -275,3 +307,18 @@ + &usb_host2_xhci { + status = "okay"; + }; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp0>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts +index ba49f0bbaac..8e912da299a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-evb1-v10.dts +@@ -132,6 +132,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; +@@ -364,7 +375,27 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -441,7 +472,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -519,6 +550,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio { + hp_detect: headphone-detect { +@@ -1371,11 +1406,11 @@ + status = "okay"; + }; + +-&vop_mmu { ++&vop { + status = "okay"; + }; + +-&vop { ++&vop_mmu { + status = "okay"; + }; + +@@ -1385,3 +1420,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +index 840b638af1c..099edb3fd0f 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-extra.dtsi +@@ -7,6 +7,46 @@ + #include "rk3588-extra-pinctrl.dtsi" + + / { ++ hdmi1_sound: hdmi1-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <128>; ++ simple-audio-card,name = "hdmi1"; ++ status = "disabled"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi1>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s6_8ch>; ++ }; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* ++ * The 4k HDMI capture controller works only with 32bit ++ * phys addresses and doesn't support IOMMU. HDMI RX CMA ++ * must be reserved below 4GB. ++ * The size of 160MB was determined as follows: ++ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB ++ * To ensure sufficient support for practical use-cases, ++ * we doubled the 66MB value. ++ */ ++ hdmi_receiver_cma: hdmi-receiver-cma { ++ compatible = "shared-dma-pool"; ++ alloc-ranges = <0x0 0x0 0x0 0xffffffff>; ++ size = <0x0 (160 * 0x100000)>; /* 160MiB */ ++ alignment = <0x0 0x40000>; /* 64K */ ++ no-map; ++ status = "disabled"; ++ }; ++ }; ++ + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; +@@ -67,6 +107,26 @@ + }; + }; + ++ hdptxphy1_grf: syscon@fd5e4000 { ++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; ++ reg = <0x0 0xfd5e4000 0x0 0x100>; ++ }; ++ ++ spdif_tx5: spdif-tx@fddb8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfddb8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; ++ dma-names = "tx"; ++ dmas = <&dmac1 22>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO0>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; +@@ -84,6 +144,21 @@ + status = "disabled"; + }; + ++ spdif_tx4: spdif-tx@fdde8000 { ++ compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; ++ reg = <0x0 0xfdde8000 0x0 0x1000>; ++ assigned-clock-parents = <&cru PLL_AUPLL>; ++ assigned-clocks = <&cru CLK_SPDIF4_SRC>; ++ clock-names = "mclk", "hclk"; ++ clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; ++ dma-names = "tx"; ++ dmas = <&dmac1 8>; ++ interrupts = ; ++ power-domains = <&power RK3588_PD_VO1>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; +@@ -135,6 +210,79 @@ + status = "disabled"; + }; + ++ hdmi1: hdmi@fdea0000 { ++ compatible = "rockchip,rk3588-dw-hdmi-qp"; ++ reg = <0x0 0xfdea0000 0x0 0x20000>; ++ clocks = <&cru PCLK_HDMITX1>, ++ <&cru CLK_HDMITX1_EARC>, ++ <&cru CLK_HDMITX1_REF>, ++ <&cru MCLK_I2S6_8CH_TX>, ++ <&cru CLK_HDMIHDP1>, ++ <&cru HCLK_VO1>; ++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "avp", "cec", "earc", "main", "hpd"; ++ phys = <&hdptxphy1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; ++ reset-names = "ref", "hdp"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo-grf = <&vo1_grf>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi1_in: port@0 { ++ reg = <0>; ++ }; ++ ++ hdmi1_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ hdmi_receiver: hdmi_receiver@fdee0000 { ++ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; ++ reg = <0x0 0xfdee0000 0x0 0x6000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "cec", "hdmi", "dma"; ++ clocks = <&cru ACLK_HDMIRX>, ++ <&cru CLK_HDMIRX_AUD>, ++ <&cru CLK_CR_PARA>, ++ <&cru PCLK_HDMIRX>, ++ <&cru CLK_HDMIRX_REF>, ++ <&cru PCLK_S_HDMIRX>, ++ <&cru HCLK_VO1>; ++ clock-names = "aclk", ++ "audio", ++ "cr_para", ++ "pclk", ++ "ref", ++ "hclk_s_hdmirx", ++ "hclk_vo1"; ++ memory-region = <&hdmi_receiver_cma>; ++ power-domains = <&power RK3588_PD_VO1>; ++ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, ++ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; ++ reset-names = "axi", "apb", "ref", "biu"; ++ rockchip,grf = <&sys_grf>; ++ rockchip,vo1-grf = <&vo1_grf>; ++ status = "disabled"; ++ }; ++ + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; +@@ -398,6 +546,23 @@ + }; + }; + ++ hdptxphy1: phy@fed70000 { ++ compatible = "rockchip,rk3588-hdptx-phy"; ++ reg = <0x0 0xfed70000 0x0 0x2000>; ++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; ++ clock-names = "ref", "apb"; ++ #clock-cells = <0>; ++ #phy-cells = <0>; ++ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, ++ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, ++ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, ++ <&cru SRST_HDPTX1_LCPLL>; ++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", ++ "lcpll"; ++ rockchip,grf = <&hdptxphy1_grf>; ++ status = "disabled"; ++ }; ++ + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; +@@ -449,3 +614,24 @@ + status = "disabled"; + }; + }; ++ ++&vop { ++ clocks = <&cru ACLK_VOP>, ++ <&cru HCLK_VOP>, ++ <&cru DCLK_VOP0>, ++ <&cru DCLK_VOP1>, ++ <&cru DCLK_VOP2>, ++ <&cru DCLK_VOP3>, ++ <&cru PCLK_VOP_ROOT>, ++ <&hdptxphy0>, ++ <&hdptxphy1>; ++ clock-names = "aclk", ++ "hclk", ++ "dclk_vp0", ++ "dclk_vp1", ++ "dclk_vp2", ++ "dclk_vp3", ++ "pclk_vop", ++ "pll_hdmiphy0", ++ "pll_hdmiphy1"; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi +index 39005131738..4331cdc70f9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-fet3588-c.dtsi +@@ -205,6 +205,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_rgb_b: led-rgb-b { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +index 42c523b553c..80e16ea4154 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +@@ -108,6 +108,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &sdhci { + bus-width = <8>; + no-sdio; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +index 2be5251d3e3..e086114c763 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +@@ -337,7 +337,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +index b3a04ca370b..8171fbfd819 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +@@ -335,7 +335,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +index e3a9598b99f..af431fdcbea 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +@@ -222,6 +222,10 @@ + compatible = "realtek,rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; ++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; ++ assigned-clock-rates = <12288000>; ++ clocks = <&cru I2S0_8CH_MCLKOUT>; ++ clock-names = "mclk"; + }; + }; + +@@ -256,6 +260,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-leds { + led_sys_pin: led-sys-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts +index 4791b77f357..73d8ce4fde2 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-h96-max-v58.dts +@@ -140,6 +140,24 @@ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; ++ ++ spdif_dit: spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ }; ++ ++ spdif_sound: spdif-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif_tx0>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_dit>; ++ }; ++ }; + }; + + &combphy0_ps { +@@ -207,7 +225,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -316,6 +334,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -400,6 +422,12 @@ + status = "okay"; + }; + ++&spdif_tx0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif0m1_tx>; ++ status = "okay"; ++}; ++ + &spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +index 7f457ab7801..9fceea6c139 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-jaguar.dts +@@ -303,7 +303,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -333,6 +333,56 @@ + }; + }; + ++ typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio4>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cc_int1>; ++ vbus-supply = <&vcc_5v0_usb_c1>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USBC-1 P11"; ++ power-role = "source"; ++ self-powered; ++ source-pdos = ++ ; ++ vbus-supply = <&vcc_5v0_usb_c1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc0_hs: endpoint { ++ remote-endpoint = <&usb_host0_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc0_ss: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ usbc0_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy0_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; +@@ -394,6 +444,56 @@ + pinctrl-0 = <&i2c8m2_xfer>; + status = "okay"; + ++ typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio4>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cc_int2>; ++ vbus-supply = <&vcc_5v0_usb_c2>; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USBC-2 P12"; ++ power-role = "source"; ++ self-powered; ++ source-pdos = ++ ; ++ vbus-supply = <&vcc_5v0_usb_c2>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc1_hs: endpoint { ++ remote-endpoint = <&usb_host1_xhci_drd_sw>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc1_ss: endpoint { ++ remote-endpoint = <&usbdp_phy1_typec_ss>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ usbc1_sbu: endpoint { ++ remote-endpoint = <&usbdp_phy1_typec_sbu>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; +@@ -451,6 +551,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + emmc { + emmc_reset: emmc-reset { +@@ -483,6 +587,26 @@ + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; + }; + }; ++ ++ usb3 { ++ cc_int1: cc-int1 { ++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ cc_int2: cc-int2 { ++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ typec0_sbu_dc_pins: typec0-sbu-dc-pins { ++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, ++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ typec1_sbu_dc_pins: typec1-sbu-dc-pins { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, ++ <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; + }; + + &saradc { +@@ -850,6 +974,24 @@ + status = "okay"; + }; + ++/* USB-C P11 connector */ ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ ++/* USB-C P12 connector */ ++&u2phy1 { ++ status = "okay"; ++}; ++ ++&u2phy1_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -892,6 +1034,56 @@ + status = "okay"; + }; + ++/* Type-C on P11 */ ++&usbdp_phy0 { ++ orientation-switch; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec0_sbu_dc_pins>; ++ sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ ++ sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy0_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_ss>; ++ }; ++ ++ usbdp_phy0_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc0_sbu>; ++ }; ++ }; ++}; ++ ++/* Type-C on P12 */ ++&usbdp_phy1 { ++ orientation-switch; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&typec1_sbu_dc_pins>; ++ sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ ++ sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usbdp_phy1_typec_ss: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc1_ss>; ++ }; ++ ++ usbdp_phy1_typec_sbu: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&usbc1_sbu>; ++ }; ++ }; ++}; ++ + /* host0 on P10 USB-A */ + &usb_host0_ehci { + status = "okay"; +@@ -902,6 +1094,36 @@ + status = "okay"; + }; + ++/* host0 on P11 USB-C */ ++&usb_host0_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb_host0_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc0_hs>; ++ }; ++ }; ++}; ++ ++/* host1 on P12 USB-C */ ++&usb_host1_xhci { ++ usb-role-switch; ++ status = "okay"; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ usb_host1_xhci_drd_sw: endpoint { ++ remote-endpoint = <&usbc1_hs>; ++ }; ++ }; ++}; ++ + /* host1 on M.2 E-key */ + &usb_host1_ehci { + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +index cb350727d11..bbe500cc924 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +@@ -360,7 +360,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -565,6 +565,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts +index 1c0851b45eb..fbe1d5c06d9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-ok3588-c.dts +@@ -312,6 +312,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + pcie2 { + pcie2_0_rst: pcie2-0-rst { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +index 87090cb9802..f748c6f760d 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +@@ -7,9 +7,6 @@ + #include "rk3588-orangepi-5.dtsi" + + / { +- model = "Xunlong Orange Pi 5 Max"; +- compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; +- + vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; +@@ -62,18 +59,12 @@ + + &led_blue_pwm { + /* PWM_LED1 */ +- pwms = <&pwm4 0 25000 0>; + status = "okay"; + }; + +-&led_green_pwm { +- /* PWM_LED2 */ +- pwms = <&pwm5 0 25000 0>; +-}; +- + /* phy2 */ + &pcie2x1l1 { +- reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie_eth>; + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts +index ce44549babf..8b1d35760c3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-max.dts +@@ -21,6 +21,17 @@ + }; + }; + }; ++ ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; + }; + + &hdmi0 { +@@ -39,10 +50,57 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { + status = "okay"; + }; + ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ ++&led_blue_pwm { ++ pwms = <&pwm4 0 25000 0>; ++}; ++ ++&led_green_pwm { ++ pwms = <&pwm5 0 25000 0>; ++}; ++ + &pinctrl { + + usb { +@@ -58,3 +116,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +index 255e33c5dbd..121e4d1c3fa 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +@@ -26,6 +26,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; +@@ -113,6 +124,10 @@ + status = "okay"; + }; + ++&hdmi0_sound { ++ status = "okay"; ++}; ++ + &hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; +@@ -125,7 +140,31 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi1 { ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -189,6 +228,14 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ + &led_blue_gpio { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +@@ -342,3 +389,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi +index a98e804a094..91d56c34a1e 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-orangepi-5.dtsi +@@ -276,7 +276,7 @@ + + /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s0>; +@@ -348,6 +348,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts +index 088cfade6f6..78aaa6635b5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-quartzpro64.dts +@@ -311,7 +311,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; +@@ -347,6 +347,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +index 2a059020946..7de17117df7 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5-itx.dts +@@ -11,6 +11,7 @@ + #include + #include + #include ++#include + #include "dt-bindings/usb/pd.h" + #include "rk3588.dtsi" + +@@ -72,6 +73,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ + pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; +@@ -261,6 +273,28 @@ + status = "okay"; + }; + ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdptxphy1 { ++ status = "okay"; ++}; ++ + &i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +@@ -564,6 +598,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + rtc_int: rtc-int { +@@ -1208,3 +1246,18 @@ + rockchip,dp-lane-mux = <2 3>; + status = "okay"; + }; ++ ++&vop { ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +index d597112f1d5..d22068475c5 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-rock-5b.dts +@@ -49,6 +49,17 @@ + }; + }; + ++ hdmi1-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi1_con_in: endpoint { ++ remote-endpoint = <&hdmi1_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; +@@ -220,7 +231,48 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdmi1 { ++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd ++ &hdmim1_tx1_scl &hdmim1_tx1_sda>; ++ status = "okay"; ++}; ++ ++&hdmi1_in { ++ hdmi1_in_vp1: endpoint { ++ remote-endpoint = <&vp1_out_hdmi1>; ++ }; ++}; ++ ++&hdmi1_out { ++ hdmi1_out_con: endpoint { ++ remote-endpoint = <&hdmi1_con_in>; ++ }; ++}; ++ ++&hdmi1_sound { ++ status = "okay"; ++}; ++ ++&hdmi_receiver_cma { ++ status = "okay"; ++}; ++ ++&hdmi_receiver { ++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; ++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdptxphy0 { ++ status = "okay"; ++}; ++ ++&hdptxphy1 { + status = "okay"; + }; + +@@ -318,6 +370,14 @@ + }; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ ++&i2s6_8ch { ++ status = "okay"; ++}; ++ + &package_thermal { + polling-delay = <1000>; + +@@ -376,7 +436,17 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { ++ hdmirx { ++ hdmirx_hpd: hdmirx-5v-detection { ++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -891,11 +961,11 @@ + status = "okay"; + }; + +-&vop_mmu { ++&vop { + status = "okay"; + }; + +-&vop { ++&vop_mmu { + status = "okay"; + }; + +@@ -905,3 +975,10 @@ + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; ++ ++&vp1 { ++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { ++ reg = ; ++ remote-endpoint = <&hdmi1_in_vp1>; ++ }; ++}; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +index 3187b4918a3..a3d8ff64783 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger-haikou.dts +@@ -189,7 +189,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -310,8 +310,10 @@ + status = "okay"; + }; + ++/* DB9 RS232/RS485 when SW2 in "UART1" mode */ + &uart5 { + rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; ++ status = "okay"; + }; + + &usbdp_phy0 { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +index e8fa449517c..c4933a08dd1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-tiger.dtsi +@@ -173,7 +173,6 @@ + + &i2c2 { + pinctrl-0 = <&i2c2m3_xfer>; +- status = "okay"; + }; + + &i2c2m3_xfer { +@@ -336,6 +335,10 @@ + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + emmc { + emmc_reset: emmc-reset { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts +index 3cbee5b9747..5a428e00ab9 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588-toybrick-x0.dts +@@ -289,6 +289,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + rtl8211f { + rtl8211f_rst: rtl8211f-rst { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +index 6bc46734cc1..60ad272982a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588-turing-rk1.dtsi +@@ -214,6 +214,8 @@ + }; + + &package_thermal { ++ polling-delay = <1000>; ++ + trips { + package_active1: trip-active1 { + temperature = <45000>; +@@ -287,6 +289,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + fan { + fan_int: fan-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +index bce72bac450..3045cb3bd68 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588j.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588j.dtsi +@@ -11,20 +11,15 @@ + compatible = "operating-points-v2"; + opp-shared; + +- opp-1416000000 { +- opp-hz = /bits/ 64 <1416000000>; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; +- opp-1608000000 { +- opp-hz = /bits/ 64 <1608000000>; +- opp-microvolt = <887500 887500 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-1704000000 { +- opp-hz = /bits/ 64 <1704000000>; +- opp-microvolt = <937500 937500 950000>; ++ opp-1296000000 { ++ opp-hz = /bits/ 64 <1296000000>; ++ opp-microvolt = <775000 775000 950000>; + clock-latency-ns = <40000>; + }; + }; +@@ -33,9 +28,14 @@ + compatible = "operating-points-v2"; + opp-shared; + ++ opp-1200000000{ ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <750000 750000 950000>; ++ opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { +@@ -43,25 +43,20 @@ + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <875000 875000 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <950000 950000 950000>; +- clock-latency-ns = <40000>; +- }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + ++ opp-1200000000{ ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <750000 750000 950000>; ++ clock-latency-ns = <40000>; ++ }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; +- opp-microvolt = <750000 750000 950000>; ++ opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { +@@ -69,16 +64,6 @@ + opp-microvolt = <787500 787500 950000>; + clock-latency-ns = <40000>; + }; +- opp-1800000000 { +- opp-hz = /bits/ 64 <1800000000>; +- opp-microvolt = <875000 875000 950000>; +- clock-latency-ns = <40000>; +- }; +- opp-2016000000 { +- opp-hz = /bits/ 64 <2016000000>; +- opp-microvolt = <950000 950000 950000>; +- clock-latency-ns = <40000>; +- }; + }; + + gpu_opp_table: opp-table { +@@ -104,10 +89,6 @@ + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>; + }; +- opp-850000000 { +- opp-hz = /bits/ 64 <800000000>; +- opp-microvolt = <787500 787500 850000>; +- }; + }; + }; + +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +index 9c394f733bb..8b717c4017a 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-coolpi-4b.dts +@@ -236,7 +236,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -361,6 +361,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +@@ -429,7 +433,7 @@ + }; + + &pwm13 { +- pinctrl-names = "active"; ++ pinctrl-names = "default"; + pinctrl-0 = <&pwm13m2_pins>; + status = "okay"; + }; +@@ -803,6 +807,14 @@ + status = "okay"; + }; + ++&u2phy0 { ++ status = "okay"; ++}; ++ ++&u2phy0_otg { ++ status = "okay"; ++}; ++ + &u2phy2 { + status = "okay"; + }; +@@ -832,6 +844,16 @@ + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + }; + ++&usbdp_phy0 { ++ /* ++ * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally ++ * the differential pairs 0+1 and the aux channel are wired to a ++ * mini DP connector. ++ */ ++ rockchip,dp-lane-mux = <0 1>; ++ status = "okay"; ++}; ++ + &usb_host0_ehci { + status = "okay"; + }; +@@ -840,6 +862,11 @@ + status = "okay"; + }; + ++&usb_host0_xhci { ++ extcon = <&u2phy0>; ++ status = "okay"; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +index bc4077575be..9f4aca9c2e3 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-evb1-v10.dts +@@ -242,7 +242,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -340,6 +340,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio { + hp_detect: headphone-detect { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +index 812bba0aef1..873a2bd6a6d 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-gameforce-ace.dts +@@ -611,7 +611,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -675,6 +675,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + audio-amplifier { + headphone_amplifier_en: headphone-amplifier-en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +index 4a3aa80f222..4189a88ecf4 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +@@ -278,7 +278,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -412,7 +412,7 @@ + status = "okay"; + + es8388: audio-codec@11 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +@@ -455,6 +455,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + bluetooth-pins { + bt_reset: bt-reset { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts +index ac48e7fd392..88a5e822ed1 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-khadas-edge2.dts +@@ -233,6 +233,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + vdd_sd { + vdd_sd_en: vdd-sd-en { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +index d2eddea1840..fbf062ec3bf 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +@@ -251,7 +251,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -359,6 +359,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + gpio-key { + key1_pin: key1-pin { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts +index 8f034c6d494..a72063c5514 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-odroid-m2.dts +@@ -264,7 +264,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -433,6 +433,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + lcd { + lcd_pwren: lcd-pwren { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +index d86aeacca23..4fedc50cce8 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +@@ -197,7 +197,11 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdmi0_sound { ++ status = "okay"; ++}; ++ ++&hdptxphy0 { + status = "okay"; + }; + +@@ -268,7 +272,7 @@ + status = "okay"; + + es8388: audio-codec@10 { +- compatible = "everest,es8388"; ++ compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s0>; +@@ -355,6 +359,10 @@ + status = "okay"; + }; + ++&i2s5_8ch { ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -365,6 +373,10 @@ + }; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + hym8563 { + hym8563_int: hym8563-int { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +index 70a43432bdc..f894742b1eb 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5a.dts +@@ -334,7 +334,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -359,6 +359,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + io_led: io-led { +diff --git a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +index 9b14d5383cd..dd7317bab61 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3588s-rock-5c.dts +@@ -68,10 +68,10 @@ + }; + }; + +- fan { ++ fan: fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; +- cooling-levels = <0 64 128 192 255>; ++ cooling-levels = <0 24 44 64 128 192 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 10000 0>; + }; +@@ -278,7 +278,7 @@ + }; + }; + +-&hdptxphy_hdmi0 { ++&hdptxphy0 { + status = "okay"; + }; + +@@ -417,6 +417,36 @@ + }; + }; + ++&package_thermal { ++ polling-delay = <1000>; ++ ++ trips { ++ package_fan0: package-fan0 { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ package_fan1: package-fan1 { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&package_fan0>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map1 { ++ trip = <&package_fan1>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_2_perstn_m0>; +@@ -425,6 +455,10 @@ + status = "okay"; + }; + ++&pd_gpu { ++ domain-supply = <&vdd_gpu_s0>; ++}; ++ + &pinctrl { + leds { + led_pins: led-pins { +@@ -843,6 +877,8 @@ + }; + + &tsadc { ++ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; + }; + +-- +2.49.0 + diff --git a/USB-PD-TCPM-improvements.patch b/USB-PD-TCPM-improvements.patch new file mode 100644 index 0000000..f84e6f3 --- /dev/null +++ b/USB-PD-TCPM-improvements.patch @@ -0,0 +1,717 @@ +From patchwork Wed Feb 26 18:44:44 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sebastian Reichel +X-Patchwork-Id: 2052544 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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Wed, 26 Feb 2025 19:45:07 +0100 (CET) +From: Sebastian Reichel +To: Marek Vasut , u-boot@lists.denx.de, + Jonas Karlman , Soeren Moch +Cc: Tim Harvey , + Philipp Tomsich , + Anand Moon , Maxim Kiselev , + Sebastian Reichel +Subject: [PATCH v2 1/4] usb: tcpm: improve handling of some power-supplies +Date: Wed, 26 Feb 2025 19:44:44 +0100 +Message-ID: <20250226184506.64114-2-sebastian.reichel@collabora.com> +X-Mailer: git-send-email 2.47.2 +In-Reply-To: <20250226184506.64114-1-sebastian.reichel@collabora.com> +References: <20250226184506.64114-1-sebastian.reichel@collabora.com> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +When the Rock 5B is booted with the current TCPM with its power supplied +by a "Cambrionix PDSync-C4" port it reaches the power-supply ready state. +Once that has happened the hub starts sending GetSinkCap messages, but +U-Boot already stopped processing PD messages. After retrying a bunch of +times the hub instead sends soft resets. Since U-Boot will also not +react to them, the USB hub will follow-up with a hard reset and that +cuts off the supply voltage. + +Since the state machine is already prepared to handle GetSinkCap +messages, try to avoid this by handling incoming messages for another +50ms after reaching the ready state. + +Fixes: 1db4c0ac77e3 ("usb: tcpm: add core framework") +Signed-off-by: Sebastian Reichel +--- + drivers/usb/tcpm/tcpm.c | 31 ++++++++++++++++++++++++++----- + 1 file changed, 26 insertions(+), 5 deletions(-) + +diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c +index 0aee57cb2f4a..b754b4dcd0b5 100644 +--- a/drivers/usb/tcpm/tcpm.c ++++ b/drivers/usb/tcpm/tcpm.c +@@ -2229,6 +2229,17 @@ static int tcpm_port_init(struct udevice *dev) + return 0; + } + ++static inline void tcpm_poll_one_event(struct udevice *dev) ++{ ++ const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); ++ struct tcpm_port *port = dev_get_uclass_plat(dev); ++ ++ drvops->poll_event(dev); ++ port->poll_event_cnt++; ++ udelay(500); ++ tcpm_check_and_run_delayed_work(dev); ++} ++ + static void tcpm_poll_event(struct udevice *dev) + { + const struct dm_tcpm_ops *drvops = dev_get_driver_ops(dev); +@@ -2242,15 +2253,25 @@ static void tcpm_poll_event(struct udevice *dev) + (port->state == SNK_READY || port->state == SRC_READY)) + break; + +- drvops->poll_event(dev); +- port->poll_event_cnt++; +- udelay(500); +- tcpm_check_and_run_delayed_work(dev); ++ tcpm_poll_one_event(dev); + } + +- if (port->state != SNK_READY && port->state != SRC_READY) ++ /* ++ * Some power-supplies send GetSinkCap shortly after they are ready. ++ * If they do not receive a response after a few retries they will issue ++ * a soft-reset followed by a hard reset, which kills the board power. ++ * Let's poll for 50ms after reaching the ready state to check if the ++ * power-supply wants something from us. ++ */ ++ if (port->state == SNK_READY) { ++ port->poll_event_cnt = 0; ++ ++ while (port->poll_event_cnt < 100) ++ tcpm_poll_one_event(dev); ++ } else { + dev_warn(dev, "TCPM: exit in state %s\n", + tcpm_states[port->state]); ++ } + + /* + * At this time, call the callback function of the respective pd chip + +From patchwork Wed Feb 26 18:44:45 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sebastian Reichel +X-Patchwork-Id: 2052546 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=collabora.com header.i=@collabora.com + header.a=rsa-sha256 header.s=mail header.b=hgX6o5vZ; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; + spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de + (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; + envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org) +Received: from phobos.denx.de (phobos.denx.de + [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) + (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) + key-exchange X25519 server-signature ECDSA (secp384r1)) + (No client certificate requested) + by legolas.ozlabs.org (Postfix) with ESMTPS id 4Z33MJ5sFGz1yCp + for ; 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+ Wed, 26 Feb 2025 19:45:07 +0100 (CET) +Received: by jupiter.universe (Postfix, from userid 1000) + id 34511480037; Wed, 26 Feb 2025 19:45:07 +0100 (CET) +From: Sebastian Reichel +To: Marek Vasut , u-boot@lists.denx.de, + Jonas Karlman , Soeren Moch +Cc: Tim Harvey , + Philipp Tomsich , + Anand Moon , Maxim Kiselev , + Sebastian Reichel +Subject: [PATCH v2 2/4] usb: tcpm: avoid resets for missing source capability + messages +Date: Wed, 26 Feb 2025 19:44:45 +0100 +Message-ID: <20250226184506.64114-3-sebastian.reichel@collabora.com> +X-Mailer: git-send-email 2.47.2 +In-Reply-To: <20250226184506.64114-1-sebastian.reichel@collabora.com> +References: <20250226184506.64114-1-sebastian.reichel@collabora.com> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +The current TCPM code implements source capability message handling +according to the USB-PD specification. Unfortunately some USB PD +sources do not properly follow the specification and do not send +source capability messages after a soft reset when they already +negotiated a specific contract before. The currently implemented way +(and what is described in the specificiation) to resolve this problem +is triggering a hard reset. + +But a hard reset is fatal on batteryless platforms powered via USB-C PD, +since that removes VBUS for some time. Since this is triggered at boot +time, the system may get stuck in a boot loop. + +For example I noticed the following behaviour on a Radxa Rock 5B +combined with an affected power-supply: + +1. The system is booted up with current code +2. A reboot is requested +3. U-Boot TCPM / fusb302 driver sends soft reset and waits for the + source capability message +4. No new source capability message is send by the power-supply + after the soft reset +5. U-Boot sends a hard reset +6. The board resets, but the fusb302 registers are not reset. This + is because of a hardware glitch. The serial pins are high when + no data is exchanged. Apparently the RK3588 has protection diodes, + which leak some voltage into the power-domain. The Rock 5B serial + pins and the fusb302 are using the same 3.3V power domain and the + leaked voltage is enough to keep the fusb302 registers alive. +7. After the hard reset the power-supply sends another source capability + message, which is auto-acked by fusb302 (because the register state + is kept) even though the U-Boot driver has not yet probed. Once the + U-Boot driver probes it sends another soft reset and waits for a new + source capability message, which never arrives. + +Fortunately the affected power-supplies (I have two setups showing this +behaviour) support sending a source capability message when explicitly +being asked. Thus an easy workaround to handle this is deviating from +the USB-PD specification and sending a Get_Source_Cap message and +waiting some time longer before doing the hard reset. + +Note, that I recently added the same workaround to the Linux kernel +with a slightly different rationale (since it needs to take over from +U-Boot). + +Fixes: 1db4c0ac77e3 ("usb: tcpm: add core framework") +Signed-off-by: Sebastian Reichel +--- + drivers/usb/tcpm/tcpm-internal.h | 1 + + drivers/usb/tcpm/tcpm.c | 32 +++++++++++++++++++++++++++++--- + 2 files changed, 30 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/tcpm/tcpm-internal.h b/drivers/usb/tcpm/tcpm-internal.h +index 561442090027..4861f4d13866 100644 +--- a/drivers/usb/tcpm/tcpm-internal.h ++++ b/drivers/usb/tcpm/tcpm-internal.h +@@ -30,6 +30,7 @@ + S(SNK_DISCOVERY_DEBOUNCE), \ + S(SNK_DISCOVERY_DEBOUNCE_DONE), \ + S(SNK_WAIT_CAPABILITIES), \ ++ S(SNK_WAIT_CAPABILITIES_TIMEOUT), \ + S(SNK_NEGOTIATE_CAPABILITIES), \ + S(SNK_TRANSITION_SINK), \ + S(SNK_TRANSITION_SINK_VBUS), \ +diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c +index b754b4dcd0b5..786d92fa4c6f 100644 +--- a/drivers/usb/tcpm/tcpm.c ++++ b/drivers/usb/tcpm/tcpm.c +@@ -1424,7 +1424,8 @@ static inline enum tcpm_state hard_reset_state(struct tcpm_port *port) + return ERROR_RECOVERY; + if (port->pwr_role == TYPEC_SOURCE) + return SRC_UNATTACHED; +- if (port->state == SNK_WAIT_CAPABILITIES) ++ if (port->state == SNK_WAIT_CAPABILITIES || ++ port->state == SNK_WAIT_CAPABILITIES_TIMEOUT) + return SNK_READY; + return SNK_UNATTACHED; + } +@@ -1650,10 +1651,35 @@ static void run_state_machine(struct udevice *dev) + tcpm_set_state(dev, SOFT_RESET_SEND, + PD_T_SINK_WAIT_CAP); + } else { +- tcpm_set_state(dev, hard_reset_state(port), +- PD_T_SINK_WAIT_CAP); ++ if (!port->self_powered) ++ tcpm_set_state(dev, SNK_WAIT_CAPABILITIES_TIMEOUT, ++ PD_T_SINK_WAIT_CAP); ++ else ++ tcpm_set_state(dev, hard_reset_state(port), ++ PD_T_SINK_WAIT_CAP); + } + break; ++ case SNK_WAIT_CAPABILITIES_TIMEOUT: ++ /* ++ * There are some USB PD sources in the field, which do not ++ * properly implement the specification and fail to start ++ * sending Source Capability messages after a soft reset. The ++ * specification suggests to do a hard reset when no Source ++ * capability message is received within PD_T_SINK_WAIT_CAP, ++ * but that might effectively kil the machine's power source. ++ * ++ * This slightly diverges from the specification and tries to ++ * recover from this by explicitly asking for the capabilities ++ * using the Get_Source_Cap control message before falling back ++ * to a hard reset. The control message should also be supported ++ * and handled by all USB PD source and dual role devices ++ * according to the specification. ++ */ ++ if (tcpm_pd_send_control(dev, PD_CTRL_GET_SOURCE_CAP)) ++ tcpm_set_state_cond(dev, hard_reset_state(port), 0); ++ else ++ tcpm_set_state(dev, hard_reset_state(port), PD_T_SINK_WAIT_CAP); ++ break; + case SNK_NEGOTIATE_CAPABILITIES: + port->pd_capable = true; + port->hard_reset_count = 0; + +From patchwork Wed Feb 26 18:44:46 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sebastian Reichel +X-Patchwork-Id: 2052545 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; + dkim=pass (2048-bit key; + unprotected) header.d=collabora.com header.i=@collabora.com + header.a=rsa-sha256 header.s=mail header.b=BxTv7Lfo; + dkim-atps=neutral +Authentication-Results: legolas.ozlabs.org; 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So basically it has the same effect as removing the USB-C plug +for a short moment. If the machine is powered from the USB-C port and +does not have a fallback supply (e.g. a battery), this will result in +a full machine reset due to power loss. + +Ideally we want to avoid triggering a hard reset on these boards. A +non-working USB-C port is probably better than unplanned reboots. But +boards with a backup supply should do the hard reset to get everything +working again. + +In theory it would be enough to check the self_powered property, but +it seems the property might not be configured consistently enough in +system firmwares. + +USB-PD hard resets should happen rarely in general, so let's at least +print an error message before the potential board reset happens. This +is also useful, since it immediately gives away which device triggered +the hard reset. + +Fixes: 1db4c0ac77e3 ("usb: tcpm: add core framework") +Signed-off-by: Sebastian Reichel +--- + drivers/usb/tcpm/tcpm.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c +index 786d92fa4c6f..909fe2ef4fcb 100644 +--- a/drivers/usb/tcpm/tcpm.c ++++ b/drivers/usb/tcpm/tcpm.c +@@ -1711,6 +1711,8 @@ static void run_state_machine(struct udevice *dev) + + /* Hard_Reset states */ + case HARD_RESET_SEND: ++ if (!port->self_powered && port->port_type == TYPEC_PORT_SNK) ++ dev_err(dev, "Initiating hard-reset, which might result in machine power-loss.\n"); + tcpm_pd_transmit(dev, TCPC_TX_HARD_RESET, NULL); + tcpm_set_state(dev, HARD_RESET_START, 0); + port->wait_dr_swap_message = false; + +From patchwork Wed Feb 26 18:44:47 2025 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Sebastian Reichel +X-Patchwork-Id: 2052542 +X-Patchwork-Delegate: marek.vasut@gmail.com +Return-Path: +X-Original-To: incoming@patchwork.ozlabs.org +Delivered-To: patchwork-incoming@legolas.ozlabs.org +Authentication-Results: legolas.ozlabs.org; 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+ Wed, 26 Feb 2025 19:45:07 +0100 (CET) +Received: by jupiter.universe (Postfix, from userid 1000) + id 37B6A480039; Wed, 26 Feb 2025 19:45:07 +0100 (CET) +From: Sebastian Reichel +To: Marek Vasut , u-boot@lists.denx.de, + Jonas Karlman , Soeren Moch +Cc: Tim Harvey , + Philipp Tomsich , + Anand Moon , Maxim Kiselev , + Sebastian Reichel +Subject: [PATCH v2 4/4] usb: tcpm: improve data role mismatch error recovery +Date: Wed, 26 Feb 2025 19:44:47 +0100 +Message-ID: <20250226184506.64114-5-sebastian.reichel@collabora.com> +X-Mailer: git-send-email 2.47.2 +In-Reply-To: <20250226184506.64114-1-sebastian.reichel@collabora.com> +References: <20250226184506.64114-1-sebastian.reichel@collabora.com> +MIME-Version: 1.0 +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +On Radxa ROCK 5B I managed to get U-Boot into an endless loop of +printing + +fusb302 usb-typec@22: TCPM: data role mismatch, initiating error recovery + +messages by changing the data role in Linux and then rebooting the +system. This is happening because the external device (A cheap USB-C hub +powered through a USB-C PD power-supply) kept its state and the error +recovery path for non self-powered devices is not enough to change it. + +Avoid this by swapping our own data role when the error recovery stage +is reached for a port, which is not self-powered. Right now data support +is limited anyways and once proper support is added we can use the data +role swap request to get the desired data direction after the initial +negotiation completed. + +Fixes: 1db4c0ac77e3 ("usb: tcpm: add core framework") +Signed-off-by: Sebastian Reichel +--- + drivers/usb/tcpm/tcpm.c | 30 +++++++++++++++++++++++++++--- + 1 file changed, 27 insertions(+), 3 deletions(-) + +diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c +index 909fe2ef4fcb..12d66d470f9a 100644 +--- a/drivers/usb/tcpm/tcpm.c ++++ b/drivers/usb/tcpm/tcpm.c +@@ -833,6 +833,28 @@ static void tcpm_pd_ctrl_request(struct udevice *dev, + } + } + ++static void tcpm_recover_data_role_mismatch(struct udevice *dev) ++{ ++ struct tcpm_port *port = dev_get_uclass_plat(dev); ++ ++ dev_err(dev, "TCPM: data role mismatch, initiating error recovery\n"); ++ if (port->self_powered) { ++ tcpm_set_state(dev, ERROR_RECOVERY, 0); ++ return; ++ } ++ ++ /* ++ * The error recovery will not help for devices, which are not ++ * self-powered because the error recovery avoids killing the board ++ * power. Since this can happen early on sending ++ * a DR_SWAP request is not sensible. Instead let's change our own ++ * data role. It can be swapped back once USB-PD reached the ready ++ * state. ++ */ ++ tcpm_set_roles(dev, true, port->pwr_role, ++ port->data_role == TYPEC_HOST ? TYPEC_DEVICE : TYPEC_HOST); ++} ++ + static void tcpm_pd_rx_handler(struct udevice *dev, + const struct pd_message *msg) + { +@@ -867,9 +889,11 @@ static void tcpm_pd_rx_handler(struct udevice *dev, + remote_is_host = !!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE); + local_is_host = port->data_role == TYPEC_HOST; + if (remote_is_host == local_is_host) { +- dev_err(dev, "TCPM: data role mismatch, initiating error recovery\n"); +- tcpm_set_state(dev, ERROR_RECOVERY, 0); +- } else { ++ tcpm_recover_data_role_mismatch(dev); ++ local_is_host = port->data_role == TYPEC_HOST; ++ } ++ ++ if (remote_is_host != local_is_host) { + if (cnt) + tcpm_pd_data_request(dev, msg); + else diff --git a/aarch64-boards b/aarch64-boards new file mode 100644 index 0000000..bb4c9fd --- /dev/null +++ b/aarch64-boards @@ -0,0 +1,106 @@ +a64-olinuxino +a64-olinuxino-emmc +amarula_a64_relic +anbernic_rg35xx_h700 +apple_m1 +bananapi_m2_plus_h5 +bananapi_m64 +beelink_gs1 +dragonboard410c +dragonboard820c +eaidk-610-rk3399 +emlid_neutis_n5_devboard +evb-px5 +evb-rk3328 +evb-rk3399 +ficus-rk3399 +firefly-rk3399 +geekbox +hikey +hmibsc +khadas-edge-captain-rk3399 +khadas-edge-rk3399 +khadas-edge-v-rk3399 +khadas-vim +khadas-vim2 +khadas-vim3 +khadas-vim3l +leez-rk3399 +libretech-ac +libretech_all_h3_cc_h5 +libretech_all_h3_it_h5 +libretech_all_h5_cc_h5 +libretech-cc +mvebu_espressobin-88f3720 +mvebu_mcbin-88f8040 +nanopc-t4-rk3399 +nanopi_a64 +nanopi-k2 +nanopi-m4-2gb-rk3399 +nanopi-m4b-rk3399 +nanopi-m4-rk3399 +nanopi_neo2 +nanopi-neo4-rk3399 +nanopi_neo_plus2 +nanopi_r1s_h5 +nanopi-r2c-plus-rk3328 +nanopi-r2c-rk3328 +nanopi-r2s-plus-rk3328 +nanopi-r2s-rk3328 +nanopi-r4s-rk3399 +oceanic_5205_5inmfd +odroid-c2 +orangepi_3 +orangepi_lite2 +orangepi_one_plus +orangepi_pc2 +orangepi_prime +orangepi-r1-plus-lts-rk3328 +orangepi-r1-plus-rk3328 +orangepi-rk3399 +orangepi_win +orangepi_zero2 +orangepi_zero2w +orangepi_zero3 +orangepi_zero_plus +orangepi_zero_plus2 +p212 +p2371-2180 +p2771-0000-500 +p3450-0000 +pine64-lts +pine64_plus +pinebook +pinebook-pro-rk3399 +pine_h64 +pinephone +pinephone-pro-rk3399 +pinetab +poplar +puma-rk3399 +qcm6490 +qcs9100 +qcom +qemu_arm64 +qemu_arm64_lwip +roc-cc-rk3328 +rock-4c-plus-rk3399 +rock-4se-rk3399 +rock64-rk3328 +rock960-rk3399 +rock-pi-4c-rk3399 +rock-pi-4-rk3399 +rock-pi-e-rk3328 +rock-pi-e-v3-rk3328 +rock-pi-n10-rk3399pro +rockpro64-rk3399 +roc-pc-mezzanine-rk3399 +roc-pc-rk3399 +rpi_arm64 +sopine_baseboard +tanix_tx6 +teres_i +transpeed-8k618-t +turris_mox +vexpress_aemv8a_juno +x96_mate diff --git a/disable-VBE-by-default.patch b/disable-VBE-by-default.patch new file mode 100644 index 0000000..1f1b710 --- /dev/null +++ b/disable-VBE-by-default.patch @@ -0,0 +1,32 @@ +From d9e3a49bc2a29922da5bddd95772279f6edba802 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 18 Aug 2023 13:28:05 +0100 +Subject: [PATCH] disable VBE by default + +The VBE protocol needs explicit device support and as +such isn't particularly useful by itself without that, +it also adds size and the potential of an attack vector +so devices that wish to use this protocol should +explicitly opt in to it like all other large features +in U-Boot. + +Signed-off-by: Peter Robinson +--- + boot/Kconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/boot/Kconfig b/boot/Kconfig +index 30eb5b328d7..e8c3fbcb11d 100644 +--- a/boot/Kconfig ++++ b/boot/Kconfig +@@ -635,7 +635,6 @@ config BOOTMETH_QFW + config BOOTMETH_VBE + bool "Bootdev support for Verified Boot for Embedded" + depends on FIT +- default y + select BOOTMETH_GLOBAL + select EVENT + help +-- +2.49.0 + diff --git a/disk-efi-Move-logic-to-get-a-GPT-entry-into-a-helper.patch b/disk-efi-Move-logic-to-get-a-GPT-entry-into-a-helper.patch new file mode 100644 index 0000000..e6e0dc6 --- /dev/null +++ b/disk-efi-Move-logic-to-get-a-GPT-entry-into-a-helper.patch @@ -0,0 +1,127 @@ +From 245be811790aa3eaeb4c7c580c403e9c5ae55bbb Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Thu, 19 Jun 2025 08:40:20 +0200 +Subject: [PATCH v3 1/4] disk: efi: Move logic to get a GPT entry into a helper + function + +Factor out the logic to get the Partition Table Entry (PTE) of a given +partition into a helper function, since it could be used by other code. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_efi.c | 67 +++++++++++++++++++++++++++++-------------------- + 1 file changed, 40 insertions(+), 27 deletions(-) + +diff --git a/disk/part_efi.c b/disk/part_efi.c +index 68ba1d11e7b6..d0b1f96adff2 100644 +--- a/disk/part_efi.c ++++ b/disk/part_efi.c +@@ -215,6 +215,34 @@ int get_disk_guid(struct blk_desc *desc, char *guid) + return 0; + } + ++static int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) ++{ ++ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); ++ gpt_entry *gpt_pte = NULL; ++ ++ /* "part" argument must be at least 1 */ ++ if (part < 1) { ++ log_debug("Invalid Argument(s)\n"); ++ return -EINVAL; ++ } ++ ++ /* This function validates AND fills in the GPT header and PTE */ ++ if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1) ++ return -EINVAL; ++ ++ if (part > le32_to_cpu(gpt_head->num_partition_entries) || ++ !is_pte_valid(&gpt_pte[part - 1])) { ++ log_debug("Invalid partition number %d\n", part); ++ free(gpt_pte); ++ return -EPERM; ++ } ++ ++ memcpy(gpt_e, &gpt_pte[part - 1], sizeof(*gpt_e)); ++ ++ free(gpt_pte); ++ return 0; ++} ++ + static void __maybe_unused part_print_efi(struct blk_desc *desc) + { + ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); +@@ -260,45 +288,32 @@ static void __maybe_unused part_print_efi(struct blk_desc *desc) + static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, + struct disk_partition *info) + { +- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); +- gpt_entry *gpt_pte = NULL; +- +- /* "part" argument must be at least 1 */ +- if (part < 1) { +- log_debug("Invalid Argument(s)\n"); +- return -EINVAL; +- } +- +- /* This function validates AND fills in the GPT header and PTE */ +- if (find_valid_gpt(desc, gpt_head, &gpt_pte) != 1) +- return -EINVAL; ++ gpt_entry gpt_pte = {}; ++ int ret; + +- if (part > le32_to_cpu(gpt_head->num_partition_entries) || +- !is_pte_valid(&gpt_pte[part - 1])) { +- log_debug("Invalid partition number %d\n", part); +- free(gpt_pte); +- return -EPERM; +- } ++ ret = part_get_gpt_pte(desc, part, &gpt_pte); ++ if (ret) ++ return ret; + + /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */ +- info->start = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].starting_lba); ++ info->start = (lbaint_t)le64_to_cpu(gpt_pte.starting_lba); + /* The ending LBA is inclusive, to calculate size, add 1 to it */ +- info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1 ++ info->size = (lbaint_t)le64_to_cpu(gpt_pte.ending_lba) + 1 + - info->start; + info->blksz = desc->blksz; + + snprintf((char *)info->name, sizeof(info->name), "%s", +- print_efiname(&gpt_pte[part - 1])); ++ print_efiname(&gpt_pte)); + strcpy((char *)info->type, "U-Boot"); +- info->bootable = get_bootable(&gpt_pte[part - 1]); +- info->type_flags = gpt_pte[part - 1].attributes.fields.type_guid_specific; ++ info->bootable = get_bootable(&gpt_pte); ++ info->type_flags = gpt_pte.attributes.fields.type_guid_specific; + if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { +- uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, ++ uuid_bin_to_str(gpt_pte.unique_partition_guid.b, + (char *)disk_partition_uuid(info), + UUID_STR_FORMAT_GUID); + } + if (IS_ENABLED(CONFIG_PARTITION_TYPE_GUID)) { +- uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b, ++ uuid_bin_to_str(gpt_pte.partition_type_guid.b, + (char *)disk_partition_type_guid(info), + UUID_STR_FORMAT_GUID); + } +@@ -306,8 +321,6 @@ static int __maybe_unused part_get_info_efi(struct blk_desc *desc, int part, + log_debug("start 0x" LBAF ", size 0x" LBAF ", name %s\n", info->start, + info->size, info->name); + +- /* Remember to free pte */ +- free(gpt_pte); + return 0; + } + +-- +2.49.0 + diff --git a/disk-efi-expose-the-part_get_gpt_pte-helper-function.patch b/disk-efi-expose-the-part_get_gpt_pte-helper-function.patch new file mode 100644 index 0000000..d8b33cf --- /dev/null +++ b/disk-efi-expose-the-part_get_gpt_pte-helper-function.patch @@ -0,0 +1,60 @@ +From 983cdf419137e2611c04a59806de57164e22c34d Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Thu, 19 Jun 2025 08:40:22 +0200 +Subject: [PATCH v3 2/4] disk: efi: expose the part_get_gpt_pte() helper + function + +This function will be used by the EFI application disk support code +to provide data required by the EFI_PARTITION_INFORMATION_PROTOCOL. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +(no changes since v1) + + disk/part_efi.c | 2 +- + include/part.h | 14 ++++++++++++++ + 2 files changed, 15 insertions(+), 1 deletion(-) + +diff --git a/disk/part_efi.c b/disk/part_efi.c +index d0b1f96adff2..fb1ed534f861 100644 +--- a/disk/part_efi.c ++++ b/disk/part_efi.c +@@ -215,7 +215,7 @@ int get_disk_guid(struct blk_desc *desc, char *guid) + return 0; + } + +-static int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) ++int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) + { + ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); + gpt_entry *gpt_pte = NULL; +diff --git a/include/part.h b/include/part.h +index 7075b2cb1164..b3a3362b2af2 100644 +--- a/include/part.h ++++ b/include/part.h +@@ -647,6 +647,20 @@ int gpt_verify_partitions(struct blk_desc *desc, + */ + int get_disk_guid(struct blk_desc *desc, char *guid); + ++/** ++ * part_get_gpt_pte() - Get the GPT partition table entry of a partition ++ * ++ * This function reads the GPT partition table entry (PTE) for a given ++ * block device and partition number. ++ * ++ * @desc: block device descriptor ++ * @part: partition number for which to return the PTE ++ * @gpt_e: GPT partition table entry ++ * ++ * Return: 0 on success, otherwise error ++ */ ++int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e); ++ + #endif + + #if CONFIG_IS_ENABLED(DOS_PARTITION) +-- +2.49.0 + diff --git a/efi_loader-disk-add-EFI_PARTITION_INFO_PROTOCOL-supp.patch b/efi_loader-disk-add-EFI_PARTITION_INFO_PROTOCOL-supp.patch new file mode 100644 index 0000000..e427e85 --- /dev/null +++ b/efi_loader-disk-add-EFI_PARTITION_INFO_PROTOCOL-supp.patch @@ -0,0 +1,152 @@ +From 5aa26c0f082529acce71092dc23d0e17db8805b9 Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Thu, 19 Jun 2025 08:40:26 +0200 +Subject: [PATCH v3 3/4] efi_loader: disk: add EFI_PARTITION_INFO_PROTOCOL + support + +The UEFI 2.10 specification mentions that this protocol shall be installed +along with EFI_BLOCK_IO_PROTOCOL. It provides cached partition information +for MBR and GPT partition types. + +This patch just implements support for GPT partition types. The legacy MBR +partition types is only needed for backward compatibility and can be added +as a follow-up if needed, to make it fully compliant with the EFI spec. + +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +Changes in v3: +- Add ifdef guards for {EFI,DOS}_PARTITION being disabled (Ilias Apalodimas). + + include/part_efi.h | 20 ++++++++++++++++++++ + lib/efi_loader/efi_disk.c | 39 +++++++++++++++++++++++++++++++++++++-- + 2 files changed, 57 insertions(+), 2 deletions(-) + +diff --git a/include/part_efi.h b/include/part_efi.h +index 59b7895b8a23..fb402df6f13e 100644 +--- a/include/part_efi.h ++++ b/include/part_efi.h +@@ -138,4 +138,24 @@ typedef struct _legacy_mbr { + __le16 signature; + } __packed legacy_mbr; + ++#define EFI_PARTITION_INFO_PROTOCOL_GUID \ ++ EFI_GUID(0x8cf2f62c, 0xbc9b, 0x4821, 0x80, \ ++ 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0) ++ ++#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000 ++#define PARTITION_TYPE_OTHER 0x00 ++#define PARTITION_TYPE_MBR 0x01 ++#define PARTITION_TYPE_GPT 0x02 ++ ++struct efi_partition_info { ++ u32 revision; ++ u32 type; ++ u8 system; ++ u8 reserved[7]; ++ union { ++ struct partition mbr; ++ gpt_entry gpt; ++ } info; ++} __packed; ++ + #endif /* _DISK_PART_EFI_H */ +diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c +index 47b583cc5e12..130c4db9606f 100644 +--- a/lib/efi_loader/efi_disk.c ++++ b/lib/efi_loader/efi_disk.c +@@ -26,6 +26,7 @@ struct efi_system_partition efi_system_partition = { + + const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID; + const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID; ++const efi_guid_t efi_partition_info_guid = EFI_PARTITION_INFO_PROTOCOL_GUID; + + /** + * struct efi_disk_obj - EFI disk object +@@ -35,6 +36,7 @@ const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID; + * @media: block I/O media information + * @dp: device path to the block device + * @volume: simple file system protocol of the partition ++ * @info: EFI partition info protocol interface + */ + struct efi_disk_obj { + struct efi_object header; +@@ -42,6 +44,7 @@ struct efi_disk_obj { + struct efi_block_io_media media; + struct efi_device_path *dp; + struct efi_simple_file_system_protocol *volume; ++ struct efi_partition_info info; + }; + + /** +@@ -426,6 +429,7 @@ static efi_status_t efi_disk_add_dev( + /* Fill in object data */ + if (part_info) { + struct efi_device_path *node = efi_dp_part_node(desc, part); ++ struct efi_partition_info *info = &diskobj->info; + struct efi_handler *handler; + void *protocol_interface; + +@@ -454,18 +458,48 @@ static efi_status_t efi_disk_add_dev( + goto error; + } + ++ info->revision = EFI_PARTITION_INFO_PROTOCOL_REVISION; ++ ++ switch (desc->part_type) { ++#if CONFIG_IS_ENABLED(EFI_PARTITION) ++ case PART_TYPE_EFI: ++ info->type = PARTITION_TYPE_GPT; ++ ret = part_get_gpt_pte(desc, part, &info->info.gpt); ++ if (ret) { ++ log_debug("get PTE for part %d failed %ld\n", ++ part, ret); ++ goto error; ++ } ++ break; ++#endif ++#if CONFIG_IS_ENABLED(DOS_PARTITION) ++ case PART_TYPE_DOS: ++ info->type = PARTITION_TYPE_MBR; ++ ++ /* TODO: implement support for MBR partition types */ ++ log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); ++ break; ++#endif ++ default: ++ info->type = PARTITION_TYPE_OTHER; ++ break; ++ } ++ + diskobj->dp = efi_dp_append_node(dp_parent, node); + efi_free_pool(node); + diskobj->media.last_block = part_info->size - 1; +- if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) ++ if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) { + esp_guid = &efi_system_partition_guid; ++ info->system = 1; ++ } ++ + } else { + diskobj->dp = efi_dp_from_part(desc, part); + diskobj->media.last_block = desc->lba - 1; + } + + /* +- * Install the device path and the block IO protocol. ++ * Install the device path, the block IO and partition info protocols. + * + * InstallMultipleProtocolInterfaces() checks if the device path is + * already installed on an other handle and returns EFI_ALREADY_STARTED +@@ -476,6 +510,7 @@ static efi_status_t efi_disk_add_dev( + &handle, + &efi_guid_device_path, diskobj->dp, + &efi_block_io_guid, &diskobj->ops, ++ &efi_partition_info_guid, &diskobj->info, + /* + * esp_guid must be last entry as it + * can be NULL. Its interface is NULL. +-- +2.49.0 + diff --git a/efi_selftest-Add-basic-partition-info-check-to-block.patch b/efi_selftest-Add-basic-partition-info-check-to-block.patch new file mode 100644 index 0000000..814a841 --- /dev/null +++ b/efi_selftest-Add-basic-partition-info-check-to-block.patch @@ -0,0 +1,95 @@ +From 4970fb56c645346c0ef1e2b5cb73e1ad5dec6378 Mon Sep 17 00:00:00 2001 +From: Javier Martinez Canillas +Date: Thu, 19 Jun 2025 08:40:28 +0200 +Subject: [PATCH v3 4/4] efi_selftest: Add basic partition info check to block + io test + +Test the EFI_PARTITION_INFO_PROTOCOL in the existing EFI_BLOCK_IO_PROTOCOL +unit test. It is fairly basic, since it only checks that the values of the +struct efi_partition_info .revision, .type and .system fields are correct. + +It doesn't check the MBR partition record information, because that's not +supported by the EFI_PARTITION_INFO_PROTOCOL implementation yet. The test +can be extended once the support is implemented, or if the in-memory disk +image used for the test is modified to have a GPT partition type instead. + +Suggested-by: Tom Rini +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Ilias Apalodimas +--- + +Changes in v3: +- Fix build in -next due missing part_efi.h header include (Ilias Apalodimas). +- Rebase on top of -next (Ilias Apalodimas). + +Changes in v2: +- Add a test for the EFI partition information protocol (Tom Rini). + + lib/efi_selftest/efi_selftest_block_device.c | 30 ++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/lib/efi_selftest/efi_selftest_block_device.c b/lib/efi_selftest/efi_selftest_block_device.c +index a367e8b89d17..f145e58a267a 100644 +--- a/lib/efi_selftest/efi_selftest_block_device.c ++++ b/lib/efi_selftest/efi_selftest_block_device.c +@@ -18,6 +18,7 @@ + #include + #include "efi_selftest_disk_image.h" + #include ++#include + + /* Block size of compressed disk image */ + #define COMPRESSED_DISK_IMAGE_BLOCK_SIZE 8 +@@ -29,6 +30,7 @@ static struct efi_boot_services *boottime; + + static const efi_guid_t block_io_protocol_guid = EFI_BLOCK_IO_PROTOCOL_GUID; + static const efi_guid_t guid_device_path = EFI_DEVICE_PATH_PROTOCOL_GUID; ++static const efi_guid_t partition_info_guid = EFI_PARTITION_INFO_PROTOCOL_GUID; + static const efi_guid_t guid_simple_file_system_protocol = + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; + static const efi_guid_t guid_file_system_info = EFI_FILE_SYSTEM_INFO_GUID; +@@ -310,6 +312,7 @@ static int execute(void) + struct efi_file_system_info info; + u16 label[12]; + } system_info; ++ struct efi_partition_info *part_info; + efi_uintn_t buf_size; + char buf[16] __aligned(ARCH_DMA_MINALIGN); + u32 part1_size; +@@ -375,6 +378,33 @@ static int execute(void) + part1_size - 1); + return EFI_ST_FAILURE; + } ++ ++ /* Open the partition information protocol */ ++ ret = boottime->open_protocol(handle_partition, ++ &partition_info_guid, ++ (void **)&part_info, NULL, NULL, ++ EFI_OPEN_PROTOCOL_GET_PROTOCOL); ++ if (ret != EFI_SUCCESS) { ++ efi_st_error("Failed to open partition information protocol\n"); ++ return EFI_ST_FAILURE; ++ } ++ /* Check that cached partition information is the expected */ ++ if (part_info->revision != EFI_PARTITION_INFO_PROTOCOL_REVISION) { ++ efi_st_error("Partition info revision %x, expected %x\n", ++ part_info->revision, EFI_PARTITION_INFO_PROTOCOL_REVISION); ++ return EFI_ST_FAILURE; ++ } ++ if (part_info->type != PARTITION_TYPE_MBR) { ++ efi_st_error("Partition info type %x, expected %x\n", ++ part_info->type, PARTITION_TYPE_MBR); ++ return EFI_ST_FAILURE; ++ } ++ if (part_info->system != 0) { ++ efi_st_error("Partition info system %x, expected 0\n", ++ part_info->system); ++ return EFI_ST_FAILURE; ++ } ++ + /* Open the simple file system protocol */ + ret = boottime->open_protocol(handle_partition, + &guid_simple_file_system_protocol, +-- +2.49.0 + diff --git a/enable-bootmenu-by-default.patch b/enable-bootmenu-by-default.patch new file mode 100644 index 0000000..1ecd514 --- /dev/null +++ b/enable-bootmenu-by-default.patch @@ -0,0 +1,49 @@ +From a956480a6d52ae90ef4a46275c2ee29a4074de36 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Fri, 18 Aug 2023 23:10:42 +0100 +Subject: [PATCH] enable bootmenu by default + +We want the boot menu on all Fedora devices as it makes +it a whole lot more user friendly. + +Signed-off-by: Peter Robinson +--- + boot/Kconfig | 2 ++ + cmd/Kconfig | 1 + + 2 files changed, 3 insertions(+) + +diff --git a/boot/Kconfig b/boot/Kconfig +index 467b09e2350..ad67b1f65a6 100644 +--- a/boot/Kconfig ++++ b/boot/Kconfig +@@ -1281,6 +1281,7 @@ config BOOTDELAY + + config AUTOBOOT_KEYED + bool "Stop autobooting via specific input key / string" ++ default y + help + This option enables stopping (aborting) of the automatic + boot feature only by issuing a specific input key or +@@ -1433,6 +1434,7 @@ config AUTOBOOT_MENUKEY + + config AUTOBOOT_MENU_SHOW + bool "Show a menu on boot" ++ default y + depends on CMD_BOOTMENU + help + This enables the boot menu, controlled by environment variables +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 43ca10f69cc..3d39f2914cc 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -413,6 +413,7 @@ source lib/efi_selftest/Kconfig + + config CMD_BOOTMENU + bool "bootmenu" ++ default y + select MENU + select CHARSET + help +-- +2.41.0 + diff --git a/improve-riscv64-configs.patch b/improve-riscv64-configs.patch new file mode 100644 index 0000000..811824e --- /dev/null +++ b/improve-riscv64-configs.patch @@ -0,0 +1,116 @@ +diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig +index 6b2fed4a..541c4211 100644 +--- a/configs/qemu-riscv64_defconfig ++++ b/configs/qemu-riscv64_defconfig +@@ -22,3 +22,12 @@ CONFIG_FLASH_SHOW_PROGRESS=0 + CONFIG_SYS_MAX_FLASH_BANKS=2 + CONFIG_UTHREAD=y + CONFIG_UNIT_TEST=y ++CONFIG_NR_CPUS=32 ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;" ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y ++CONFIG_FS_BTRFS=y +diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig +index 95f24ac3..470a0187 100644 +--- a/configs/qemu-riscv64_smode_defconfig ++++ b/configs/qemu-riscv64_smode_defconfig +@@ -25,3 +25,8 @@ CONFIG_FLASH_SHOW_PROGRESS=0 + CONFIG_SYS_MAX_FLASH_BANKS=2 + CONFIG_UTHREAD=y + CONFIG_UNIT_TEST=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig +index d2b0aec8..f694ab50 100644 +--- a/configs/qemu-riscv64_spl_defconfig ++++ b/configs/qemu-riscv64_spl_defconfig +@@ -25,3 +25,6 @@ CONFIG_FLASH_SHOW_PROGRESS=0 + CONFIG_SYS_MAX_FLASH_BANKS=2 + # CONFIG_BINMAN_FDT is not set + CONFIG_UNIT_TEST=y ++CONFIG_NR_CPUS=32 ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="cp.l ${fdtcontroladdr} ${fdt_addr_r} 0x20000;" +diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig +index b1c4d00c..7efe9b83 100644 +--- a/configs/sifive_unleashed_defconfig ++++ b/configs/sifive_unleashed_defconfig +@@ -41,3 +41,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_SPL_DM_SEQ_ALIAS=y + CONFIG_SPL_CLK=y + CONFIG_DM_MTD=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y +diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig +index f70e3db4..26fca59d 100644 +--- a/configs/sifive_unmatched_defconfig ++++ b/configs/sifive_unmatched_defconfig +@@ -27,7 +27,7 @@ CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 + CONFIG_BOOTSTD_DEFAULTS=y + CONFIG_USE_PREBOOT=y +-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};nvme scan" ++CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt addr ${fdtcontroladdr};" + CONFIG_DEFAULT_FDT_FILE="sifive/hifive-unmatched-a00.dtb" + CONFIG_SYS_CBSIZE=256 + CONFIG_SYS_PBSIZE=276 +@@ -66,3 +66,9 @@ CONFIG_SCSI=y + CONFIG_USB=y + CONFIG_USB_XHCI_HCD=y + CONFIG_USB_XHCI_PCI=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y ++CONFIG_FS_BTRFS=y +diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig +index e145ced8..d69b2e8c 100644 +--- a/configs/starfive_visionfive2_defconfig ++++ b/configs/starfive_visionfive2_defconfig +@@ -154,3 +154,21 @@ CONFIG_USB_GADGET=y + # CONFIG_WATCHDOG_AUTOSTART is not set + CONFIG_WDT=y + CONFIG_WDT_STARFIVE=y ++CONFIG_CMD_SBI=y ++CONFIG_SYSRESET_SBI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_SYSRESET_CMD_POWEROFF=y ++CONFIG_CMD_BTRFS=y ++CONFIG_FS_BTRFS=y ++CONFIG_CMD_EXT4_WRITE=y ++CONFIG_FAT_WRITE=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_LSBLK=y ++CONFIG_CMD_WRITE=y ++CONFIG_CMD_CAT=y ++CONFIG_CMD_XXD=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_WGET=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_EFIDEBUG=y +diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h +index cf4fcb90..63078ee4 100644 +--- a/include/configs/qemu-riscv.h ++++ b/include/configs/qemu-riscv.h +@@ -32,8 +32,6 @@ + + #define CFG_EXTRA_ENV_SETTINGS \ + CFG_STD_DEVICES_SETTINGS \ +- "fdt_high=0xffffffffffffffff\0" \ +- "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x84000000\0" \ + "kernel_comp_addr_r=0x88000000\0" \ + "kernel_comp_size=0x4000000\0" \ diff --git a/p3450-fix-board.patch b/p3450-fix-board.patch new file mode 100644 index 0000000..a4bce81 --- /dev/null +++ b/p3450-fix-board.patch @@ -0,0 +1,139 @@ +From 00937cdf45286364c2acd7250f0900cb2c3dae86 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 8 Jul 2025 21:48:22 +0100 +Subject: [PATCH] p3450: reduce size of Jetson Nano u-boot.bin + +The Jetson Nano contains all it's firmware on a 4Mb SPI +flash, the allocated size in that flash for U-Boot is +753664 bytes so we need to ensure the u-boot.bin doesn't +exceed that else it will fail. + +Add a BOARD_SIZE_LIMIT and drop a few large, and somewhat +esoteric, options to bring us back under that limit. + +Signed-off-by: Peter Robinson +--- + configs/p3450-0000_defconfig | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig +index a002178b7fb..518ed6b37a2 100644 +--- a/configs/p3450-0000_defconfig ++++ b/configs/p3450-0000_defconfig +@@ -14,6 +14,8 @@ CONFIG_ENV_SECT_SIZE=0x1000 + CONFIG_DEFAULT_DEVICE_TREE="tegra210-p3450-0000" + CONFIG_SYS_BOOTM_LEN=0x800000 + CONFIG_SYS_LOAD_ADDR=0x80080000 ++CONFIG_HAS_BOARD_SIZE_LIMIT=y ++CONFIG_BOARD_SIZE_LIMIT=753664 + CONFIG_TEGRA210=y + CONFIG_TARGET_P3450_0000=y + CONFIG_TEGRA_GPU=y +@@ -24,8 +26,14 @@ CONFIG_SYS_PBSIZE=2089 + CONFIG_CONSOLE_MUX=y + CONFIG_SYS_STDIO_DEREGISTER=y + CONFIG_SYS_PROMPT="Tegra210 (P3450-0000) # " ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_BOOTM_PLAN9 is not set + # CONFIG_CMD_IMI is not set ++# CONFIG_CRC32_VERIFY is not set + CONFIG_CMD_DFU=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_GO is not set + CONFIG_CMD_GPIO=y + CONFIG_CMD_I2C=y + CONFIG_CMD_MMC=y +-- +2.50.0 +From 60287cee71a5748d0036c356d16b85938f5bf9c8 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 9 Jul 2025 22:06:06 +0100 +Subject: [PATCH] p3450: fix Jetson Nano SPI flash + +The Nano's SPI flash stopped working in U-Boot, as the +prior stage loaded U-Boot, the only thing it was used +for was save/loading env vars so update the DT so it +can now initialise it. It also drops enabling the old +TEGRA114_SPI driver, as the flash hangs off the faster +TEGRA210_QSPI interface, nothing on the Nano uses the +old interface by default so it's surplus. + +Signed-off-by: Peter Robinson +--- + arch/arm/dts/tegra210-p3450-0000.dts | 9 ++++++++- + arch/arm/dts/tegra210.dtsi | 6 +++--- + configs/p3450-0000_defconfig | 1 - + include/dt-bindings/clock/tegra210-car.h | 6 +++--- + 4 files changed, 14 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts +index 9ef744ac8b0..ddeeb232de2 100644 +--- a/arch/arm/dts/tegra210-p3450-0000.dts ++++ b/arch/arm/dts/tegra210-p3450-0000.dts +@@ -124,7 +124,14 @@ + + spi@70410000 { + status = "okay"; +- spi-max-frequency = <80000000>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <104000000>; ++ spi-tx-bus-width = <2>; ++ spi-rx-bus-width = <2>; ++ }; + }; + + usb@7d000000 { +diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi +index 28ecd2b467a..6dd8fe26c38 100644 +--- a/arch/arm/dts/tegra210.dtsi ++++ b/arch/arm/dts/tegra210.dtsi +@@ -762,10 +762,10 @@ + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; +- clocks = <&tegra_car TEGRA210_CLK_QSPI>; +- clock-names = "qspi"; ++ clocks = <&tegra_car TEGRA210_CLK_QSPI>, ++ <&tegra_car TEGRA210_CLK_QSPI_PM>; ++ clock-names = "qspi", "qspi_out"; + resets = <&tegra_car 211>; +- reset-names = "qspi"; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + status = "disabled"; +diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig +index 518ed6b37a2..3b4b863100f 100644 +--- a/configs/p3450-0000_defconfig ++++ b/configs/p3450-0000_defconfig +@@ -61,7 +61,6 @@ CONFIG_RTL8169=y + CONFIG_NVME_PCI=y + CONFIG_PCI_TEGRA=y + CONFIG_SYS_NS16550=y +-CONFIG_TEGRA114_SPI=y + CONFIG_TEGRA210_QSPI=y + CONFIG_USB=y + CONFIG_USB_EHCI_HCD=y +diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h +index eddac16800d..50d19647fb9 100644 +--- a/include/dt-bindings/clock/tegra210-car.h ++++ b/include/dt-bindings/clock/tegra210-car.h +@@ -302,9 +302,9 @@ + #define TEGRA210_CLK_AUDIO3 274 + #define TEGRA210_CLK_AUDIO4 275 + #define TEGRA210_CLK_SPDIF 276 +-#define TEGRA210_CLK_CLK_OUT_1 277 +-#define TEGRA210_CLK_CLK_OUT_2 278 +-#define TEGRA210_CLK_CLK_OUT_3 279 ++/* 277 */ ++#define TEGRA210_CLK_QSPI_PM 278 ++/* 279 */ + #define TEGRA210_CLK_BLINK 280 + /* 281 */ + /* 282 */ +-- +2.50.0 + diff --git a/riscv64-boards b/riscv64-boards new file mode 100644 index 0000000..f96e775 --- /dev/null +++ b/riscv64-boards @@ -0,0 +1,4 @@ +qemu-riscv64_spl +sifive_unleashed +sifive_unmatched +starfive_visionfive2 diff --git a/rockchip-Enable-preboot-start-for-pci-usb.patch b/rockchip-Enable-preboot-start-for-pci-usb.patch new file mode 100644 index 0000000..177b44c --- /dev/null +++ b/rockchip-Enable-preboot-start-for-pci-usb.patch @@ -0,0 +1,783 @@ +From 020f67a37342b091c74dab93a133253401d4d899 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 31 Dec 2024 14:15:41 +0000 +Subject: [PATCH] rockchip: Enable preboot start for pci/usb + +Enable the preboot so nvme works OOTB + +Signed-off-by: Peter Robinson +--- + configs/anbernic-rgxx3-rk3566_defconfig | 2 ++ + configs/bpi-r2-pro-rk3568_defconfig | 2 ++ + configs/cm3588-nas-rk3588_defconfig | 2 ++ + configs/coolpi-4b-rk3588s_defconfig | 2 ++ + configs/coolpi-cm5-evb-rk3588_defconfig | 2 ++ + configs/evb-rk3568_defconfig | 2 ++ + configs/evb-rk3588_defconfig | 2 ++ + configs/firefly-rk3399_defconfig | 2 ++ + configs/generic-rk3568_defconfig | 2 ++ + configs/generic-rk3588_defconfig | 2 ++ + configs/jaguar-rk3588_defconfig | 2 ++ + configs/lubancat-2-rk3568_defconfig | 2 ++ + configs/nanopc-t4-rk3399_defconfig | 2 ++ + configs/nanopc-t6-rk3588_defconfig | 2 ++ + configs/nanopi-r5c-rk3568_defconfig | 2 ++ + configs/nanopi-r5s-rk3568_defconfig | 2 ++ + configs/nanopi-r6c-rk3588s_defconfig | 2 ++ + configs/nanopi-r6s-rk3588s_defconfig | 2 ++ + configs/neu6a-io-rk3588_defconfig | 2 ++ + configs/neu6b-io-rk3588_defconfig | 2 ++ + configs/nova-rk3588s_defconfig | 2 ++ + configs/odroid-m1-rk3568_defconfig | 2 ++ + configs/orangepi-3b-rk3566_defconfig | 2 ++ + configs/orangepi-5-plus-rk3588_defconfig | 2 ++ + configs/orangepi-5-rk3588s_defconfig | 2 ++ + configs/pinebook-pro-rk3399_defconfig | 1 + + configs/pinetab2-rk3566_defconfig | 2 ++ + configs/powkiddy-x55-rk3566_defconfig | 2 ++ + configs/quartz64-a-rk3566_defconfig | 2 ++ + configs/quartz64-b-rk3566_defconfig | 2 ++ + configs/quartzpro64-rk3588_defconfig | 2 ++ + configs/radxa-cm3-io-rk3566_defconfig | 2 ++ + configs/radxa-e25-rk3568_defconfig | 2 ++ + configs/radxa-zero-3-rk3566_defconfig | 2 ++ + configs/roc-pc-mezzanine-rk3399_defconfig | 2 ++ + configs/rock-3a-rk3568_defconfig | 2 ++ + configs/rock-3b-rk3568_defconfig | 2 ++ + configs/rock-3c-rk3566_defconfig | 2 ++ + configs/rock-4c-plus-rk3399_defconfig | 2 ++ + configs/rock-4se-rk3399_defconfig | 2 ++ + configs/rock-5-itx-rk3588_defconfig | 2 ++ + configs/rock-pi-4-rk3399_defconfig | 2 ++ + configs/rock-pi-4c-rk3399_defconfig | 2 ++ + configs/rock-pi-n10-rk3399pro_defconfig | 2 ++ + configs/rock5a-rk3588s_defconfig | 2 ++ + configs/rock5b-rk3588_defconfig | 2 ++ + configs/rock960-rk3399_defconfig | 2 ++ + configs/rockpro64-rk3399_defconfig | 2 ++ + configs/sige7-rk3588_defconfig | 2 ++ + configs/soquartz-blade-rk3566_defconfig | 2 ++ + configs/soquartz-cm4-rk3566_defconfig | 2 ++ + configs/soquartz-model-a-rk3566_defconfig | 2 ++ + configs/tiger-rk3588_defconfig | 2 ++ + configs/toybrick-rk3588_defconfig | 2 ++ + configs/turing-rk1-rk3588_defconfig | 2 ++ + 55 files changed, 109 insertions(+) + +diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig +index 14c97b4c5bf..de92e1b4141 100644 +--- a/configs/anbernic-rgxx3-rk3566_defconfig ++++ b/configs/anbernic-rgxx3-rk3566_defconfig +@@ -12,6 +12,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + # CONFIG_EFI_LOADER is not set + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig +index d84ea2f955f..de777817c37 100644 +--- a/configs/bpi-r2-pro-rk3568_defconfig ++++ b/configs/bpi-r2-pro-rk3568_defconfig +@@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig +index fd0a32d6d79..e561be511d4 100644 +--- a/configs/cm3588-nas-rk3588_defconfig ++++ b/configs/cm3588-nas-rk3588_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig +index ea985b81670..96d7cffb075 100644 +--- a/configs/coolpi-4b-rk3588s_defconfig ++++ b/configs/coolpi-4b-rk3588s_defconfig +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig +index 58ffe7baf5f..5eadc091242 100644 +--- a/configs/coolpi-cm5-evb-rk3588_defconfig ++++ b/configs/coolpi-cm5-evb-rk3588_defconfig +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig +index a068bc6846c..8c94f7b21bc 100644 +--- a/configs/evb-rk3568_defconfig ++++ b/configs/evb-rk3568_defconfig +@@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig +index 3d4d2747145..051015fd811 100644 +--- a/configs/evb-rk3588_defconfig ++++ b/configs/evb-rk3588_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig +index 3871627318b..b96aadc78eb 100644 +--- a/configs/firefly-rk3399_defconfig ++++ b/configs/firefly-rk3399_defconfig +@@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_MAX_SIZE=0x40000 +diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig +index f79f0e84400..ba5339a004f 100644 +--- a/configs/generic-rk3568_defconfig ++++ b/configs/generic-rk3568_defconfig +@@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig +index 51e31dce3a9..1c767caa06a 100644 +--- a/configs/generic-rk3588_defconfig ++++ b/configs/generic-rk3588_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig +index 6e853991d1d..a5a56a33d09 100644 +--- a/configs/jaguar-rk3588_defconfig ++++ b/configs/jaguar-rk3588_defconfig +@@ -16,6 +16,8 @@ CONFIG_DEBUG_UART_BASE=0xfeb50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig +index 46cc3c03fff..8915d5bfba9 100644 +--- a/configs/lubancat-2-rk3568_defconfig ++++ b/configs/lubancat-2-rk3568_defconfig +@@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_EFI_VAR_BUF_SIZE=16384 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig +index 26c12c51078..33f7e838c2c 100644 +--- a/configs/nanopc-t4-rk3399_defconfig ++++ b/configs/nanopc-t4-rk3399_defconfig +@@ -14,6 +14,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_MAX_SIZE=0x40000 +diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig +index 772b7df1555..ba6cf48308c 100644 +--- a/configs/nanopc-t6-rk3588_defconfig ++++ b/configs/nanopc-t6-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig +index 4a43b17ccb1..91c95b491d5 100644 +--- a/configs/nanopi-r5c-rk3568_defconfig ++++ b/configs/nanopi-r5c-rk3568_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig +index a60d229fbbf..355d8114a9b 100644 +--- a/configs/nanopi-r5s-rk3568_defconfig ++++ b/configs/nanopi-r5s-rk3568_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/nanopi-r6c-rk3588s_defconfig b/configs/nanopi-r6c-rk3588s_defconfig +index c4de5518a72..92697c536d9 100644 +--- a/configs/nanopi-r6c-rk3588s_defconfig ++++ b/configs/nanopi-r6c-rk3588s_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig +index 2726729b9ac..63a3690db8e 100644 +--- a/configs/nanopi-r6s-rk3588s_defconfig ++++ b/configs/nanopi-r6s-rk3588s_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig +index 291e0d26d42..e385aba7bc4 100644 +--- a/configs/neu6a-io-rk3588_defconfig ++++ b/configs/neu6a-io-rk3588_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig +index 4e22852f23c..79f4e66cb9b 100644 +--- a/configs/neu6b-io-rk3588_defconfig ++++ b/configs/neu6b-io-rk3588_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig +index fb30dfd1db8..e99898355e1 100644 +--- a/configs/nova-rk3588s_defconfig ++++ b/configs/nova-rk3588s_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig +index a8e8a8781e1..a3ea2e592b9 100644 +--- a/configs/odroid-m1-rk3568_defconfig ++++ b/configs/odroid-m1-rk3568_defconfig +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig +index 2181c9caf58..fee0c719f25 100644 +--- a/configs/orangepi-3b-rk3566_defconfig ++++ b/configs/orangepi-3b-rk3566_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig +index 9050fceda45..2e1fe2c6dc5 100644 +--- a/configs/orangepi-5-plus-rk3588_defconfig ++++ b/configs/orangepi-5-plus-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig +index 6e2ff7d338a..7ec7d13e1f9 100644 +--- a/configs/orangepi-5-rk3588s_defconfig ++++ b/configs/orangepi-5-rk3588s_defconfig +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig +index dfa927ccb17..acc2a0a9fcd 100644 +--- a/configs/pinebook-pro-rk3399_defconfig ++++ b/configs/pinebook-pro-rk3399_defconfig +@@ -22,6 +22,7 @@ CONFIG_PCI=y + CONFIG_DEBUG_UART=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_MAX_SIZE=0x40000 +diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig +index 45e63b42d19..3ef0ddbbe31 100644 +--- a/configs/pinetab2-rk3566_defconfig ++++ b/configs/pinetab2-rk3566_defconfig +@@ -18,6 +18,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/powkiddy-x55-rk3566_defconfig b/configs/powkiddy-x55-rk3566_defconfig +index 85280839889..f93a463087b 100644 +--- a/configs/powkiddy-x55-rk3566_defconfig ++++ b/configs/powkiddy-x55-rk3566_defconfig +@@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig +index fe3fa37611a..60b1f8f1784 100644 +--- a/configs/quartz64-a-rk3566_defconfig ++++ b/configs/quartz64-a-rk3566_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig +index 929736f76af..c3155d9b835 100644 +--- a/configs/quartz64-b-rk3566_defconfig ++++ b/configs/quartz64-b-rk3566_defconfig +@@ -17,6 +17,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig +index ade7be27e92..263d21bee8b 100644 +--- a/configs/quartzpro64-rk3588_defconfig ++++ b/configs/quartzpro64-rk3588_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig +index 2655fdc3170..c1a27f6e310 100644 +--- a/configs/radxa-cm3-io-rk3566_defconfig ++++ b/configs/radxa-cm3-io-rk3566_defconfig +@@ -9,6 +9,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig +index 4df594ddc01..3830d27b264 100644 +--- a/configs/radxa-e25-rk3568_defconfig ++++ b/configs/radxa-e25-rk3568_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig +index 5989b07ad79..1b571ec3847 100644 +--- a/configs/radxa-zero-3-rk3566_defconfig ++++ b/configs/radxa-zero-3-rk3566_defconfig +@@ -11,6 +11,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig +index 3ab5fd69c62..ba254d8f6c0 100644 +--- a/configs/roc-pc-mezzanine-rk3399_defconfig ++++ b/configs/roc-pc-mezzanine-rk3399_defconfig +@@ -21,6 +21,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig +index 733ce631457..3387796a0c5 100644 +--- a/configs/rock-3a-rk3568_defconfig ++++ b/configs/rock-3a-rk3568_defconfig +@@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig +index 2023feb36c2..84c6aab6b33 100644 +--- a/configs/rock-3b-rk3568_defconfig ++++ b/configs/rock-3b-rk3568_defconfig +@@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig +index 2528c7c639c..0a0010b1268 100644 +--- a/configs/rock-3c-rk3566_defconfig ++++ b/configs/rock-3c-rk3566_defconfig +@@ -16,6 +16,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig +index 0c73a212ea1..2ae2eff39e2 100644 +--- a/configs/rock-4c-plus-rk3399_defconfig ++++ b/configs/rock-4c-plus-rk3399_defconfig +@@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_EFI_CAPSULE_ON_DISK=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y + # CONFIG_ANDROID_BOOT_IMAGE is not set +diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig +index 3ae19692155..12621b8a41b 100644 +--- a/configs/rock-4se-rk3399_defconfig ++++ b/configs/rock-4se-rk3399_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_EFI_CAPSULE_ON_DISK=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig +index d0dd1c20ece..b3a778907c8 100644 +--- a/configs/rock-5-itx-rk3588_defconfig ++++ b/configs/rock-5-itx-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig +index f3a5c2c45f3..d95576e804a 100644 +--- a/configs/rock-pi-4-rk3399_defconfig ++++ b/configs/rock-pi-4-rk3399_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_EFI_CAPSULE_ON_DISK=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig +index 9bda50c8c77..d26eb3dcb44 100644 +--- a/configs/rock-pi-4c-rk3399_defconfig ++++ b/configs/rock-pi-4c-rk3399_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_EFI_CAPSULE_ON_DISK=y + CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig +index a9c6d8a907a..1cde3859eef 100644 +--- a/configs/rock-pi-n10-rk3399pro_defconfig ++++ b/configs/rock-pi-n10-rk3399pro_defconfig +@@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + # CONFIG_ANDROID_BOOT_IMAGE is not set + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb" + # CONFIG_CONSOLE_MUX is not set +diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig +index 9618d590009..9608f7e7e4c 100644 +--- a/configs/rock5a-rk3588s_defconfig ++++ b/configs/rock5a-rk3588s_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig +index 47ee2109f8e..e1c6961a3ab 100644 +--- a/configs/rock5b-rk3588_defconfig ++++ b/configs/rock5b-rk3588_defconfig +@@ -18,6 +18,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig +index aebfa73459c..8b60ad3bf00 100644 +--- a/configs/rock960-rk3399_defconfig ++++ b/configs/rock960-rk3399_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFF1A0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb" + CONFIG_SYS_PBSIZE=1052 + CONFIG_DISPLAY_BOARDINFO_LATE=y +diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig +index 08b7e2784e9..d80e120c66f 100644 +--- a/configs/rockpro64-rk3399_defconfig ++++ b/configs/rockpro64-rk3399_defconfig +@@ -20,6 +20,8 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" + CONFIG_DISPLAY_BOARDINFO_LATE=y + CONFIG_SPL_MAX_SIZE=0x40000 +diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig +index 8b033e22b84..978df10442c 100644 +--- a/configs/sige7-rk3588_defconfig ++++ b/configs/sige7-rk3588_defconfig +@@ -13,6 +13,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_SPL_SPI=y + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig +index a1a51b2c657..4083f217c0b 100644 +--- a/configs/soquartz-blade-rk3566_defconfig ++++ b/configs/soquartz-blade-rk3566_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig +index a8bca0eaccc..c3dd48d9dc1 100644 +--- a/configs/soquartz-cm4-rk3566_defconfig ++++ b/configs/soquartz-cm4-rk3566_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig +index f080d2e36d2..f6f2f67b0a6 100644 +--- a/configs/soquartz-model-a-rk3566_defconfig ++++ b/configs/soquartz-model-a-rk3566_defconfig +@@ -11,6 +11,8 @@ CONFIG_DEBUG_UART_BASE=0xFE660000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig +index f962ac416f3..1fc7301f6ae 100644 +--- a/configs/tiger-rk3588_defconfig ++++ b/configs/tiger-rk3588_defconfig +@@ -17,6 +17,8 @@ CONFIG_DEBUG_UART_CLOCK=24000000 + # CONFIG_DEBUG_UART_BOARD_INIT is not set + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig +index 5e70341c987..fd7e842f9e5 100644 +--- a/configs/toybrick-rk3588_defconfig ++++ b/configs/toybrick-rk3588_defconfig +@@ -10,6 +10,8 @@ CONFIG_SYS_LOAD_ADDR=0xc00800 + CONFIG_DEBUG_UART_BASE=0xFEB50000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y + CONFIG_SPL_FIT_SIGNATURE=y +diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig +index 0eddf15833c..1a9aacc7b5d 100644 +--- a/configs/turing-rk1-rk3588_defconfig ++++ b/configs/turing-rk1-rk3588_defconfig +@@ -12,6 +12,8 @@ CONFIG_DEBUG_UART_BASE=0xFEBC0000 + CONFIG_DEBUG_UART_CLOCK=24000000 + CONFIG_PCI=y + CONFIG_DEBUG_UART=y ++CONFIG_USE_PREBOOT=y ++CONFIG_PREBOOT="pci enum; usb start; nvme scan;" + CONFIG_AHCI=y + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y +-- +2.47.1 + diff --git a/sources b/sources new file mode 100644 index 0000000..88fc3b3 --- /dev/null +++ b/sources @@ -0,0 +1 @@ +SHA512 (u-boot-2025.07.tar.bz2) = 0d9a4906aaee134c6b6c496aaf7f54c653ede8e878f851e877ec7876e26cd14e356cd29112849295deeb72bee6b4d292151fb4d9db23d23608350c3fe567d955 diff --git a/tools-termios_linux.h-Fix-build-error-on-ppc64.patch b/tools-termios_linux.h-Fix-build-error-on-ppc64.patch new file mode 100644 index 0000000..80327ac --- /dev/null +++ b/tools-termios_linux.h-Fix-build-error-on-ppc64.patch @@ -0,0 +1,198 @@ +From patchwork Fri Jun 27 13:53:37 2025 +Content-Type: text/plain; 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[62.151.111.63]) + by smtp.gmail.com with ESMTPSA id + 5b1f17b1804b1-4538a3a6716sm51645685e9.11.2025.06.27.06.54.10 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Fri, 27 Jun 2025 06:54:10 -0700 (PDT) +From: Javier Martinez Canillas +To: u-boot@lists.denx.de +Cc: =?utf-8?q?Dan_Hor=C3=A1k?= , + Peter Robinson , + Javier Martinez Canillas , + =?utf-8?q?Marek_Beh=C3=BAn?= , Stefan Roese , + This contributor prefers not to receive mails , + Tom Rini +Subject: [RFC PATCH] tools: termios_linux.h: Fix build error on ppc64 +Date: Fri, 27 Jun 2025 15:53:37 +0200 +Message-ID: <20250627135355.2731430-1-javierm@redhat.com> +X-Mailer: git-send-email 2.49.0 +MIME-Version: 1.0 +X-Mimecast-Spam-Score: 0 +X-Mimecast-MFC-PROC-ID: z65za21YYzkwgA1f4karVpsKGGndOCroafvzzrKiAYY_1751032453 +X-Mimecast-Originator: redhat.com +X-BeenThere: u-boot@lists.denx.de +X-Mailman-Version: 2.1.39 +Precedence: list +List-Id: U-Boot discussion +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Errors-To: u-boot-bounces@lists.denx.de +Sender: "U-Boot" +X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de +X-Virus-Status: Clean + +Commit 93b55636b09f ("tools: kwboot: Allow any baudrate on Linux") added a +tcgetattr() function to be used, instead of the libc's termios functions. + +This was done to allow using the raw TCGETS2/TCSETS2 ioctls that allow to +support arbitrary baud rates. + +This breaks the build for PowerPC, because that architecture does not have +a struct termios2 defined becuase the termios and ktermios are the same. + +On PowerPC, the termios ioctl() emulates the TCGETS2/TCSETS*2 ioctls with +tcgetattr/tcsetattr using just the struct termios (that's as mentioned the +same than what is defined as struct termios2 in other architectures). + +So there is no need to use the TCGETS2/TCSETS2 ioctls on that architecture +and just TCGETS/TCSETS ioctls with termios as defined by PowerPC is enough. + +Fixes: 93b55636b09f ("tools: kwboot: Allow any baudrate on Linux") +Signed-off-by: Javier Martinez Canillas +Reviewed-by: Tom Rini +--- +The patch fixes a build error found on Fedora rawhide with latest glibc: + +https://bugzilla.redhat.com/show_bug.cgi?id=2375150 + +It is an RFC because I'm not familiar with this part of the code nor the +PowerPC architecture. But this patch fixes the mentioned compile issue. + + tools/termios_linux.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/tools/termios_linux.h b/tools/termios_linux.h +index 0806a91180a0..0e5a5c475b55 100644 +--- a/tools/termios_linux.h ++++ b/tools/termios_linux.h +@@ -32,13 +32,13 @@ + #include + #include + +-#if defined(BOTHER) && defined(TCGETS2) ++#if defined(BOTHER) && defined(TCGETS2) && !defined(__powerpc64__) + #define termios termios2 + #endif + + static inline int tcgetattr(int fd, struct termios *t) + { +-#if defined(BOTHER) && defined(TCGETS2) ++#if defined(BOTHER) && defined(TCGETS2) && !defined(__powerpc64__) + return ioctl(fd, TCGETS2, t); + #else + return ioctl(fd, TCGETS, t); +@@ -50,7 +50,7 @@ static inline int tcsetattr(int fd, int a, const struct termios *t) + int cmd; + + switch (a) { +-#if defined(BOTHER) && defined(TCGETS2) ++#if defined(BOTHER) && defined(TCGETS2) && !defined(__powerpc64__) + case TCSANOW: + cmd = TCSETS2; + break; diff --git a/uboot-tools.spec b/uboot-tools.spec new file mode 100644 index 0000000..8e73278 --- /dev/null +++ b/uboot-tools.spec @@ -0,0 +1,432 @@ +#global candidate rc0 +%if 0%{?rhel} +%bcond_with toolsonly +%else +%bcond_without toolsonly +%endif + +# Set it to "opensbi" (stable) or "opensbi-unstable" (unstable, git) +%global opensbi opensbi-unstable + +Name: uboot-tools +Version: 2025.07 +Release: 2%{?candidate:.%{candidate}}.0.riscv64%{?dist} +Epoch: 1 +Summary: U-Boot utilities +# Automatically converted from old format: GPLv2+ BSD LGPL-2.1+ LGPL-2.0+ - review is highly recommended. +License: GPL-2.0-or-later AND LicenseRef-Callaway-BSD AND LGPL-2.1-or-later AND LGPL-2.0-or-later +URL: http://www.denx.de/wiki/U-Boot +ExcludeArch: s390x +Source0: https://ftp.denx.de/pub/u-boot/u-boot-%{version}%{?candidate:-%{candidate}}.tar.bz2 +Source1: aarch64-boards +Source2: riscv64-boards + +# Fedora patches to enable/disable features +Patch1: disable-VBE-by-default.patch +Patch2: enable-bootmenu-by-default.patch +# This is now legacy, most devices use bootflow, we keep this for the laggards +Patch3: uefi-distro-load-FDT-from-any-partition-on-boot-device.patch +# Identify VFAT partitions as ESP, allows EFI setvar on our images +Patch4: uefi-Add-all-options-for-EFI-System-Partitions.patch +# New function to find fdt for loading from disk +Patch6: uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch +# Enable UEFI SetVariable for devices without backed storage +Patch7: uefi-enable-SetVariableRT-with-volotile-storage.patch +# Enable UEFI HTTPS boot for all Fedora firmware +Patch8: uefi-enable-https-boot-by-default.patch +# Fix PPC tools build +Patch9: tools-termios_linux.h-Fix-build-error-on-ppc64.patch + +# Device improvments +# USB-PD improvements +Patch10: USB-PD-TCPM-improvements.patch +# Rockchips improvements +Patch11: rockchip-Enable-preboot-start-for-pci-usb.patch +# Rockchip DT rebase for fixes +Patch12: Rebase-to-upstream-6.15.5-rockchip-DTs.patch +Patch13: Initial-MNT-Reform2-support.patch +# Fix Jetson Nano +Patch14: p3450-fix-board.patch + +# Add EFI_PARTITION_INFO_PROTOCOL support +Patch20: disk-efi-Move-logic-to-get-a-GPT-entry-into-a-helper.patch +Patch21: disk-efi-expose-the-part_get_gpt_pte-helper-function.patch +Patch22: efi_loader-disk-add-EFI_PARTITION_INFO_PROTOCOL-supp.patch +Patch23: efi_selftest-Add-basic-partition-info-check-to-block.patch + + +# RISCV (riscv64): +Patch30: improve-riscv64-configs.patch + +BuildRequires: bc +BuildRequires: bison +BuildRequires: dtc +BuildRequires: flex +BuildRequires: gcc +BuildRequires: gnutls-devel +BuildRequires: libuuid-devel +BuildRequires: make +BuildRequires: ncurses-devel +BuildRequires: openssl-devel +BuildRequires: openssl-devel-engine +BuildRequires: perl-interpreter +BuildRequires: python3-devel +BuildRequires: python3-setuptools +BuildRequires: python3-libfdt +BuildRequires: SDL2-devel +BuildRequires: swig +%if %{with toolsonly} +%ifarch aarch64 +BuildRequires: arm-trusted-firmware-armv8 +BuildRequires: crust-firmware +BuildRequires: python3-pyelftools +BuildRequires: xxd +%endif +%ifarch riscv64 +BuildRequires: %{opensbi} +%endif +%endif +Requires: dtc +%ifarch riscv64 +BuildRequires: %{opensbi} +%endif + +%description +This package contains a few U-Boot utilities - mkimage for creating boot images +and fw_printenv/fw_setenv for manipulating the boot environment variables. + +%if %{with toolsonly} +%ifarch aarch64 +%package -n uboot-images-armv8 +Summary: U-Boot firmware images for aarch64 boards +BuildArch: noarch + +%description -n uboot-images-armv8 +U-Boot firmware binaries for aarch64 boards +%endif + +%ifarch riscv64 +%package -n uboot-images-riscv64 +Summary: U-Boot firmware images for riscv64 boards +BuildArch: noarch + +%description -n uboot-images-riscv64 +U-Boot firmware binaries for riscv64 boards +%endif +%endif + +%prep +%autosetup -p1 -n u-boot-%{version}%{?candidate:-%{candidate}} + +cp %SOURCE1 %SOURCE2 . + +%build +mkdir builds + +%make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-only_defconfig O=builds/ +%make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" tools-all O=builds/ + +%if %{with toolsonly} +# OpenSBI firmware is distributed in U-Boot SPL images +%ifarch riscv64 +export OPENSBI=%{_datadir}/%{opensbi}/generic/firmware/fw_dynamic.bin +%endif + +%ifarch aarch64 riscv64 +for board in $(cat %{_arch}-boards) +do + echo "Building board: $board" + mkdir builds/$(echo $board)/ + + # ATF selection, needs improving, suggestions of ATF SoC to Board matrix welcome + sun50i=(a64-olinuxino a64-olinuxino-emmc amarula_a64_relic bananapi_m64 nanopi_a64 oceanic_5205_5inmfd orangepi_win pine64-lts pine64_plus pine64_plus pinebook pinephone pinephone pinetab sopine_baseboard teres_i) + if [[ " ${sun50i[*]} " == *" $board "* ]]; then + echo "Board: $board using sun50i_a64" + cp /usr/share/arm-trusted-firmware/sun50i_a64/bl31.bin builds/$(echo $board)/atf-bl31 + cp /usr/share/crust-firmware/a64/scp.bin builds/$(echo $board)/ + fi + sun50h5=(bananapi_m2_plus_h5 emlid_neutis_n5_devboard libretech_all_h3_cc_h5 libretech_all_h3_it_h5 libretech_all_h5_cc_h5 nanopi_neo2 nanopi_neo_plus2 nanopi_r1s_h5 orangepi_pc2 orangepi_prime orangepi_zero_plus2 orangepi_zero_plus) + if [[ " ${sun50h5[*]} " == *" $board "* ]]; then + echo "Board: $board using sun50i_h6" + cp /usr/share/arm-trusted-firmware/sun50i_a64/bl31.bin builds/$(echo $board)/atf-bl31 + cp /usr/share/crust-firmware/h5/scp.bin builds/$(echo $board)/ + fi + sun50h6=(beelink_gs1 emlid_neutis_n5_devboard orangepi_3 orangepi_lite2 orangepi_one_plus pine_h64 tanix_tx6) + if [[ " ${sun50h6[*]} " == *" $board "* ]]; then + echo "Board: $board using sun50i_h6" + cp /usr/share/arm-trusted-firmware/sun50i_h6/bl31.bin builds/$(echo $board)/atf-bl31 + cp /usr/share/crust-firmware/h6/scp.bin builds/$(echo $board)/ + fi + sun50i_h616=(anbernic_rg35xx_h700 orangepi_zero2 orangepi_zero2w orangepi_zero3 transpeed-8k618-t x96_mate) + if [[ " ${sun50i_h616[*]} " == *" $board "* ]]; then + echo "Board: $board using sun50i_h616" + cp /usr/share/arm-trusted-firmware/sun50i_h616/bl31.bin builds/$(echo $board)/atf-bl31 + fi + rk3328=(evb-rk3328 nanopi-r2c-plus-rk3328 nanopi-r2c-rk3328 nanopi-r2s-rk3328 nanopi-r2s-plus-rk3328 orangepi-r1-plus-lts-rk3328 orangepi-r1-plus-rk3328 roc-cc-rk3328 rock64-rk3328 rock-pi-e-rk3328 rock-pi-e-v3-rk3328) + if [[ " ${rk3328[*]} " == *" $board "* ]]; then + echo "Board: $board using rk3328" + cp /usr/share/arm-trusted-firmware/rk3328/bl31.elf builds/$(echo $board)/atf-bl31 + fi + rk3368=(evb-px5 geekbox) + if [[ " ${rk3368[*]} " == *" $board "* ]]; then + echo "Board: $board using rk3368" + cp /usr/share/arm-trusted-firmware/rk3368/bl31.elf builds/$(echo $board)/atf-bl31 + fi + rk3399=(eaidk-610-rk3399 evb-rk3399 ficus-rk3399 firefly-rk3399 khadas-edge-captain-rk3399 khadas-edge-rk3399 khadas-edge-v-rk3399 leez-rk3399 nanopc-t4-rk3399 nanopi-m4-2gb-rk3399 nanopi-m4b-rk3399 nanopi-m4-rk3399 nanopi-neo4-rk3399 nanopi-r4s-rk3399 orangepi-rk3399 pinebook-pro-rk3399 pinephone-pro-rk3399 puma-rk3399 rock-4c-plus-rk3399 rock-4se-rk3399 rock960-rk3399 rock-pi-4c-rk3399 rock-pi-4-rk3399 rock-pi-n10-rk3399pro rockpro64-rk3399 roc-pc-mezzanine-rk3399 roc-pc-rk3399) + if [[ " ${rk3399[*]} " == *" $board "* ]]; then + echo "Board: $board using rk3399" + cp /usr/share/arm-trusted-firmware/rk3399/* builds/$(echo $board)/ + cp builds/$(echo $board)/bl31.elf builds/$(echo $board)/atf-bl31 + fi + zynqmp=(xilinx_zynqmp_kria xilinx_zynqmp_virt) + if [[ " ${zynqmp[*]} " == *" $board "* ]]; then + echo "Board: $board using zynqmp" + cp /usr/share/arm-trusted-firmware/zynqmp/bl31.bin builds/$(echo $board)/atf-bl31 + fi + # End ATF + + make $(echo $board)_defconfig O=builds/$(echo $board)/ + BL31=builds/$(echo $board)/atf-bl31 %make_build HOSTCC="gcc $RPM_OPT_FLAGS" CROSS_COMPILE="" O=builds/$(echo $board)/ + +done + +%endif +%endif + +%install +mkdir -p %{buildroot}%{_bindir} +mkdir -p %{buildroot}%{_mandir}/man1 +mkdir -p %{buildroot}%{_datadir}/uboot/ + +%if %{with toolsonly} +%ifarch aarch64 +for board in $(ls builds) +do + for file in u-boot.bin u-boot.img u-boot-dtb.img u-boot-sunxi-with-spl.bin u-boot-rockchip-spi.bin u-boot-rockchip.bin + do + if [ -f builds/$(echo $board)/$(echo $file) ]; then + install -pD -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/$(echo $file) + fi + done +done + +# Just for xilinx_zynqmp +for board in "xilinx_zynqmp_kria xilinx_zynqmp_virt" +do + for file in u-boot.itb spl/boot.bin + do + if [ -f builds/$(echo $board)/$(echo $file) ]; then + install -pD -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/$(echo $file) + fi + done +done + +# For Apple M-series we also need the nodtb variant +install -pD -m 0644 builds/apple_m1/u-boot-nodtb.bin %{buildroot}%{_datadir}/uboot/apple_m1/u-boot-nodtb.bin +%endif + +%ifarch riscv64 +for board in $(ls builds) +do + for file in u-boot.itb spl/u-boot-spl.bin spl/u-boot-spl.bin.normal.out + do + if [ -f builds/$(echo $board)/$(echo $file) ]; then + install -pD -m 0644 builds/$(echo $board)/$(echo $file) %{buildroot}%{_datadir}/uboot/$(echo $board)/$(echo $file) + fi + done +done +%endif + +# Bit of a hack to remove binaries we don't use as they're large +for board in $(ls builds) +do + rm -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot.dtb + if [ -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot-sunxi-with-spl.bin ]; then + rm -f %{buildroot}%{_datadir}/uboot/$(echo $board)/u-boot{,-dtb}.* + fi +done +%endif + +for tool in dumpimage env/fw_printenv fdt_add_pubkey fit_check_sign fit_info gdb/gdbcont gdb/gdbsend gen_eth_addr gen_ethaddr_crc ifwitool img2srec kwboot mkeficapsule mkenvimage mkimage mksunxiboot ncb proftool sunxi-spl-image-builder +do +install -p -m 0755 builds/tools/$tool %{buildroot}%{_bindir} +done +for tool in dumpimage kwboot mkeficapsule mkimage +do +install -p -m 0644 doc/$tool.1 %{buildroot}%{_mandir}/man1 +done + +install -p -m 0755 builds/tools/env/fw_printenv %{buildroot}%{_bindir} +( cd %{buildroot}%{_bindir}; ln -sf fw_printenv fw_setenv ) + +%files +%license Licenses/* +%doc README doc/develop/distro.rst doc/README.gpt +%doc doc/develop/uefi doc/usage doc/arch/arm64.rst +%{_bindir}/* +%{_mandir}/man1/dumpimage.1* +%{_mandir}/man1/kwboot.1* +%{_mandir}/man1/mkeficapsule.1* +%{_mandir}/man1/mkimage.1* + +%if %{with toolsonly} +%ifarch aarch64 +%files -n uboot-images-armv8 +%license Licenses/* +%dir %{_datadir}/uboot/ +%{_datadir}/uboot/* +%endif + +%ifarch riscv64 +%files -n uboot-images-riscv64 +%license Licenses/* +%dir %{_datadir}/uboot/ +%{_datadir}/uboot/* +%endif +%endif + +%changelog +* Fri Jul 11 2025 David Abdurachmanov - 1:2025.07-2.0.riscv64 +- Update for riscv64 + +* Thu Jul 10 2025 Peter Robinson - 1:2025.07-2 +- Update patch for rebase issue + +* Wed Jul 09 2025 Peter Robinson - 1:2025.07-1 +- Update to 2025.07 GA + +* Fri Jun 27 2025 Peter Robinson - 1:2025.07-0.5.rc5 +- Update to 2025.07 RC5 +- Enable LWIP stack by default +- Enable HTTP(s) boot support + +* Thu Jun 26 2025 Javier Martinez Canillas - 1:2025.07-0.4.rc4 +- Add EFI_PARTITION_INFO_PROTOCOL support + +* Sun Jun 15 2025 Peter Robinson - 1:2025.07-0.3.rc4 +- Update to 2025.07 RC4 + +* Tue May 13 2025 Peter Robinson - 1:2025.07-0.2.rc2 +- Update to 2025.07 RC2 + +* Thu May 01 2025 Peter Robinson - 1:2025.07-0.1.rc1 +- Update to 2025.07 RC1 + +* Sun Apr 20 2025 Peter Robinson - 1:2025.04-2 +- Fix for RPi5 serial console + +* Tue Apr 08 2025 Peter Robinson - 1:2025.04-1 +- Update to 2025.04 GA + +* Tue Mar 25 2025 Peter Robinson - 1:2025.04-0.7.rc5 +- Update to 2025.04 RC5 + +* Wed Mar 12 2025 Peter Robinson - 1:2025.04-0.6.rc4 +- Update to 2025.04 RC4 + +* Wed Feb 26 2025 Peter Robinson - 1:2025.04-0.5.rc3 +- Update to 2025.04 RC3 + +* Tue Feb 18 2025 David Abdurachmanov - 1:2025.04-0.4.rc2 +- Add support for riscv64 + +* Tue Feb 11 2025 Peter Robinson - 1:2025.04-0.3.rc2 +- Update to 2025.05 RC2 + +* Tue Feb 11 2025 Peter Robinson - 1:2025.04-0.2.rc1 +- Update to 2025.05 RC1 + +* Tue Jan 28 2025 Peter Robinson - 1:2025.01-3 +- Add new fdt_add_pubkey tool + +* Sun Jan 19 2025 Fedora Release Engineering - 1:2025.01-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_42_Mass_Rebuild + +* Tue Jan 07 2025 Peter Robinson - 1:2025.01-1 +- Update to 2025.01 GA + +* Mon Jan 06 2025 Peter Robinson - 1:2025.01-0.2.rc6 +- Rebuild for TF-A 2.12 + +* Tue Dec 31 2024 Peter Robinson - 1:2025.01-0.1.rc6 +- Update to 2025.01 RC6 + +* Fri Oct 11 2024 Peter Robinson - 1:2024.10-1 +- Update to 2024.10 GA +- Fix passing RPi firmware CMA setting to kernel DT +- Update Geekbox + +* Thu Oct 03 2024 Peter Robinson - 1:2024.10-0.8.rc6 +- Pass CMA FW setting through to kernel DT for Raspberry Pi + +* Tue Oct 01 2024 Peter Robinson - 1:2024.10-0.7.rc6 +- Update to 2024.10 RC6 + +* Mon Sep 16 2024 Peter Robinson - 1:2024.10-0.6.rc5 +- Update to 2024.10 RC5 + +* Fri Sep 6 2024 Peter Robinson - 1:2024.10-0.5.rc4 +- Add missing licenses directory + +* Tue Sep 03 2024 Peter Robinson - 1:2024.10-0.4.rc4 +- Update to 2024.10 RC4 + +* Mon Sep 02 2024 Peter Robinson - 1:2024.10-0.3.rc3 +- Fix Allwinner firmware chainloading (rhbz#2309138) +- Fix ATF firmware selection on a number of devices +- Support Allwinner SCP firmware (fixes suspend/resume) + +* Tue Aug 27 2024 Peter Robinson - 1:2024.10-0.2.rc3 +- Update to 2024.10 RC3 +- Enable initial QCM6490 SoC support + +* Thu Aug 15 2024 Peter Robinson - 1:2024.10-0.1.rc2 +- Update to 2024.10 RC2 + +* Tue Jul 23 2024 Peter Robinson - 1:2024.07-1 +- Update to 2024.07 + +* Sat Jul 20 2024 Fedora Release Engineering - 1:2024.07-0.3.rc4 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_41_Mass_Rebuild + +* Tue Jun 18 2024 Peter Robinson - 1:2024.07-0.2.rc4 +- Update to 2024.07 RC4 + +* Sat May 25 2024 Peter Robinson - 1:2024.07-0.1.rc3 +- Update to 2024.07 RC3 + +* Wed Apr 03 2024 Peter Robinson - 1:2024.04-1 +- Update to 2024.04 GA +- Rockchip rk3328 USB fixes + +* Wed Mar 27 2024 Peter Robinson - 1:2024.04-0.8.rc5 +- Update to 2024.04 RC5 + +* Thu Mar 21 2024 Peter Robinson - 1:2024.04-0.7.rc4 +- Updated patch for DTB loading + +* Fri Mar 15 2024 Peter Robinson - 1:2024.04-0.6.rc4 +- Updated fix for FDT load + +* Wed Mar 13 2024 Peter Robinson - 1:2024.04-0.5.rc4 +- Fixes for Rockchip rk3399 autoboot + +* Tue Mar 12 2024 Peter Robinson - 1:2024.04-0.4.rc4 +- Update to 2024.04 RC4 +- Initial fix for loading DT off /boot (rhbz 2247873) + +* Thu Feb 29 2024 Peter Robinson - 1:2024.04-0.3.rc3 +- Update to 2024.04 RC3 +- Enable a number of new upstream devices +- Upstream now builds Rockchip SPI artifacts +- Various cleanups +- Fix ESP partition detection to enable EFI vars + +* Wed Feb 14 2024 Peter Robinson - 1:2024.04-0.2.rc2 +- Update to 2024.04 RC2 + +* Sat Jan 27 2024 Fedora Release Engineering - 1:2024.01-2 +- Rebuilt for https://fedoraproject.org/wiki/Fedora_40_Mass_Rebuild + +* Mon Jan 08 2024 Peter Robinson - 1:2024.01-1 +- Update to 2024.01 diff --git a/uefi-Add-all-options-for-EFI-System-Partitions.patch b/uefi-Add-all-options-for-EFI-System-Partitions.patch new file mode 100644 index 0000000..3bf1ec8 --- /dev/null +++ b/uefi-Add-all-options-for-EFI-System-Partitions.patch @@ -0,0 +1,57 @@ +From 86782e882e9542f5f402e00cd87efb36ad0552d3 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Sat, 2 Mar 2024 11:17:42 +0000 +Subject: [PATCH v4] disk: dos: Add all options for EFI System Partitions + +The EFI spec states that the ESP can be any of FAT12/16/32 but for +compatibility doesn't necssarily require the partition to be the +EFI partition table ID of 0xef. A number of arm devices will not +find their firmware on a FAT partition with an ID of 0xef so also +allow the original FAT12/16/32 partition IDs as they are also +permissable for an ESP. + +Signed-off-by: Peter Robinson +--- + +v2: +- Add 0x0c option +- Make hex constants consistent +- Move from if to switch statement +v3: +- Fix switch brain fart +v4: +- Drop boot_ind out of switch + + disk/part_dos.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/disk/part_dos.c b/disk/part_dos.c +index 567ead7511d..a35181dff4f 100644 +--- a/disk/part_dos.c ++++ b/disk/part_dos.c +@@ -40,10 +40,21 @@ static int get_bootable(dos_partition_t *p) + { + int ret = 0; + +- if (p->sys_ind == 0xef) ++ switch (p->sys_ind) { ++ case 0x01: ++ case 0x06: ++ case 0x0b: ++ case 0x0c: ++ case 0xef: + ret |= PART_EFI_SYSTEM_PARTITION; ++ break; ++ default: ++ break; ++ } ++ + if (p->boot_ind == 0x80) + ret |= PART_BOOTABLE; ++ + return ret; + } + +-- +2.44.0 + diff --git a/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch new file mode 100644 index 0000000..5954848 --- /dev/null +++ b/uefi-distro-load-FDT-from-any-partition-on-boot-device.patch @@ -0,0 +1,87 @@ +From 4306c538d4a00dd1aa46c55c3c4005c2b0bf7cd5 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 24 Nov 2022 12:57:55 +0000 +Subject: [PATCH] distro: load FDT from any partition on boot device + +In the EFI_LOADER boot path, we were only checking the FAT partition +containing the EFI payload for dtb files. But this is somewhat of a +fiction. In reality there will be one small (V)FAT partition containing +grub (or whatever the payload may be), and a second boot partition +containing kernel/initrd/fdt (typically ext4). It is this second +partition where we should be looking for a FDT to load. + +So instead scan all the partitions of the disk containing the EFI +payload. This matches where grub looks for kernel/initrd (barring +custom grub.cfg, in which case the user can use grub's 'devicetree' +command to load the correct FDT). + +The other option is somehow passing the ${fdtfile} to grub so that it +can load the FDT based on selected kernel version location (which grub +knows) and SoC/board specific ${fdtfile} (which grub does not know). + +Signed-off-by: Rob Clark +Signed-off-by: Peter Robinson +--- + include/config_distro_bootcmd.h | 37 +++++++++++++++++++++------------ + 1 file changed, 24 insertions(+), 13 deletions(-) + +diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h +index fcb319a20ae..e71004fad9c 100644 +--- a/include/config_distro_bootcmd.h ++++ b/include/config_distro_bootcmd.h +@@ -155,28 +155,39 @@ + "fi\0" \ + \ + "load_efi_dtb=" \ +- "load ${devtype} ${devnum}:${distro_bootpart} " \ +- "${fdt_addr_r} ${prefix}${efi_fdtfile}\0" \ ++ "load ${devtype} ${devnum}:${dtb_devp} " \ ++ "${fdt_addr_r} ${prefix}${efi_fdtfile} && " \ ++ "run boot_efi_binary\0" \ + \ + "efi_dtb_prefixes=/ /dtb/ /dtb/current/\0" \ +- "scan_dev_for_efi=" \ ++ "scan_dev_for_dtb=" \ + "setenv efi_fdtfile ${fdtfile}; " \ + BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + BOOTENV_RUN_EXTENSION_INIT \ +- "for prefix in ${efi_dtb_prefixes}; do " \ +- "if test -e ${devtype} " \ +- "${devnum}:${distro_bootpart} " \ +- "${prefix}${efi_fdtfile}; then " \ +- "run load_efi_dtb; " \ +- BOOTENV_RUN_EXTENSION_APPLY \ +- "fi;" \ +- "done;" \ +- "run boot_efi_bootmgr;" \ ++ "part list ${devtype} ${devnum} dtb_devplist; " \ ++ "env exists dtb_devplist || setenv dtb_devplist " \ ++ "${distro_bootpart}; " \ ++ "for dtb_devp in ${dtb_devplist}; do " \ ++ "for prefix in ${efi_dtb_prefixes}; do " \ ++ "if test -e ${devtype} " \ ++ "${devnum}:${dtb_devp} " \ ++ "${prefix}${efi_fdtfile};"\ ++ " then " \ ++ "echo Found DTB ${devtype} " \ ++ "${devnum}:${dtb_devp} " \ ++ "${prefix}${efi_fdtfile};"\ ++ "run load_efi_dtb; " \ ++ BOOTENV_RUN_EXTENSION_APPLY \ ++ "fi;" \ ++ "done; " \ ++ "done; " \ ++ "run boot_efi_binary\0" \ ++ "scan_dev_for_efi=" \ + "if test -e ${devtype} ${devnum}:${distro_bootpart} " \ + "efi/boot/"BOOTEFI_NAME"; then " \ + "echo Found EFI removable media binary " \ + "efi/boot/"BOOTEFI_NAME"; " \ +- "run boot_efi_binary; " \ ++ "run scan_dev_for_dtb; " \ + "echo EFI LOAD FAILED: continuing...; " \ + "fi; " \ + "setenv efi_fdtfile\0" +-- +2.38.1 + diff --git a/uefi-enable-SetVariableRT-with-volotile-storage.patch b/uefi-enable-SetVariableRT-with-volotile-storage.patch new file mode 100644 index 0000000..ee9bcf4 --- /dev/null +++ b/uefi-enable-SetVariableRT-with-volotile-storage.patch @@ -0,0 +1,33 @@ +From fd736dd720b29fa69a4bb87492f3f94dc6076996 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Tue, 25 Mar 2025 17:13:44 +0000 +Subject: [PATCH] efi: enable SetVariableRT with volotile storage + +Signed-off-by: Peter Robinson +--- + lib/efi_loader/Kconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig +index d4f6b56afaa..3e522131b01 100644 +--- a/lib/efi_loader/Kconfig ++++ b/lib/efi_loader/Kconfig +@@ -108,6 +108,7 @@ choice + config EFI_VARIABLE_FILE_STORE + bool "Store non-volatile UEFI variables as file" + depends on FAT_WRITE ++ default y + help + Select this option if you want non-volatile UEFI variables to be + stored as file /ubootefi.var on the EFI system partition. +@@ -115,6 +116,7 @@ config EFI_VARIABLE_FILE_STORE + config EFI_RT_VOLATILE_STORE + bool "Allow variable runtime services in volatile storage (e.g RAM)" + depends on EFI_VARIABLE_FILE_STORE ++ default y + help + When EFI variables are stored on file we don't allow SetVariableRT, + since the OS doesn't know how to write that file. At the same time +-- +2.49.0 + diff --git a/uefi-enable-https-boot-by-default.patch b/uefi-enable-https-boot-by-default.patch new file mode 100644 index 0000000..38a9928 --- /dev/null +++ b/uefi-enable-https-boot-by-default.patch @@ -0,0 +1,81 @@ +From 2f532a911729e4b51cc596f4c671789fdbbccba9 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Wed, 25 Jun 2025 16:08:23 +0100 +Subject: [PATCH] enable https boot by default + +Signed-off-by: Peter Robinson +--- + Kconfig | 3 ++- + cmd/Kconfig | 1 + + lib/efi_loader/Kconfig | 1 + + lib/mbedtls/Kconfig | 3 ++- + 4 files changed, 6 insertions(+), 2 deletions(-) + +diff --git a/Kconfig b/Kconfig +index 51358633762..869f0b4cc25 100644 +--- a/Kconfig ++++ b/Kconfig +@@ -758,7 +758,7 @@ menu "Networking" + + choice + prompt "Networking stack" +- default NET ++ default NET_LWIP + + config NO_NET + bool "No networking support" +@@ -774,6 +774,7 @@ config NET + + config NET_LWIP + bool "Use lwIP for networking stack" ++ default y + imply NETDEVICES + help + Include networking support based on the lwIP (lightweight IP) +diff --git a/cmd/Kconfig b/cmd/Kconfig +index e4e1ae1c04d..d6faec3ace1 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -2162,6 +2162,7 @@ config CMD_WGET + + config WGET_HTTPS + bool "wget https" ++ default y + depends on CMD_WGET + depends on PROT_TCP_LWIP + depends on MBEDTLS_LIB +diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig +index 3dadbc54b58..48ed2584160 100644 +--- a/lib/efi_loader/Kconfig ++++ b/lib/efi_loader/Kconfig +@@ -552,6 +552,7 @@ config EFI_BOOTMGR + + config EFI_HTTP_BOOT + bool "EFI HTTP Boot support" ++ default y + depends on NET || NET_LWIP + select CMD_NET + select CMD_DNS +diff --git a/lib/mbedtls/Kconfig b/lib/mbedtls/Kconfig +index 789721ee6cd..7a241c2bc26 100644 +--- a/lib/mbedtls/Kconfig ++++ b/lib/mbedtls/Kconfig +@@ -2,7 +2,7 @@ + + choice + prompt "Crypto libraries (U-Boot Proper)" +- default LEGACY_HASHING_AND_CRYPTO ++ default MBEDTLS_LIB + help + Select crypto libraries. + LEGACY_HASHING_AND_CRYPTO for legacy crypto libraries, +@@ -15,6 +15,7 @@ config LEGACY_HASHING_AND_CRYPTO + + config MBEDTLS_LIB + bool "MbedTLS libraries" ++ default y + select MBEDTLS_LIB_X509 + endchoice + +-- +2.50.0 diff --git a/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch new file mode 100644 index 0000000..b89526c --- /dev/null +++ b/uefi-initial-find_fdt_location-for-finding-the-DT-on-disk.patch @@ -0,0 +1,202 @@ +From 80693a6a332f40e0bb5ae79de1b3106976c2aef4 Mon Sep 17 00:00:00 2001 +From: Peter Robinson +Date: Thu, 10 Jul 2025 12:19:43 +0100 +Subject: [PATCH] initial find_fdt_location for finding the DT on disk + +The old distro boot looked for a DT on the first boot partition +in the /dtb or /dtb/current directories, and Fedora extended this +to look not just on the boot partition but all the partitions on +that disk. + +The new ways of booting, both bootstd and bootefi bootmgr processes +don't properly look for those options. This provides a function +to search for the DTB on disk so that if the other DT mechanisms +don't work this will look for one on disk to provide a working DT +so that devices will continue to work as they did previously. + +Signed-off-by: Peter Robinson +--- + cmd/bootefi.c | 1 + + cmd/bootmenu.c | 5 ++ + include/efi_loader.h | 2 + + lib/efi_loader/efi_helper.c | 104 ++++++++++++++++++++++++++++++++++++ + 4 files changed, 112 insertions(+) + +diff --git a/cmd/bootefi.c b/cmd/bootefi.c +index 8e8752127ed..347f5573bf0 100644 +--- a/cmd/bootefi.c ++++ b/cmd/bootefi.c +@@ -147,6 +147,7 @@ static int do_bootefi(struct cmd_tbl *cmdtp, int flag, int argc, + if (argc > 2) { + uintptr_t fdt_addr; + ++ /* Do we need to run find_fdt_location here?*/ + fdt_addr = hextoul(argv[2], NULL); + fdt = map_sysmem(fdt_addr, 0); + } else { +diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c +index d3108778c6f..de5fa96b08d 100644 +--- a/cmd/bootmenu.c ++++ b/cmd/bootmenu.c +@@ -502,6 +502,11 @@ static void handle_uefi_bootnext(void) + u16 bootnext; + efi_status_t ret; + efi_uintn_t size; ++ const char *fdt_opt; ++ ++ /* Find the DTB on disk */ ++ log_debug("We will load the DTB\n"); ++ fdt_opt = find_fdt_location(); + + /* Initialize EFI drivers */ + ret = efi_init_obj_list(); +diff --git a/include/efi_loader.h b/include/efi_loader.h +index 3e70ac07055..df8d0c2a64c 100644 +--- a/include/efi_loader.h ++++ b/include/efi_loader.h +@@ -570,6 +570,8 @@ struct efi_register_notify_event { + struct list_head handles; + }; + ++/* Find the FDT on any partition */ ++char *find_fdt_location(void); + /* called at pre-initialization */ + int efi_init_early(void); + /* Initialize efi execution environment */ +diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c +index 44b806aadc4..e715a9190ae 100644 +--- a/lib/efi_loader/efi_helper.c ++++ b/lib/efi_loader/efi_helper.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -98,6 +99,99 @@ int efi_get_pxe_arch(void) + return -EINVAL; + } + ++/* We need to pass a blk device in and return a location, or a loaded DT */ ++char *find_fdt_location(void) ++{ ++ const char *fdt_filename; ++ /* FIXME: dynamic size */ ++ char fdt_fullpath[60]; ++ const char *prefix; ++ struct udevice *blk; ++ /* FIXME: Fedora really only cares about first 2*/ ++ int MAX_PART = 8; ++ int part; ++ struct disk_partition info; ++ int fdtext; ++ int ret; ++ int retfdt; ++ int retload; ++ loff_t fdtsize; ++ ulong pbraddr; ++ loff_t len_read; ++ ++ /* step one logic: we have the DT name we're hunting for */ ++ fdt_filename = env_get("fdtfile"); ++ if (fdt_filename) { ++ log_debug("FFL: We're looking for the DTB now!: %s\n", fdt_filename); ++ ++ /* probe all block disks to search for fdt */ ++ uclass_foreach_dev_probe(UCLASS_BLK, blk) { ++ log_debug("FFL: dev name: %s\n", blk->name); ++ struct blk_desc *desc; ++ desc = dev_get_uclass_plat(blk); ++ /* we should get a partition count here for looping */ ++ /* For loop for each partition */ ++ /* Need to also deal with zero part whole disk - part_get_info_whole_disk */ ++ for (part = 1; part <= MAX_PART; part++) { ++ log_debug("FFL: part num: %d\n", part); ++ ret = part_get_info(desc, part, &info); ++ /* if we have partition check it for DT */ ++ if (ret < 0) { ++ log_debug("FFL: no partition\n"); ++ } else { ++ log_debug("FFL: we have a partition\n"); ++ /* we should have a case/for prefix in =/ /dtb/ /dtb/current/ */ ++ /* but for now we hard code if for Fedora */ ++ prefix = "/dtb"; ++ snprintf(fdt_fullpath, sizeof(fdt_fullpath), "%s/%s", prefix, fdt_filename); ++ log_debug("FFL: full name: %s\n", fdt_fullpath); ++ /* search for DT on partition and either find and exit or continue */ ++ if (fs_set_blk_dev_with_part(desc, part) == 0){ ++ log_debug("FFL: set block part pass\n"); ++ fdtext = fs_exists(fdt_fullpath); ++ if (fdtext) { ++ /* we have a fdt!*/ ++ if (fs_set_blk_dev_with_part(desc, part) == 0){ ++ retfdt = fs_size(fdt_fullpath, &fdtsize); ++ if (retfdt == 0) { ++ log_debug("FFL: we have found a DT on disk, size %lld\n", fdtsize); ++ /* Get the main fdt and map it */ ++ const char *fdt_pbr; ++ fdt_pbr = env_get("fdt_addr_r"); ++ pbraddr = hextoul(fdt_pbr, NULL); ++ log_debug("FFL: fdr addr: %s\n", fdt_pbr); ++ if (fs_set_blk_dev_with_part(desc, part) == 0){ ++ retload = fs_read(fdt_fullpath, pbraddr, 0, fdtsize, &len_read); ++ if (retload == 0) { ++ log_debug("FFL: we have a loaded DT, size %lld we can return\n", fdtsize); ++ log_info("Found DTB: %s\n", fdt_filename); ++ return fdt_pbr; ++ } else { ++ log_debug("FFL: DT load failed\n"); ++ } ++ } ++ } else { ++ log_debug("FFL: we DON'T have a DT with size\n"); ++ } ++ } ++ } else { ++ /* we don't have a fdt!*/ ++ log_debug("FFL: we DON'T have a DT\n"); ++ } ++ } else { ++ log_debug("FFL: set block part FAIL\n"); ++ } ++ } ++ } ++ } ++ } else { ++ log_debug("FFL: fdt_filename not defined!!\n"); ++ } ++ ++ /* We didn't find a FDT */ ++ return NULL; ++} ++ + /** + * efi_create_current_boot_var() - Return Boot#### name were #### is replaced by + * the value of BootCurrent +@@ -558,11 +652,21 @@ efi_status_t efi_install_fdt(void *fdt) + const char *fdt_opt; + uintptr_t fdt_addr; + ++ /* Check if there is device tree loaded from disk */ ++ fdt_opt = find_fdt_location(); ++ if (fdt_opt) ++ log_debug("Found DTB on disk\n"); + /* Check if there is a hardware device tree */ + fdt_opt = env_get("fdt_addr"); ++ if (!fdt_opt) { ++ fdt_opt = env_get("fdt_addr"); ++ if (fdt_opt) ++ log_info("Found DTB: Prior firmware\n"); ++ } + /* Use our own device tree as fallback */ + if (!fdt_opt) { + fdt_opt = env_get("fdtcontroladdr"); ++ log_debug("Using DT from U-Boot\n"); + if (!fdt_opt) { + log_err("need device tree\n"); + return EFI_NOT_FOUND; +-- +2.50.0 +