diff --git a/0002-Workaround-for-a-win8.1-32-S4-resume-bug.patch b/0001-Workaround-for-a-win8.1-32-S4-resume-bug.patch similarity index 100% rename from 0002-Workaround-for-a-win8.1-32-S4-resume-bug.patch rename to 0001-Workaround-for-a-win8.1-32-S4-resume-bug.patch diff --git a/seabios-pci-refactor-the-pci_config_-functions.patch b/seabios-pci-refactor-the-pci_config_-functions.patch new file mode 100644 index 0000000..a43cb5c --- /dev/null +++ b/seabios-pci-refactor-the-pci_config_-functions.patch @@ -0,0 +1,172 @@ +From d1e13b6d631a45882471efcbe367c690e1698b42 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Volker=20R=C3=BCmelin?= +Date: Sat, 2 Apr 2022 20:28:38 +0200 +Subject: [PATCH 1/2] pci: refactor the pci_config_*() functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 4: reset: force standard PCI configuration access +RH-Commit: [1/2] 49093312e6cdddd301766fcfb91cf80260be3f05 (kraxel/centos-seabios) +RH-Bugzilla: 2086407 +RH-Acked-by: Miroslav Rezanina +RH-Acked-by: Oliver Steffen + +Split out the Standard PCI Configuration Access Mechanism +pci_ioconfig_*() functions from the pci_config_*() functions. +The standard PCI CAM functions will be used in the next patch. + +Reviewed-by: Gerd Hoffmann +Signed-off-by: Volker Rümelin +(cherry picked from commit d24f42b0d819ea473ae05b2f955b822d0126d901) +--- + src/hw/pci.c | 54 ++++++++++++++++++++++++++++++++++++++++------------ + src/hw/pci.h | 12 +++++++++++- + 2 files changed, 53 insertions(+), 13 deletions(-) + +diff --git a/src/hw/pci.c b/src/hw/pci.c +index 3df1dae4..f13cbdea 100644 +--- a/src/hw/pci.c ++++ b/src/hw/pci.c +@@ -26,63 +26,93 @@ static u32 ioconfig_cmd(u16 bdf, u32 addr) + return 0x80000000 | (bdf << 8) | (addr & 0xfc); + } + ++void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outl(val, PORT_PCI_DATA); ++} ++ + void pci_config_writel(u16 bdf, u32 addr, u32 val) + { + if (!MODESEGMENT && mmconfig) { + writel(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outl(val, PORT_PCI_DATA); ++ pci_ioconfig_writel(bdf, addr, val); + } + } + ++void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outw(val, PORT_PCI_DATA + (addr & 2)); ++} ++ + void pci_config_writew(u16 bdf, u32 addr, u16 val) + { + if (!MODESEGMENT && mmconfig) { + writew(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outw(val, PORT_PCI_DATA + (addr & 2)); ++ pci_ioconfig_writew(bdf, addr, val); + } + } + ++void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ outb(val, PORT_PCI_DATA + (addr & 3)); ++} ++ + void pci_config_writeb(u16 bdf, u32 addr, u8 val) + { + if (!MODESEGMENT && mmconfig) { + writeb(mmconfig_addr(bdf, addr), val); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- outb(val, PORT_PCI_DATA + (addr & 3)); ++ pci_ioconfig_writeb(bdf, addr, val); + } + } + ++u32 pci_ioconfig_readl(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inl(PORT_PCI_DATA); ++} ++ + u32 pci_config_readl(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readl(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inl(PORT_PCI_DATA); ++ return pci_ioconfig_readl(bdf, addr); + } + } + ++u16 pci_ioconfig_readw(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inw(PORT_PCI_DATA + (addr & 2)); ++} ++ + u16 pci_config_readw(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readw(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inw(PORT_PCI_DATA + (addr & 2)); ++ return pci_ioconfig_readw(bdf, addr); + } + } + ++u8 pci_ioconfig_readb(u16 bdf, u32 addr) ++{ ++ outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); ++ return inb(PORT_PCI_DATA + (addr & 3)); ++} ++ + u8 pci_config_readb(u16 bdf, u32 addr) + { + if (!MODESEGMENT && mmconfig) { + return readb(mmconfig_addr(bdf, addr)); + } else { +- outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); +- return inb(PORT_PCI_DATA + (addr & 3)); ++ return pci_ioconfig_readb(bdf, addr); + } + } + +diff --git a/src/hw/pci.h b/src/hw/pci.h +index 01c51f70..ee6acafc 100644 +--- a/src/hw/pci.h ++++ b/src/hw/pci.h +@@ -32,6 +32,15 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devfn) { + ; BDF >= 0 \ + ; BDF=pci_next(BDF, (BUS))) + ++// standard PCI configration access mechanism ++void pci_ioconfig_writel(u16 bdf, u32 addr, u32 val); ++void pci_ioconfig_writew(u16 bdf, u32 addr, u16 val); ++void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); ++u32 pci_ioconfig_readl(u16 bdf, u32 addr); ++u16 pci_ioconfig_readw(u16 bdf, u32 addr); ++u8 pci_ioconfig_readb(u16 bdf, u32 addr); ++ ++// PCI configuration access using either PCI CAM or PCIe ECAM + void pci_config_writel(u16 bdf, u32 addr, u32 val); + void pci_config_writew(u16 bdf, u32 addr, u16 val); + void pci_config_writeb(u16 bdf, u32 addr, u8 val); +@@ -39,9 +48,10 @@ u32 pci_config_readl(u16 bdf, u32 addr); + u16 pci_config_readw(u16 bdf, u32 addr); + u8 pci_config_readb(u16 bdf, u32 addr); + void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +-void pci_enable_mmconfig(u64 addr, const char *name); + u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); + int pci_next(int bdf, int bus); ++ ++void pci_enable_mmconfig(u64 addr, const char *name); + int pci_probe_host(void); + void pci_reboot(void); + +-- +2.31.1 + diff --git a/seabios-reset-force-standard-PCI-configuration-access.patch b/seabios-reset-force-standard-PCI-configuration-access.patch new file mode 100644 index 0000000..7502ca3 --- /dev/null +++ b/seabios-reset-force-standard-PCI-configuration-access.patch @@ -0,0 +1,157 @@ +From dbca6bf0626072c3b90ffe4f4c6e5db92814bd5d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Volker=20R=C3=BCmelin?= +Date: Sat, 2 Apr 2022 20:28:39 +0200 +Subject: [PATCH 2/2] reset: force standard PCI configuration access +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Gerd Hoffmann +RH-MergeRequest: 4: reset: force standard PCI configuration access +RH-Commit: [2/2] 70fa6dd1d546a03a3b44e438f84682325f5ee029 (kraxel/centos-seabios) +RH-Bugzilla: 2086407 +RH-Acked-by: Miroslav Rezanina +RH-Acked-by: Oliver Steffen + +After a reset of a QEMU -machine q35 guest, the PCI Express +Enhanced Configuration Mechanism is disabled and the variable +mmconfig no longer matches the configuration register PCIEXBAR +of the Q35 chipset. Until the variable mmconfig is reset to 0, +all pci_config_*() functions no longer work. + +The variable mmconfig is located in one of the read-only C-F +segments. To reset it the pci_config_*() functions are needed, +but they do not work. + +Replace all pci_config_*() calls with Standard PCI Configuration +Mechanism pci_ioconfig_*() calls until mmconfig is overwritten +with 0 by a fresh copy of the BIOS. + +This fixes + +In resume (status=0) +In 32bit resume +Attempting a hard reboot +Unable to unlock ram - bridge not found + +and a reset loop with QEMU -accel tcg. + +Signed-off-by: Volker Rümelin +(cherry picked from commit 01774004c7f7fdc9c1e8f1715f70d3b913f8d491) +--- + src/fw/shadow.c | 14 +++++++------- + src/hw/pci.c | 27 +++++++++++++++++++++++++++ + src/hw/pci.h | 6 ++++++ + 3 files changed, 40 insertions(+), 7 deletions(-) + +diff --git a/src/fw/shadow.c b/src/fw/shadow.c +index 4c627a8f..8930616e 100644 +--- a/src/fw/shadow.c ++++ b/src/fw/shadow.c +@@ -32,8 +32,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + { + // Read in current PAM settings from pci config space + union pamdata_u pamdata; +- pamdata.data32[0] = pci_config_readl(bdf, ALIGN_DOWN(pam0, 4)); +- pamdata.data32[1] = pci_config_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); ++ pamdata.data32[0] = pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4)); ++ pamdata.data32[1] = pci_ioconfig_readl(bdf, ALIGN_DOWN(pam0, 4) + 4); + u8 *pam = &pamdata.data8[pam0 & 0x03]; + + // Make ram from 0xc0000-0xf0000 writable +@@ -46,8 +46,8 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + pam[0] = 0x30; + + // Write PAM settings back to pci config space +- pci_config_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); +- pci_config_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); ++ pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4), pamdata.data32[0]); ++ pci_ioconfig_writel(bdf, ALIGN_DOWN(pam0, 4) + 4, pamdata.data32[1]); + + if (!ram_present) + // Copy bios. +@@ -59,7 +59,7 @@ __make_bios_writable_intel(u16 bdf, u32 pam0) + static void + make_bios_writable_intel(u16 bdf, u32 pam0) + { +- int reg = pci_config_readb(bdf, pam0); ++ int reg = pci_ioconfig_readb(bdf, pam0); + if (!(reg & 0x10)) { + // QEMU doesn't fully implement the piix shadow capabilities - + // if ram isn't backing the bios segment when shadowing is +@@ -125,8 +125,8 @@ make_bios_writable(void) + // At this point, statically allocated variables can't be written, + // so do this search manually. + int bdf; +- foreachbdf(bdf, 0) { +- u32 vendev = pci_config_readl(bdf, PCI_VENDOR_ID); ++ pci_ioconfig_foreachbdf(bdf, 0) { ++ u32 vendev = pci_ioconfig_readl(bdf, PCI_VENDOR_ID); + u16 vendor = vendev & 0xffff, device = vendev >> 16; + if (vendor == PCI_VENDOR_ID_INTEL + && device == PCI_DEVICE_ID_INTEL_82441) { +diff --git a/src/hw/pci.c b/src/hw/pci.c +index f13cbdea..8eda84b2 100644 +--- a/src/hw/pci.c ++++ b/src/hw/pci.c +@@ -157,6 +157,33 @@ u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) + return 0; + } + ++// Helper function for pci_ioconfig_foreachbdf() macro - return next device ++int pci_ioconfig_next(int bdf, int bus) ++{ ++ if (pci_bdf_to_fn(bdf) == 0 ++ && (pci_ioconfig_readb(bdf, PCI_HEADER_TYPE) & 0x80) == 0) ++ // Last found device wasn't a multi-function device - skip to ++ // the next device. ++ bdf += 8; ++ else ++ bdf += 1; ++ ++ for (;;) { ++ if (pci_bdf_to_bus(bdf) != bus) ++ return -1; ++ ++ u16 v = pci_ioconfig_readw(bdf, PCI_VENDOR_ID); ++ if (v != 0x0000 && v != 0xffff) ++ // Device is present. ++ return bdf; ++ ++ if (pci_bdf_to_fn(bdf) == 0) ++ bdf += 8; ++ else ++ bdf += 1; ++ } ++} ++ + // Helper function for foreachbdf() macro - return next device + int + pci_next(int bdf, int bus) +diff --git a/src/hw/pci.h b/src/hw/pci.h +index ee6acafc..b2f5baf4 100644 +--- a/src/hw/pci.h ++++ b/src/hw/pci.h +@@ -27,6 +27,11 @@ static inline u16 pci_bus_devfn_to_bdf(int bus, u16 devfn) { + return (bus << 8) | devfn; + } + ++#define pci_ioconfig_foreachbdf(BDF, BUS) \ ++ for (BDF=pci_ioconfig_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ ++ ; BDF >= 0 \ ++ ; BDF=pci_ioconfig_next(BDF, (BUS))) ++ + #define foreachbdf(BDF, BUS) \ + for (BDF=pci_next(pci_bus_devfn_to_bdf((BUS), 0)-1, (BUS)) \ + ; BDF >= 0 \ +@@ -39,6 +44,7 @@ void pci_ioconfig_writeb(u16 bdf, u32 addr, u8 val); + u32 pci_ioconfig_readl(u16 bdf, u32 addr); + u16 pci_ioconfig_readw(u16 bdf, u32 addr); + u8 pci_ioconfig_readb(u16 bdf, u32 addr); ++int pci_ioconfig_next(int bdf, int bus); + + // PCI configuration access using either PCI CAM or PCIe ECAM + void pci_config_writel(u16 bdf, u32 addr, u32 val); +-- +2.31.1 + diff --git a/seabios.spec b/seabios.spec index ef205b0..579caee 100644 --- a/seabios.spec +++ b/seabios.spec @@ -1,6 +1,6 @@ Name: seabios Version: 1.16.0 -Release: 2%{?dist} +Release: 3%{?dist} Summary: Open-source legacy BIOS implementation License: LGPLv3 @@ -8,14 +8,6 @@ URL: https://www.coreboot.org/SeaBIOS Source0: https://code.coreboot.org/p/seabios/downloads/get/seabios-1.16.0.tar.gz -Patch0002: 0002-Workaround-for-a-win8.1-32-S4-resume-bug.patch -# For bz#2004662 - RFE: "Unable to allocate resource at romfile_loader_allocate:87" when running very large VMs -Patch3: seabios-malloc-use-variable-for-ZoneHigh-size.patch -# For bz#2004662 - RFE: "Unable to allocate resource at romfile_loader_allocate:87" when running very large VMs -Patch4: seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch - -# Source-git patches - Source10: config.vga-cirrus Source12: config.vga-qxl Source13: config.vga-stdvga @@ -24,6 +16,18 @@ Source19: config.vga-virtio Source20: config.vga-ramfb Source21: config.vga-bochs-display +Patch0002: 0001-Workaround-for-a-win8.1-32-S4-resume-bug.patch +# For bz#2004662 - RFE: "Unable to allocate resource at romfile_loader_allocate:87" when running very large VMs +Patch3: seabios-malloc-use-variable-for-ZoneHigh-size.patch +# For bz#2004662 - RFE: "Unable to allocate resource at romfile_loader_allocate:87" when running very large VMs +Patch4: seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch +# For bz#2086407 - qemu reboot problem with seabios 1.16.0 +Patch5: seabios-pci-refactor-the-pci_config_-functions.patch +# For bz#2086407 - qemu reboot problem with seabios 1.16.0 +Patch6: seabios-reset-force-standard-PCI-configuration-access.patch + +# Source-git patches + BuildRequires: make BuildRequires: gcc BuildRequires: python3 iasl @@ -139,6 +143,12 @@ install -m 0644 binaries/vgabios*.bin $RPM_BUILD_ROOT%{_datadir}/seavgabios %{_datadir}/seavgabios/vgabios*.bin %changelog +* Thu May 26 2022 Miroslav Rezanina - 1.16.0-3 +- seabios-pci-refactor-the-pci_config_-functions.patch [bz#2086407] +- seabios-reset-force-standard-PCI-configuration-access.patch [bz#2086407] +- Resolves: bz#2086407 + (qemu reboot problem with seabios 1.16.0) + * Tue May 10 2022 Miroslav Rezanina - 1.16.0-2 - seabios-malloc-use-variable-for-ZoneHigh-size.patch [bz#2004662] - seabios-malloc-use-large-ZoneHigh-when-there-is-enough-memor.patch [bz#2004662]