95 lines
3.2 KiB
Diff
95 lines
3.2 KiB
Diff
commit ced615cf8146f51b5d6fe7a29107a2adc77407ca
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Author: Sathya Priya Kumar <sathyapriya.k@amd.com>
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Date: Thu Jan 11 01:20:07 2024 -0600
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rasdaemon: Add error decoding for MCA_CTL_SMU extended bits
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Enable error decoding support for the newly added extended
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error bit descriptions from MCA_CTL_SMU.
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b'0:11 can be decoded from existing array smca_smu2_mce_desc.
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Define a function to append the newly defined b'58:62 to the
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smca_smu2_mce_desc. This reduces the maintaining Reserved bits
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from b'12:57 in the code.
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Signed-off-by: Sathya Priya Kumar <sathyapriya.k@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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---
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mce-amd-smca.c | 33 ++++++++++++++++++++++++++++++++-
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ras-mce-handler.h | 1 +
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2 files changed, 33 insertions(+), 1 deletion(-)
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--- rasdaemon-0.6.7.orig/mce-amd-smca.c 2024-06-28 10:34:16.453522865 -0400
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+++ rasdaemon-0.6.7/mce-amd-smca.c 2024-06-28 10:34:46.049124270 -0400
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@@ -397,7 +397,7 @@ static const char * const smca_smu_mce_d
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"An ECC or parity error in an SMU RAM instance",
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};
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-static const char * const smca_smu2_mce_desc[] = {
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+static const char * smca_smu2_mce_desc[64] = {
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"High SRAM ECC or parity error",
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"Low SRAM ECC or parity error",
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"Data Cache Bank A ECC or parity error",
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@@ -409,6 +409,15 @@ static const char * const smca_smu2_mce_
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"Instruction Tag Cache Bank A ECC or parity error",
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"Instruction Tag Cache Bank B ECC or parity error",
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"System Hub Read Buffer ECC or parity error",
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+ "PHY RAS ECC Error",
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+};
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+
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+static const char * smca_smu2_ext_mce_desc[] = {
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+ "A correctable error from a GFX Sub-IP",
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+ "A fatal error from a GFX Sub-IP",
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+ "Reserved",
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+ "Reserved",
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+ "A poison error from a GFX Sub-IP",
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};
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static const char * const smca_mp5_mce_desc[] = {
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@@ -815,6 +824,27 @@ static struct smca_bank_name smca_names[
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[SMCA_GMI_PHY] = { "Global Memory Interconnect PHY Unit" },
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};
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+void smca_smu2_ext_err_desc(void)
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+{
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+ int i, j;
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+ int smu2_bits = 62;
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+
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+ /*
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+ * MCA_CTL_SMU error stings are defined for b'58:59 and b'62
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+ * in MI300A AMD systems. See AMD PPR MCA::SMU::MCA_CTL_SMU
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+ *
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+ * b'0:11 can be decoded from existing array smca_smu2_mce_desc.
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+ * b'12:57 are Reserved and b'58:62 are appended to the
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+ * smca_smu2_mce_desc.
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+ */
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+ for (i = 12, j = 0; i < smu2_bits || j < 5; i++, j++) {
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+ for ( ; i < 58; i++)
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+ smca_smu2_mce_desc[i] = "Reserved";
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+
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+ smca_smu2_mce_desc[i] = smca_smu2_ext_mce_desc[j];
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+ }
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+}
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+
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void amd_decode_errcode(struct mce_event *e)
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{
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@@ -906,6 +936,7 @@ unsigned short xec = (e->status >> 16) &
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mcatype_hwid = HWID_MCATYPE(ipid_high & MCI_IPID_HWID,
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(ipid_high & MCI_IPID_MCATYPE) >> 16);
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+ smca_smu2_ext_err_desc();
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fixup_hwid(m, &mcatype_hwid);
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for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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--- rasdaemon-0.6.7.orig/ras-mce-handler.h 2024-06-28 10:34:16.453522865 -0400
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+++ rasdaemon-0.6.7/ras-mce-handler.h 2024-06-28 10:34:17.795508302 -0400
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@@ -121,6 +121,7 @@ int set_intel_imc_log(enum cputype cputy
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/* Undertake AMD SMCA Error Decoding */
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void decode_smca_error(struct mce_event *e, struct mce_priv *m);
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void amd_decode_errcode(struct mce_event *e);
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+void smca_smu2_ext_err_desc(void);
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/* Per-CPU-type decoders for Intel CPUs */
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void p4_decode_model(struct mce_event *e);
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