135 lines
4.3 KiB
Diff
135 lines
4.3 KiB
Diff
commit ad0444190e02bca309a61a4bad51bc0e16c0aef5
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Author: Avadhut Naik <avadhut.naik@amd.com>
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Date: Fri May 10 13:20:19 2024 -0500
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rasdaemon: Update SMCA bank error descriptions
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Update error descriptions of SMCA bank types to support AMD's new Family
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1Ah-based processors.
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Also, modify some existing error descriptions to better reflect the error
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received.
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Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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diff --git a/mce-amd-smca.c b/mce-amd-smca.c
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index 6632663..a55e013 100644
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--- a/mce-amd-smca.c
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+++ b/mce-amd-smca.c
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@@ -108,7 +108,7 @@ static const char * const smca_ls_mce_desc[] = {
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"Store queue parity",
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"Miss address buffer payload parity",
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"L1 TLB parity",
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- "Reserved",
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+ "DC Tag error type 5",
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"DC tag error type 6",
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"DC tag error type 1",
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"Internal error type 1",
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@@ -125,6 +125,12 @@ static const char * const smca_ls_mce_desc[] = {
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"DC tag error type 3",
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"DC tag error type 5",
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"L2 fill data error",
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+ "Error on SCB cacheline state or address field",
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+ "Error on SCB data, commit pipe 0",
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+ "Error on SCB data, commit pipe 1",
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+ "Error on SCB data for non-cacheable DRAM or IO",
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+ "System Read Data Error detected by write combine buffer",
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+ "Hardware Asserts",
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};
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static const char * const smca_ls2_mce_desc[] = {
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@@ -168,7 +174,7 @@ static const char * const smca_if_mce_desc[] = {
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"BP L1-BTB Multi-Hit Error",
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"BP L2-BTB Multi-Hit Error",
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"L2 Cache Response Poison error",
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- "L2 Cache Error Response",
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+ "System Read Data error",
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"Hardware Assertion Error",
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"L1-TLB Multi-Hit",
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"L2-TLB Multi-Hit",
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@@ -182,6 +188,7 @@ static const char * const smca_l2_mce_desc[] = {
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"L2M Data Array ECC Error",
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"Hardware Assert Error",
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"SDP Read Response Parity Error",
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+ "Error initiated by programmable state machine",
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};
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static const char * const smca_de_mce_desc[] = {
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@@ -193,7 +200,7 @@ static const char * const smca_de_mce_desc[] = {
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"Fetch address FIFO parity error",
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"Patch RAM data parity error",
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"Patch RAM sequencer parity error",
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- "Micro-op buffer parity error",
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+ "Micro-op fetch queue parity error",
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"Hardware Assertion MCA Error",
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};
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@@ -235,6 +242,7 @@ static const char * const smca_l3_mce_desc[] = {
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"L3 victim queue Data Fabric error",
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"L3 Hardware Assertion",
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"XI WCB Parity Poison Creation event",
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+ "Machine check error initiated by DSM action",
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};
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static const char * const smca_cs_mce_desc[] = {
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@@ -268,6 +276,9 @@ static const char * const smca_cs2_mce_desc[] = {
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"Address Violation on the no data channel",
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"Security Violation on the no data channel",
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"Hardware Assert Error",
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+ "Shadow Tag Array Protocol Error",
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+ "Shadow Tag ECC Error",
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+ "Shadow Tag Transaction Error",
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};
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/*
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@@ -303,6 +314,8 @@ static const char * const smca_pie_mce_desc[] = {
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"A deferred error was detected in the DF",
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"Watch Dog Timer",
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"An SRAM ECC error was detected in the CNLI block",
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+ "Register access during DF Cstate",
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+ "DSM Error",
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};
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static const char * const smca_umc_mce_desc[] = {
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@@ -318,6 +331,11 @@ static const char * const smca_umc_mce_desc[] = {
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"ECS Error",
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"UMC Throttling Error",
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"Read CRC Error",
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+ "Reserved",
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+ "Reserved",
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+ "Reserved",
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+ "Reserved",
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+ "RFM SRAM ECC error",
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};
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static const char * const smca_umc_quirk_mce_desc[] = {
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@@ -391,6 +409,12 @@ static const char * const smca_psp2_mce_desc[] = {
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"TLB Bank 0 parity error",
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"TLB Bank 1 parity error",
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"System Hub Read Buffer ECC or parity error",
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+ "FUSE IP SRAM ECC or parity error",
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+ "PCRU FUSE SRAM ECC or parity error",
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+ "SIB SRAM parity error",
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+ "mpASP SECEMC Error",
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+ "mpASP A5 Hang",
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+ "SIB WDT error",
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};
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static const char * const smca_smu_mce_desc[] = {
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@@ -431,6 +455,7 @@ static const char * const smca_mp5_mce_desc[] = {
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"Instruction Cache Bank B ECC or parity error",
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"Instruction Tag Cache Bank A ECC or parity error",
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"Instruction Tag Cache Bank B ECC or parity error",
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+ "Fuse SRAM ECC or parity error",
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};
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static const char * const smca_mpdma_mce_desc[] = {
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@@ -483,6 +508,7 @@ static const char * const smca_mpdma_mce_desc[] = {
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"MPDMA PTE Internal Data FIFO ECC or parity error",
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"MPDMA PTE Command Memory DMA ECC or parity error",
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"MPDMA PTE Command Memory Internal ECC or parity error",
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+ "MPDMA TVF SDP Master Memory 7 ECC or parity error",
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};
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static const char * const smca_nbio_mce_desc[] = {
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