208 lines
8.0 KiB
Diff
208 lines
8.0 KiB
Diff
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commit 8704a85d8dc3483423ec2934fee8132f85f8fdb6
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Author: Brian WoodsGhannam, Yazen <brian.woods@amd.comYazen.Ghannam@amd.com>
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Date: Fri Nov 1 15:48:14 2019 +0100
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rasdaemon: add support for new AMD SMCA bank types
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Going forward, the Scalable Machine Check Architecture (SMCA) has some
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updated and additional bank types which show up in Zen2. The differing
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bank types include: CS_V2, PSP_V2, SMU_V2, MP5, NBIO, and PCIE. The V2
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bank types replace the original bank types but have unique HWID/MCAtype
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IDs from the originals so there's no conflicts between different
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versions or other bank types. All of the differing bank types have new
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MCE descriptions which have been added as well.
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CC: "mchehab+samsung@kernel.org" <mchehab+samsung@kernel.org>, "Namburu, Chandu-babu" <chandu@amd.com> # Thread-Topic: [PATCH 2/2] rasdaemon: add support for new AMD SMCA bank types
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Signed-off-by: Brian Woods <brian.woods@amd.com>
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Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
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Cc: Chandu-babu Namburu <chandu@amd.com>
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Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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diff --git a/mce-amd-smca.c b/mce-amd-smca.c
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index 6c3e8a5..114e786 100644
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--- a/mce-amd-smca.c
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+++ b/mce-amd-smca.c
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@@ -49,11 +49,17 @@ enum smca_bank_types {
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SMCA_FP, /* Floating Point */
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SMCA_L3_CACHE, /* L3 Cache */
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SMCA_CS, /* Coherent Slave */
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+ SMCA_CS_V2, /* Coherent Slave V2 */
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SMCA_PIE, /* Power, Interrupts, etc. */
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SMCA_UMC, /* Unified Memory Controller */
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SMCA_PB, /* Parameter Block */
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SMCA_PSP, /* Platform Security Processor */
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+ SMCA_PSP_V2, /* Platform Security Processor V2 */
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SMCA_SMU, /* System Management Unit */
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+ SMCA_SMU_V2, /* System Management Unit V2 */
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+ SMCA_MP5, /* Microprocessor 5 Unit */
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+ SMCA_NBIO, /* Northbridge IO Unit */
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+ SMCA_PCIE, /* PCI Express Unit */
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N_SMCA_BANK_TYPES
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};
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@@ -165,6 +171,23 @@ static const char * const smca_cs_mce_desc[] = {
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"Atomic request parity",
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"ECC error on probe filter access",
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};
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+/* Coherent Slave Unit V2 */
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+static const char * const smca_cs2_mce_desc[] = {
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+ "Illegal Request",
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+ "Address Violation",
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+ "Security Violation",
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+ "Illegal Response",
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+ "Unexpected Response",
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+ "Request or Probe Parity Error",
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+ "Read Response Parity Error",
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+ "Atomic Request Parity Error",
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+ "SDP read response had no match in the CS queue",
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+ "Probe Filter Protocol Error",
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+ "Probe Filter ECC Error",
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+ "SDP read response had an unexpected RETRY error",
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+ "Counter overflow error",
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+ "Counter underflow error",
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+};
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/* Power, Interrupt, etc.. */
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static const char * const smca_pie_mce_desc[] = {
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"HW assert",
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@@ -189,10 +212,75 @@ static const char * const smca_pb_mce_desc[] = {
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static const char * const smca_psp_mce_desc[] = {
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"PSP RAM ECC or parity error",
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};
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+/* Platform Security Processor V2 */
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+static const char * const smca_psp2_mce_desc[] = {
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+ "High SRAM ECC or parity error",
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+ "Low SRAM ECC or parity error",
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+ "Instruction Cache Bank 0 ECC or parity error",
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+ "Instruction Cache Bank 1 ECC or parity error",
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+ "Instruction Tag Ram 0 parity error",
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+ "Instruction Tag Ram 1 parity error",
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+ "Data Cache Bank 0 ECC or parity error",
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+ "Data Cache Bank 1 ECC or parity error",
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+ "Data Cache Bank 2 ECC or parity error",
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+ "Data Cache Bank 3 ECC or parity error",
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+ "Data Tag Bank 0 parity error",
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+ "Data Tag Bank 1 parity error",
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+ "Data Tag Bank 2 parity error",
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+ "Data Tag Bank 3 parity error",
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+ "Dirty Data Ram parity error",
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+ "TLB Bank 0 parity error",
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+ "TLB Bank 1 parity error",
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+ "System Hub Read Buffer ECC or parity error",
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+};
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/* System Management Unit */
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static const char * const smca_smu_mce_desc[] = {
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"SMU RAM ECC or parity error",
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};
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+/* System Management Unit V2 */
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+static const char * const smca_smu2_mce_desc[] = {
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+ "High SRAM ECC or parity error",
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+ "Low SRAM ECC or parity error",
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+ "Data Cache Bank A ECC or parity error",
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+ "Data Cache Bank B ECC or parity error",
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+ "Data Tag Cache Bank A ECC or parity error",
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+ "Data Tag Cache Bank B ECC or parity error",
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+ "Instruction Cache Bank A ECC or parity error",
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+ "Instruction Cache Bank B ECC or parity error",
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+ "Instruction Tag Cache Bank A ECC or parity error",
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+ "Instruction Tag Cache Bank B ECC or parity error",
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+ "System Hub Read Buffer ECC or parity error",
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+};
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+/* Microprocessor 5 Unit */
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+static const char * const smca_mp5_mce_desc[] = {
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+ "High SRAM ECC or parity error",
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+ "Low SRAM ECC or parity error",
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+ "Data Cache Bank A ECC or parity error",
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+ "Data Cache Bank B ECC or parity error",
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+ "Data Tag Cache Bank A ECC or parity error",
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+ "Data Tag Cache Bank B ECC or parity error",
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+ "Instruction Cache Bank A ECC or parity error",
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+ "Instruction Cache Bank B ECC or parity error",
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+ "Instruction Tag Cache Bank A ECC or parity error",
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+ "Instruction Tag Cache Bank B ECC or parity error",
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+};
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+/* Northbridge IO Unit */
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+static const char * const smca_nbio_mce_desc[] = {
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+ "ECC or Parity error",
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+ "PCIE error",
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+ "SDP ErrEvent error",
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+ "SDP Egress Poison Error",
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+ "IOHC Internal Poison Error",
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+};
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+/* PCI Express Unit */
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+static const char * const smca_pcie_mce_desc[] = {
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+ "CCIX PER Message logging",
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+ "CCIX Read Response with Status: Non-Data Error",
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+ "CCIX Write Response with Status: Non-Data Error",
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+ "CCIX Read Response with Status: Data Error",
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+ "CCIX Non-okay write response with data error",
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+};
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+
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struct smca_mce_desc {
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const char * const *descs;
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@@ -208,11 +296,17 @@ static struct smca_mce_desc smca_mce_descs[] = {
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[SMCA_FP] = { smca_fp_mce_desc, ARRAY_SIZE(smca_fp_mce_desc) },
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[SMCA_L3_CACHE] = { smca_l3_mce_desc, ARRAY_SIZE(smca_l3_mce_desc) },
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[SMCA_CS] = { smca_cs_mce_desc, ARRAY_SIZE(smca_cs_mce_desc) },
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+ [SMCA_CS_V2] = { smca_cs2_mce_desc, ARRAY_SIZE(smca_cs2_mce_desc) },
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[SMCA_PIE] = { smca_pie_mce_desc, ARRAY_SIZE(smca_pie_mce_desc) },
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[SMCA_UMC] = { smca_umc_mce_desc, ARRAY_SIZE(smca_umc_mce_desc) },
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[SMCA_PB] = { smca_pb_mce_desc, ARRAY_SIZE(smca_pb_mce_desc) },
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[SMCA_PSP] = { smca_psp_mce_desc, ARRAY_SIZE(smca_psp_mce_desc) },
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+ [SMCA_PSP_V2] = { smca_psp2_mce_desc, ARRAY_SIZE(smca_psp2_mce_desc)},
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[SMCA_SMU] = { smca_smu_mce_desc, ARRAY_SIZE(smca_smu_mce_desc) },
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+ [SMCA_SMU_V2] = { smca_smu2_mce_desc, ARRAY_SIZE(smca_smu2_mce_desc)},
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+ [SMCA_MP5] = { smca_mp5_mce_desc, ARRAY_SIZE(smca_mp5_mce_desc) },
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+ [SMCA_NBIO] = { smca_nbio_mce_desc, ARRAY_SIZE(smca_nbio_mce_desc)},
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+ [SMCA_PCIE] = { smca_pcie_mce_desc, ARRAY_SIZE(smca_pcie_mce_desc)},
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};
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struct smca_hwid {
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@@ -235,6 +329,7 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
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/* Data Fabric MCA types */
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{ SMCA_CS, 0x0000002E },
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+ { SMCA_CS_V2, 0x0002002E },
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{ SMCA_PIE, 0x0001002E },
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/* Unified Memory Controller MCA type */
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@@ -245,9 +340,20 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
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/* Platform Security Processor MCA type */
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{ SMCA_PSP, 0x000000FF },
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+ { SMCA_PSP_V2, 0x000100FF },
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/* System Management Unit MCA type */
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{ SMCA_SMU, 0x00000001 },
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+ { SMCA_SMU_V2, 0x00010001 },
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+
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+ /* Microprocessor 5 Unit MCA type */
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+ { SMCA_MP5, 0x00020001 },
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+
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+ /* Northbridge IO Unit MCA type */
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+ { SMCA_NBIO, 0x00000018 },
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+
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+ /* PCI Express Unit MCA type */
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+ { SMCA_PCIE, 0x00000046 },
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};
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struct smca_bank_name {
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@@ -264,11 +370,17 @@ static struct smca_bank_name smca_names[] = {
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[SMCA_FP] = { "Floating Point Unit" },
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[SMCA_L3_CACHE] = { "L3 Cache" },
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[SMCA_CS] = { "Coherent Slave" },
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+ [SMCA_CS_V2] = { "Coherent Slave" },
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[SMCA_PIE] = { "Power, Interrupts, etc." },
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[SMCA_UMC] = { "Unified Memory Controller" },
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[SMCA_PB] = { "Parameter Block" },
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[SMCA_PSP] = { "Platform Security Processor" },
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+ [SMCA_PSP_V2] = { "Platform Security Processor" },
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[SMCA_SMU] = { "System Management Unit" },
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+ [SMCA_SMU_V2] = { "System Management Unit" },
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+ [SMCA_MP5] = { "Microprocessor 5 Unit" },
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+ [SMCA_NBIO] = { "Northbridge IO Unit" },
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+ [SMCA_PCIE] = { "PCI Express Unit" },
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};
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static void amd_decode_errcode(struct mce_event *e)
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