113 lines
4.0 KiB
Diff
113 lines
4.0 KiB
Diff
From 3ba6092159b6e3b25505af2a49c0f6ac99043db9 Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:28 -0800
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Subject: [PATCH 06/24] x86: Add AMX XTILECFG and XTILEDATA components
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RH-Author: Paul Lai <plai@redhat.com>
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RH-MergeRequest: 176: Enable KVM AMX support
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RH-Commit: [6/13] 95229f87b4494631d57232f374a174f7bc95843a
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RH-Bugzilla: 1916415
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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The AMX TILECFG register and the TMMx tile data registers are
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saved/restored via XSAVE, respectively in state component 17
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(64 bytes) and state component 18 (8192 bytes).
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Add AMX feature bits to x86_ext_save_areas array to set
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up AMX components. Add structs that define the layout of
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AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the
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structs sizes.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-3-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 1f16764f7d4515bfd5e4ae0aae814fa280a7d0c8)
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Signed-off-by: Paul Lai <plai@redhat.com>
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---
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target/i386/cpu.c | 8 ++++++++
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target/i386/cpu.h | 18 +++++++++++++++++-
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2 files changed, 25 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index f44fad3a2a..0453c27c9d 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1401,6 +1401,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
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[XSTATE_PKRU_BIT] =
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{ .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
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.size = sizeof(XSavePKRU) },
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+ [XSTATE_XTILE_CFG_BIT] = {
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+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
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+ .size = sizeof(XSaveXTILECFG),
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+ },
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+ [XSTATE_XTILE_DATA_BIT] = {
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+ .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE,
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+ .size = sizeof(XSaveXTILEDATA)
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+ },
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};
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static uint32_t xsave_area_size(uint64_t mask)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 5d9702a991..e1dd8b9555 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -537,6 +537,8 @@ typedef enum X86Seg {
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#define XSTATE_ZMM_Hi256_BIT 6
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#define XSTATE_Hi16_ZMM_BIT 7
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#define XSTATE_PKRU_BIT 9
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+#define XSTATE_XTILE_CFG_BIT 17
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+#define XSTATE_XTILE_DATA_BIT 18
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#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
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#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
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@@ -845,6 +847,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
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/* AVX512_FP16 instruction */
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#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
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+/* AMX tile (two-dimensional register) */
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+#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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@@ -1348,6 +1352,16 @@ typedef struct XSavePKRU {
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uint32_t padding;
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} XSavePKRU;
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+/* Ext. save area 17: AMX XTILECFG state */
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+typedef struct XSaveXTILECFG {
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+ uint8_t xtilecfg[64];
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+} XSaveXTILECFG;
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+
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+/* Ext. save area 18: AMX XTILEDATA state */
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+typedef struct XSaveXTILEDATA {
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+ uint8_t xtiledata[8][1024];
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+} XSaveXTILEDATA;
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+
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QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
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QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
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QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
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@@ -1355,6 +1369,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
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QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
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QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
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QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
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+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) != 0x40);
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+QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) != 0x2000);
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typedef struct ExtSaveArea {
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uint32_t feature, bits;
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@@ -1362,7 +1378,7 @@ typedef struct ExtSaveArea {
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uint32_t ecx;
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} ExtSaveArea;
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-#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1)
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+#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
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extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT];
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--
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2.35.3
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