57 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
			
		
		
	
	
			57 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| From a246db2fbd892b572fced12da843628f1aab8cd2 Mon Sep 17 00:00:00 2001
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| From: Tao Su <tao1.su@linux.intel.com>
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| Date: Thu, 31 Oct 2024 16:52:32 +0800
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| Subject: [PATCH 36/38] target/i386: Add AVX512 state when AVX10 is supported
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| 
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| RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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| RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets
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| RH-Jira: RHEL-30315 RHEL-45110
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| RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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| RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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| RH-Commit: [7/9] 6f791fae9a3255140795b709435b25159226becf (bonzini/rhel-qemu-kvm)
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| 
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| AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register
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| are identical to AVX512 state regardless of the supported vector lengths.
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| 
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| Given that some E-cores will support AVX10 but not support AVX512, add
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| AVX512 state components to guest when AVX10 is enabled.
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| 
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| Based on a patch by Tao Su <tao1.su@linux.intel.com>
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| 
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| Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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| Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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| Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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| Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1.su@linux.intel.com
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| Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| (cherry picked from commit 0d7475be3b402c25d74c5a4573cbeb733c8f3559)
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| Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| ---
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|  target/i386/cpu.c | 10 +++++++++-
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|  1 file changed, 9 insertions(+), 1 deletion(-)
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| 
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| diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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| index a740429fdd..ddec461dd4 100644
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| --- a/target/i386/cpu.c
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| +++ b/target/i386/cpu.c
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| @@ -7140,7 +7140,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
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|          return false;
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|      }
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|  
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| -    return (env->features[esa->feature] & esa->bits);
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| +    if (env->features[esa->feature] & esa->bits) {
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| +        return true;
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| +    }
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| +    if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F
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| +        && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) {
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| +        return true;
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| +    }
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| +
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| +    return false;
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|  }
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|  
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|  static void x86_cpu_reset_hold(Object *obj, ResetType type)
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| -- 
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| 2.39.3
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| 
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