83 lines
3.2 KiB
Diff
83 lines
3.2 KiB
Diff
From c24fcdf0712ef81ec25ca3a4a1144cca18303fbe Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Thu, 29 Jul 2021 07:42:19 -0400
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Subject: [PATCH 13/39] i386/cpu: Expose AVX_VNNI instruction to guest
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RH-Author: Miroslav Rezanina <mrezanin@redhat.com>
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RH-MergeRequest: 32: Synchronize with RHEL-AV 8.5 release 27 to RHEL 9
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RH-Commit: [5/15] 56381e35a1dc06af7d457d1fe61b1c108dd25d06 (mrezanin/centos-src-qemu-kvm)
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RH-Bugzilla: 1957194
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RH-Acked-by: Stefano Garzarella <sgarzare@redhat.com>
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RH-Acked-by: Kevin Wolf <kwolf@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Andrew Jones <drjones@redhat.com>
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Expose AVX (VEX-encoded) versions of the Vector Neural Network
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Instructions to guest.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EAX[bit 4] AVX_VNNI
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The following instructions are available when this feature is
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present in the guest.
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1. VPDPBUS: Multiply and Add Unsigned and Signed Bytes
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2. VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation
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3. VPDPWSSD: Multiply and Add Signed Word Integers
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4. VPDPWSSDS: Multiply and Add Signed Integers with Saturation
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As for the kvm related code, please reference Linux commit id 1085a6b585d7.
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The release document ref below link:
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https://software.intel.com/content/www/us/en/develop/download/\
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intel-architecture-instruction-set-extensions-programming-reference.html
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20210407015609.22936-1-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit c1826ea6a052084f2e6a0bae9dd5932a727df039)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target/i386/cpu.c | 4 ++--
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target/i386/cpu.h | 2 ++
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2 files changed, 4 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index da47c3e50e..0de2932c79 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -996,7 +996,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, NULL, NULL,
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- NULL, "avx512-bf16", NULL, NULL,
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+ "avx-vnni", "avx512-bf16", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@@ -3284,7 +3284,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
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MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
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.features[FEAT_7_1_EAX] =
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- CPUID_7_1_EAX_AVX512_BF16,
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+ CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
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/* XSAVES is added in version 2 */
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 570f916878..edc8984448 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -804,6 +804,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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/* Speculative Store Bypass Disable */
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
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+/* AVX VNNI Instruction */
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+#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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/* AVX512 BFloat16 Instruction */
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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--
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2.27.0
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