48e88e8e19
- kvm-hw-virtio-virtio-iommu-Migrate-to-3-phase-reset.patch [RHEL-7188] - kvm-hw-i386-intel-iommu-Migrate-to-3-phase-reset.patch [RHEL-7188] - kvm-hw-arm-smmuv3-Move-reset-to-exit-phase.patch [RHEL-7188] - kvm-hw-vfio-common-Add-a-trace-point-in-vfio_reset_handl.patch [RHEL-7188] - kvm-docs-devel-reset-Document-reset-expectations-for-DMA.patch [RHEL-7188] - kvm-qga-implement-a-guest-get-load-command.patch [RHEL-69622] - kvm-migration-Fix-UAF-for-incoming-migration-on-Migratio.patch [RHEL-69775] - kvm-scripts-improve-error-from-qemu-trace-stap-on-missin.patch [RHEL-47340] - kvm-Recommend-systemtap-client-from-qemu-tools.patch [RHEL-47340] - Resolves: RHEL-7188 ([intel iommu][PF] DMAR: DRHD: handling fault status reg) - Resolves: RHEL-69622 ([qemu-guest-agent][RFE] Report CPU load average) - Resolves: RHEL-69775 (Guest crashed on the target host when the migration was canceled) - Resolves: RHEL-47340 ([Qemu RHEL-9] qemu-trace-stap should handle lack of stap more gracefully)
124 lines
4.7 KiB
Diff
124 lines
4.7 KiB
Diff
From a3dfbe30e930c8d794057e45fffd91a9b0e6afd0 Mon Sep 17 00:00:00 2001
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From: Eric Auger <eric.auger@redhat.com>
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Date: Tue, 18 Feb 2025 19:25:33 +0100
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Subject: [PATCH 3/9] hw/arm/smmuv3: Move reset to exit phase
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Eric Auger <eric.auger@redhat.com>
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RH-MergeRequest: 341: Fix vIOMMU reset order
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RH-Jira: RHEL-7188
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: Donald Dutile <None>
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RH-Acked-by: Cédric Le Goater <clg@redhat.com>
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RH-Commit: [3/5] e291cb45c32e0fab49b200c275553bbe76b97264 (eauger1/centos-qemu-kvm)
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Currently the iommu may be reset before the devices
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it protects. For example this happens with virtio-scsi-pci.
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when system_reset is issued from qmp monitor: spurious
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"virtio: zero sized buffers are not allowed" warnings can
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be observed. This happens because outstanding DMA requests
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are still happening while the SMMU gets reset.
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This can also happen with VFIO devices. In that case
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spurious DMA translation faults can be observed on host.
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Make sure the SMMU is reset in the 'exit' phase after
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all DMA capable devices have been reset during the 'enter'
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or 'hold' phase.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
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Message-Id: <20250218182737.76722-4-eric.auger@redhat.com>
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Reviewed-by: Peter Xu <peterx@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit e39e3f8b8dea856f141e9945167d2b18021ef445)
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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---
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hw/arm/smmu-common.c | 9 +++++++--
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hw/arm/smmuv3.c | 14 ++++++++++----
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hw/arm/trace-events | 1 +
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3 files changed, 18 insertions(+), 6 deletions(-)
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diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
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index 3f82728758..f4210fcbc1 100644
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--- a/hw/arm/smmu-common.c
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+++ b/hw/arm/smmu-common.c
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@@ -924,7 +924,12 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
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}
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}
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-static void smmu_base_reset_hold(Object *obj, ResetType type)
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+/*
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+ * Make sure the IOMMU is reset in 'exit' phase after
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+ * all outstanding DMA requests have been quiesced during
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+ * the 'enter' or 'hold' reset phases
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+ */
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+static void smmu_base_reset_exit(Object *obj, ResetType type)
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{
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SMMUState *s = ARM_SMMU(obj);
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@@ -950,7 +955,7 @@ static void smmu_base_class_init(ObjectClass *klass, void *data)
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device_class_set_props(dc, smmu_dev_properties);
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device_class_set_parent_realize(dc, smmu_base_realize,
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&sbc->parent_realize);
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- rc->phases.hold = smmu_base_reset_hold;
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+ rc->phases.exit = smmu_base_reset_exit;
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}
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static const TypeInfo smmu_base_info = {
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index 3971976389..2e90570915 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -1870,13 +1870,19 @@ static void smmu_init_irq(SMMUv3State *s, SysBusDevice *dev)
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}
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}
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-static void smmu_reset_hold(Object *obj, ResetType type)
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+/*
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+ * Make sure the IOMMU is reset in 'exit' phase after
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+ * all outstanding DMA requests have been quiesced during
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+ * the 'enter' or 'hold' reset phases
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+ */
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+static void smmu_reset_exit(Object *obj, ResetType type)
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{
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SMMUv3State *s = ARM_SMMUV3(obj);
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SMMUv3Class *c = ARM_SMMUV3_GET_CLASS(s);
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- if (c->parent_phases.hold) {
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- c->parent_phases.hold(obj, type);
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+ trace_smmu_reset_exit();
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+ if (c->parent_phases.exit) {
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+ c->parent_phases.exit(obj, type);
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}
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smmuv3_init_regs(s);
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@@ -1999,7 +2005,7 @@ static void smmuv3_class_init(ObjectClass *klass, void *data)
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SMMUv3Class *c = ARM_SMMUV3_CLASS(klass);
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dc->vmsd = &vmstate_smmuv3;
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- resettable_class_set_parent_phases(rc, NULL, smmu_reset_hold, NULL,
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+ resettable_class_set_parent_phases(rc, NULL, NULL, smmu_reset_exit,
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&c->parent_phases);
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device_class_set_parent_realize(dc, smmu_realize,
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&c->parent_realize);
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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index be6c8f720b..79ef347e3e 100644
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--- a/hw/arm/trace-events
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+++ b/hw/arm/trace-events
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@@ -56,6 +56,7 @@ smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
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smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
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smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
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smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d"
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+smmu_reset_exit(void) ""
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# strongarm.c
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strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d"
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--
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2.48.1
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