51 lines
2.0 KiB
Diff
51 lines
2.0 KiB
Diff
From a0a63864906cd578c7bc73ea5318282fb393c147 Mon Sep 17 00:00:00 2001
|
|
From: "plai@redhat.com" <plai@redhat.com>
|
|
Date: Wed, 3 Apr 2019 15:54:25 +0100
|
|
Subject: [PATCH 01/10] i386: Add new MSR indices for IA32_PRED_CMD and
|
|
IA32_ARCH_CAPABILITIES
|
|
|
|
RH-Author: plai@redhat.com
|
|
Message-id: <1554306874-28796-2-git-send-email-plai@redhat.com>
|
|
Patchwork-id: 85379
|
|
O-Subject: [RHEL8.1 qemu-kvm PATCH resend 01/10] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
|
|
Bugzilla: 1561761
|
|
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
|
|
RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
|
|
|
From: Robert Hoo <robert.hu@linux.intel.com>
|
|
|
|
IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
|
|
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
|
|
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
|
|
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
|
|
|
|
https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
|
|
|
|
Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
|
|
Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
|
|
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
(cherry picked from commit 8c80c99fcceabd0708a5a83f08577e778c9419f5)
|
|
Signed-off-by: Paul Lai <plai@redhat.com>
|
|
Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
|
|
---
|
|
target/i386/cpu.h | 2 ++
|
|
1 file changed, 2 insertions(+)
|
|
|
|
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
|
index fb6caf4..1dc565c 100644
|
|
--- a/target/i386/cpu.h
|
|
+++ b/target/i386/cpu.h
|
|
@@ -352,6 +352,8 @@ typedef enum X86Seg {
|
|
#define MSR_TSC_ADJUST 0x0000003b
|
|
#define MSR_IA32_SPEC_CTRL 0x48
|
|
#define MSR_VIRT_SSBD 0xc001011f
|
|
+#define MSR_IA32_PRED_CMD 0x49
|
|
+#define MSR_IA32_ARCH_CAPABILITIES 0x10a
|
|
#define MSR_IA32_TSCDEADLINE 0x6e0
|
|
|
|
#define FEATURE_CONTROL_LOCKED (1<<0)
|
|
--
|
|
1.8.3.1
|
|
|