123 lines
4.1 KiB
Diff
123 lines
4.1 KiB
Diff
From 5be7728369a8f109a86b2d5aea89c6dc4014c559 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 18 Jul 2025 18:03:45 +0200
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Subject: [PATCH 023/115] target/i386: Remove AccelCPUClass::cpu_class_init
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need
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 391: TDX support, including attestation and device assignment
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RH-Jira: RHEL-15710 RHEL-20798 RHEL-49728
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RH-Acked-by: Yash Mankad <None>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: David Hildenbrand <david@redhat.com>
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RH-Commit: [23/115] a327127b0c6a96c8198420732006770480b18e69 (bonzini/rhel-qemu-kvm)
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Expose x86_tcg_ops symbol, then directly set it as
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CPUClass::tcg_ops in TYPE_X86_CPU's class_init(),
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using CONFIG_TCG #ifdef'ry. No need for the
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AccelCPUClass::cpu_class_init() handler anymore.
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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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Message-ID: <20250405161320.76854-3-philmd@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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(cherry picked from commit a522b04bb9cf67789116ad7a6165946d4b214bac)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Conflicts: missing one member of x86_tcg_ops
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---
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target/i386/cpu.c | 4 ++++
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target/i386/tcg/tcg-cpu.c | 14 +-------------
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target/i386/tcg/tcg-cpu.h | 4 ++++
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3 files changed, 9 insertions(+), 13 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 816285facd..4eef3d1dbd 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -42,6 +42,7 @@
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#include "hw/boards.h"
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#include "hw/i386/sgx-epc.h"
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#endif
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+#include "tcg/tcg-cpu.h"
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#include "disas/capstone.h"
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#include "cpu-internal.h"
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@@ -9034,6 +9035,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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#ifndef CONFIG_USER_ONLY
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cc->sysemu_ops = &i386_sysemu_ops;
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#endif /* !CONFIG_USER_ONLY */
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+#ifdef CONFIG_TCG
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+ cc->tcg_ops = &x86_tcg_ops;
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+#endif /* CONFIG_TCG */
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cc->gdb_arch_name = x86_gdb_arch_name;
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#ifdef TARGET_X86_64
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diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
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index cca19cd40e..0160f3f70d 100644
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--- a/target/i386/tcg/tcg-cpu.c
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+++ b/target/i386/tcg/tcg-cpu.c
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@@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
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#include "hw/core/tcg-cpu-ops.h"
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-static const TCGCPUOps x86_tcg_ops = {
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+const TCGCPUOps x86_tcg_ops = {
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.initialize = tcg_x86_init,
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.synchronize_from_tb = x86_cpu_synchronize_from_tb,
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.restore_state_to_opc = x86_restore_state_to_opc,
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@@ -128,17 +128,6 @@ static const TCGCPUOps x86_tcg_ops = {
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#endif /* !CONFIG_USER_ONLY */
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};
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-static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
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-{
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- /* for x86, all cpus use the same set of operations */
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- cc->tcg_ops = &x86_tcg_ops;
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-}
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-
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-static void x86_tcg_cpu_class_init(CPUClass *cc)
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-{
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- cc->init_accel_cpu = x86_tcg_cpu_init_ops;
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-}
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-
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static void x86_tcg_cpu_xsave_init(void)
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{
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#define XO(bit, field) \
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@@ -187,7 +176,6 @@ static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
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acc->cpu_target_realize = tcg_cpu_realizefn;
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#endif /* CONFIG_USER_ONLY */
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- acc->cpu_class_init = x86_tcg_cpu_class_init;
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acc->cpu_instance_init = x86_tcg_cpu_instance_init;
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}
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static const TypeInfo x86_tcg_cpu_accel_type_info = {
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diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
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index 53a8494455..9bbf0cb875 100644
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--- a/target/i386/tcg/tcg-cpu.h
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+++ b/target/i386/tcg/tcg-cpu.h
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@@ -19,6 +19,8 @@
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#ifndef TCG_CPU_H
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#define TCG_CPU_H
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+#include "cpu.h"
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+
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#define XSAVE_FCW_FSW_OFFSET 0x000
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#define XSAVE_FTW_FOP_OFFSET 0x004
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#define XSAVE_CWD_RIP_OFFSET 0x008
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@@ -76,6 +78,8 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFF
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET);
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QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET);
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+extern const TCGCPUOps x86_tcg_ops;
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+
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bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
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#endif /* TCG_CPU_H */
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--
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2.50.1
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