84 lines
3.4 KiB
Diff
84 lines
3.4 KiB
Diff
From 79ac76edecdbbe253ad42385730aac18cdc40bd7 Mon Sep 17 00:00:00 2001
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From: Babu Moger <babu.moger@amd.com>
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Date: Fri, 20 Jun 2025 14:54:53 -0500
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Subject: [PATCH 20/57] target/i386: Add couple of feature bits in
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CPUID_Fn80000021_EAX
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RH-Author: John Allen <None>
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RH-MergeRequest: 378: Update EPYC Models and Feature Bits
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RH-Jira: RHEL-52649
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [6/8] c6507eb24fcef271fdd6a234d2c255ef38c4e691 (johnalle/qemu-kvm-fork)
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Add CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
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MSR_KERNEL_GS_BASE is non-serializing amd PREFETCHI that the
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cates
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support for IC prefetch.
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CPUID_Fn80000021_EAX
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Bit Feature description
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20 Indicates support for IC prefetch.
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1 FsGsKernelGsBaseNonSerializing.
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WRMSR to FS_BASE, GS_BASE and KernelGSbase are
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serializing.
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Link: https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/programmer-references/57238.zip
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Link: https://lore.kernel.org/r/a5f6283a59579b09ac345b3f21ecb3b3b2d92451.1746734284.git.babu.moger@amd.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit dfd5b456108a75588ab094358ba5754787146d3d)
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JIRA: https://issues.redhat.com/browse/RHEL-52649
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Signed-off-by: John Allen <johnalle@redhat.com>
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---
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target/i386/cpu.c | 4 ++--
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target/i386/cpu.h | 4 ++++
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2 files changed, 6 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 7d48c51767..2218071fca 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1233,12 +1233,12 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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[FEAT_8000_0021_EAX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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- "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
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+ "no-nested-data-bp", "fs-gs-base-ns", "lfence-always-serializing", NULL,
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NULL, NULL, "null-sel-clr-base", NULL,
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"auto-ibrs", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ "prefetchi", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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"ibpb-brtype", "srso-no", "srso-user-kernel-no", NULL,
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},
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index cf92a4972c..e513e5f62d 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -1030,12 +1030,16 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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/* Processor ignores nested data breakpoints */
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#define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0)
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+/* WRMSR to FS_BASE, GS_BASE, or KERNEL_GS_BASE is non-serializing */
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+#define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1)
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/* LFENCE is always serializing */
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#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
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/* Null Selector Clears Base */
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#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
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/* Automatic IBRS */
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#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
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+/* Indicates support for IC prefetch */
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+#define CPUID_8000_0021_EAX_PREFETCHI (1U << 20)
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/* Selective Branch Predictor Barrier */
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#define CPUID_8000_0021_EAX_SBPB (1U << 27)
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/* IBPB includes branch type prediction flushing */
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--
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2.39.3
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