106 lines
4.1 KiB
Diff
106 lines
4.1 KiB
Diff
From 1587da0703e72cca8325a20b709280b8df85d066 Mon Sep 17 00:00:00 2001
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From: Sandipan Das <sandipan.das@amd.com>
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Date: Thu, 24 Oct 2024 17:18:21 -0500
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Subject: [PATCH 16/57] target/i386: Add PerfMonV2 feature bit
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RH-Author: John Allen <None>
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RH-MergeRequest: 378: Update EPYC Models and Feature Bits
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RH-Jira: RHEL-52649
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [2/8] ec365cf4ac558c6c83f7a957e8df937cb6fbfa27 (johnalle/qemu-kvm-fork)
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CPUID leaf 0x80000022, i.e. ExtPerfMonAndDbg, advertises new performance
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monitoring features for AMD processors. Bit 0 of EAX indicates support
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for Performance Monitoring Version 2 (PerfMonV2) features. If found to
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be set during PMU initialization, the EBX bits can be used to determine
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the number of available counters for different PMUs. It also denotes the
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availability of global control and status registers.
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Add the required CPUID feature word and feature bit to allow guests to
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make use of the PerfMonV2 features.
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Signed-off-by: Sandipan Das <sandipan.das@amd.com>
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Link: https://lore.kernel.org/r/a96f00ee2637674c63c61e9fc4dee343ea818053.1729807947.git.babu.moger@amd.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 209b0ac12074341d0093985eb9ad3e7edb252ce5)
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JIRA: https://issues.redhat.com/browse/RHEL-52649
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Signed-off-by: John Allen <johnalle@redhat.com>
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---
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target/i386/cpu.c | 26 ++++++++++++++++++++++++++
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target/i386/cpu.h | 4 ++++
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2 files changed, 30 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 53069a460c..4546369836 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1246,6 +1246,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.tcg_features = 0,
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.unmigratable_flags = 0,
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},
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+ [FEAT_8000_0022_EAX] = {
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+ .type = CPUID_FEATURE_WORD,
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+ .feat_names = {
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+ "perfmon-v2", NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ },
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+ .cpuid = { .eax = 0x80000022, .reg = R_EAX, },
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+ .tcg_features = 0,
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+ .unmigratable_flags = 0,
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+ },
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[FEAT_XSAVE] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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@@ -7096,6 +7112,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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*edx = 0;
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}
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break;
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+ case 0x80000022:
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+ *eax = *ebx = *ecx = *edx = 0;
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+ /* AMD Extended Performance Monitoring and Debug */
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+ if (kvm_enabled() && cpu->enable_pmu &&
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+ (env->features[FEAT_8000_0022_EAX] & CPUID_8000_0022_EAX_PERFMON_V2)) {
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+ *eax |= CPUID_8000_0022_EAX_PERFMON_V2;
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+ *ebx |= kvm_arch_get_supported_cpuid(cs->kvm_state, index, count,
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+ R_EBX) & 0xf;
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+ }
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+ break;
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case 0xC0000000:
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*eax = env->cpuid_xlevel2;
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*ebx = 0;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 9a16239b8e..cf92a4972c 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -638,6 +638,7 @@ typedef enum FeatureWord {
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FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
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FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
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FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
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+ FEAT_8000_0022_EAX, /* CPUID[8000_0022].EAX */
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FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
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@@ -1044,6 +1045,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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/* Not vulnerable to SRSO at the user-kernel boundary */
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#define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30)
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+/* Performance Monitoring Version 2 */
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+#define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0)
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+
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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#define CPUID_XSAVE_XGETBV1 (1U << 2)
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--
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2.39.3
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