100 lines
4.4 KiB
Diff
100 lines
4.4 KiB
Diff
From 9eae8d0c65d59aacbbd65f522c9d829f5f658c59 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 18 Jul 2025 18:21:11 +0200
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Subject: [PATCH 021/115] redhat: target/i386: add CPUID and MSR bits from
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Clearwater Forest
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 391: TDX support, including attestation and device assignment
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RH-Jira: RHEL-15710 RHEL-20798 RHEL-49728
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RH-Acked-by: Yash Mankad <None>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: David Hildenbrand <david@redhat.com>
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RH-Commit: [21/115] 9f8fe79556c5a52cec955596a3ec8691c05fd65d (bonzini/rhel-qemu-kvm)
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They are used by TDX. But do not add the model yet.
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Link: https://lore.kernel.org/r/20250121020650.1899618-4-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(extracted from commit 56e84d898f17606b5d88778726466540af96b234)
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---
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target/i386/cpu.h | 33 +++++++++++++++++++++++++++------
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1 file changed, 27 insertions(+), 6 deletions(-)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index cc42a2c520..ee1a1b6622 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -951,6 +951,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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/* Speculative Store Bypass Disable */
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#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
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+/* SHA512 Instruction */
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+#define CPUID_7_1_EAX_SHA512 (1U << 0)
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+/* SM3 Instruction */
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+#define CPUID_7_1_EAX_SM3 (1U << 1)
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+/* SM4 Instruction */
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+#define CPUID_7_1_EAX_SM4 (1U << 2)
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/* AVX VNNI Instruction */
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#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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/* AVX512 BFloat16 Instruction */
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@@ -963,6 +969,12 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_7_1_EAX_FSRS (1U << 11)
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/* Fast Short REP CMPS/SCAS */
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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+/* Flexible return and event delivery (FRED) */
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+#define CPUID_7_1_EAX_FRED (1U << 17)
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+/* Load into IA32_KERNEL_GS_BASE (LKGS) */
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+#define CPUID_7_1_EAX_LKGS (1U << 18)
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+/* Non-Serializing Write to Model Specific Register (WRMSRNS) */
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+#define CPUID_7_1_EAX_WRMSRNS (1U << 19)
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/* Support Tile Computational Operations on FP16 Numbers */
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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/* Support for VPMADD52[H,L]UQ */
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@@ -976,17 +988,23 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
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/* AMX COMPLEX Instructions */
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#define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
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+/* AVX-VNNI-INT16 Instructions */
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+#define CPUID_7_1_EDX_AVX_VNNI_INT16 (1U << 10)
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/* PREFETCHIT0/1 Instructions */
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#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
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/* Support for Advanced Vector Extensions 10 */
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#define CPUID_7_1_EDX_AVX10 (1U << 19)
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-/* Flexible return and event delivery (FRED) */
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-#define CPUID_7_1_EAX_FRED (1U << 17)
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-/* Load into IA32_KERNEL_GS_BASE (LKGS) */
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-#define CPUID_7_1_EAX_LKGS (1U << 18)
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-/* Non-Serializing Write to Model Specific Register (WRMSRNS) */
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-#define CPUID_7_1_EAX_WRMSRNS (1U << 19)
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+/* Indicate bit 7 of the IA32_SPEC_CTRL MSR is supported */
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+#define CPUID_7_2_EDX_PSFD (1U << 0)
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+/* Indicate bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported */
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+#define CPUID_7_2_EDX_IPRED_CTRL (1U << 1)
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+/* Indicate bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported */
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+#define CPUID_7_2_EDX_RRSBA_CTRL (1U << 2)
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+/* Indicate bit 8 of the IA32_SPEC_CTRL MSR is supported */
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+#define CPUID_7_2_EDX_DDPD_U (1U << 3)
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+/* Indicate bit 10 of the IA32_SPEC_CTRL MSR is supported */
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+#define CPUID_7_2_EDX_BHI_CTRL (1U << 4)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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@@ -1118,7 +1136,10 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
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#define MSR_ARCH_CAP_PSDP_NO (1U << 15)
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#define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
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+#define MSR_ARCH_CAP_BHI_NO (1U << 20)
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#define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
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+#define MSR_ARCH_CAP_GDS_NO (1U << 26)
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+#define MSR_ARCH_CAP_RFDS_NO (1U << 27)
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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--
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2.50.1
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