193 lines
5.6 KiB
Diff
193 lines
5.6 KiB
Diff
From 92f0b5d0c7a841a21cabbc6efc1d7baf0e5a3e0f Mon Sep 17 00:00:00 2001
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From: Bandan Das <bsd@redhat.com>
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Date: Wed, 9 Aug 2023 12:26:12 -0400
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Subject: [PATCH 2/7] target/i386: Add new EPYC CPU versions with updated
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cache_info
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RH-Author: Bandan Das <None>
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RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
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RH-Bugzilla: 2094913
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RH-Acked-by: Wei Huang <None>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [2/7] 71a2fd907636733f86729bc9328600f6f9306eaf (bdas1/qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
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commit d7c72735f618a7ee27ee109d8b1468193734606a
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Author: Michael Roth <michael.roth@amd.com>
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Date: Thu May 4 15:53:07 2023 -0500
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target/i386: Add new EPYC CPU versions with updated cache_info
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Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
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The only difference vs. older models is an updated cache_info with
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the 'complex_indexing' bit unset, since this bit is not currently
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defined for AMD and may cause problems should it be used for
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something else in the future. Setting this bit will also cause
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CPUID validation failures when running SEV-SNP guests.
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Signed-off-by: Michael Roth <michael.roth@amd.com>
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Acked-by: Michael S. Tsirkin <mst@redhat.com>
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Message-Id: <20230504205313.225073-3-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bandan Das <bsd@redhat.com>
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---
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target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 118 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 3558c92ed0..8aa7eb611c 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1707,6 +1707,56 @@ static const CPUCaches epyc_cache_info = {
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},
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};
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+static CPUCaches epyc_v4_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 64 * KiB,
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+ .line_size = 64,
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+ .associativity = 4,
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+ .partitions = 1,
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+ .sets = 256,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 512 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 1024,
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+ .lines_per_tag = 1,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 8 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 8192,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .complex_indexing = false,
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+ },
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+};
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+
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static const CPUCaches epyc_rome_cache_info = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DATA_CACHE,
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@@ -1757,6 +1807,56 @@ static const CPUCaches epyc_rome_cache_info = {
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},
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};
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+static const CPUCaches epyc_rome_v3_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 512 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 1024,
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+ .lines_per_tag = 1,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 16 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 16384,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .complex_indexing = false,
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+ },
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+};
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+
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static const CPUCaches epyc_milan_cache_info = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DATA_CACHE,
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@@ -4112,6 +4212,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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+ {
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+ .version = 4,
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+ .props = (PropValue[]) {
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+ { "model-id",
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+ "AMD EPYC-v4 Processor" },
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+ { /* end of list */ }
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+ },
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+ .cache_info = &epyc_v4_cache_info
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+ },
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{ /* end of list */ }
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}
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},
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@@ -4231,6 +4340,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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+ {
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+ .version = 3,
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+ .props = (PropValue[]) {
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+ { "model-id",
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+ "AMD EPYC-Rome-v3 Processor" },
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+ { /* end of list */ }
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+ },
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+ .cache_info = &epyc_rome_v3_cache_info
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.39.3
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