7f165dc009
- kvm-Revert-i386-Fix-pkg_id-offset-for-EPYC-cpu-models.patch [bz#1873417] - kvm-Revert-target-i386-Enable-new-apic-id-encoding-for-E.patch [bz#1873417] - kvm-Revert-hw-i386-Move-arch_id-decode-inside-x86_cpus_i.patch [bz#1873417] - kvm-Revert-i386-Introduce-use_epyc_apic_id_encoding-in-X.patch [bz#1873417] - kvm-Revert-hw-i386-Introduce-apicid-functions-inside-X86.patch [bz#1873417] - kvm-Revert-target-i386-Cleanup-and-use-the-EPYC-mode-top.patch [bz#1873417] - kvm-Revert-hw-386-Add-EPYC-mode-topology-decoding-functi.patch [bz#1873417] - kvm-nvram-Exit-QEMU-if-NVRAM-cannot-contain-all-prom-env.patch [bz#1867739] - kvm-usb-fix-setup_len-init-CVE-2020-14364.patch [bz#1869715] - kvm-Remove-explicit-glusterfs-api-dependency.patch [bz#1872853] - kvm-disable-virgl.patch [bz#1831271] - Resolves: bz#1831271 (Drop virgil acceleration support and remove virglrenderer dependency) - Resolves: bz#1867739 (-prom-env does not validate input) - Resolves: bz#1869715 (CVE-2020-14364 qemu-kvm: QEMU: usb: out-of-bounds r/w access issue while processing usb packets [rhel-av-8.3.0]) - Resolves: bz#1872853 (move the glusterfs dependency out of qemu-kvm-core to the glusterfs module) - Resolves: bz#1873417 (AMD/NUMA topology - revert 5.1 changes)
289 lines
11 KiB
Diff
289 lines
11 KiB
Diff
From 4236a54d72270d871ff1ed3fd09a2971327077a1 Mon Sep 17 00:00:00 2001
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From: Igor Mammedov <imammedo@redhat.com>
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Date: Fri, 28 Aug 2020 16:23:48 -0400
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Subject: [PATCH 06/11] Revert "target/i386: Cleanup and use the EPYC mode
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topology functions"
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RH-Author: Igor Mammedov <imammedo@redhat.com>
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Message-id: <20200828162349.1616028-7-imammedo@redhat.com>
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Patchwork-id: 98251
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O-Subject: [RHEL-AV 8.3.0 qemu-kvm PATCH 6/7] Revert "target/i386: Cleanup and use the EPYC mode topology functions"
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Bugzilla: 1873417
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1873417
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Brew: http://brewweb.devel.redhat.com/brew/taskinfo?taskID=31005031
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Branch: rhel-av-8.3.0
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Upstream: RHEL only
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Tested: locally
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A regression was introduced since qemu-5.0, when EPYC specific
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APIC ID encoding was introduced. Which leads to migration failing
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with:
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"
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: Unknown savevm section or instance 'apic' 4. Make sure that your current VM setup matches your saved VM setup, including any hotplugged devices
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: load of migration failed: Invalid argument
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"
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when EPYC cpu model and more than 1 numa node is used.
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EPYC specific APIC ID encoding is considered as failed
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experiment and upstream is preparing to revert it as well.
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This reverts commit dd08ef0318e2b61d14bc069590d174913f7f437a.
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Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 161 ++++++++++++++++++++++++++++++++++++----------
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1 file changed, 127 insertions(+), 34 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 5e3d086f05..73fc83e53f 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -338,15 +338,68 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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}
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}
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+/*
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+ * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
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+ * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
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+ * Define the constants to build the cpu topology. Right now, TOPOEXT
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+ * feature is enabled only on EPYC. So, these constants are based on
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+ * EPYC supported configurations. We may need to handle the cases if
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+ * these values change in future.
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+ */
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+/* Maximum core complexes in a node */
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+#define MAX_CCX 2
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+/* Maximum cores in a core complex */
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+#define MAX_CORES_IN_CCX 4
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+/* Maximum cores in a node */
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+#define MAX_CORES_IN_NODE 8
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+/* Maximum nodes in a socket */
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+#define MAX_NODES_PER_SOCKET 4
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+
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+/*
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+ * Figure out the number of nodes required to build this config.
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+ * Max cores in a node is 8
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+ */
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+static int nodes_in_socket(int nr_cores)
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+{
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+ int nodes;
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+
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+ nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
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+
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+ /* Hardware does not support config with 3 nodes, return 4 in that case */
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+ return (nodes == 3) ? 4 : nodes;
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+}
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+
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+/*
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+ * Decide the number of cores in a core complex with the given nr_cores using
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+ * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
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+ * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
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+ * L3 cache is shared across all cores in a core complex. So, this will also
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+ * tell us how many cores are sharing the L3 cache.
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+ */
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+static int cores_in_core_complex(int nr_cores)
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+{
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+ int nodes;
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+
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+ /* Check if we can fit all the cores in one core complex */
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+ if (nr_cores <= MAX_CORES_IN_CCX) {
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+ return nr_cores;
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+ }
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+ /* Get the number of nodes required to build this config */
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+ nodes = nodes_in_socket(nr_cores);
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+
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+ /*
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+ * Divide the cores accros all the core complexes
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+ * Return rounded up value
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+ */
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+ return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
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+}
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+
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/* Encode cache info for CPUID[8000001D] */
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-static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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- X86CPUTopoInfo *topo_info,
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- uint32_t *eax, uint32_t *ebx,
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- uint32_t *ecx, uint32_t *edx)
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+static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
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+ uint32_t *eax, uint32_t *ebx,
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+ uint32_t *ecx, uint32_t *edx)
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{
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uint32_t l3_cores;
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- unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
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-
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assert(cache->size == cache->line_size * cache->associativity *
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cache->partitions * cache->sets);
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@@ -355,13 +408,10 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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/* L3 is shared among multiple cores */
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if (cache->level == 3) {
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- l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
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- topo_info->cores_per_die *
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- topo_info->threads_per_core),
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- nodes);
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- *eax |= (l3_cores - 1) << 14;
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+ l3_cores = cores_in_core_complex(cs->nr_cores);
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+ *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
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} else {
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- *eax |= ((topo_info->threads_per_core - 1) << 14);
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+ *eax |= ((cs->nr_threads - 1) << 14);
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}
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assert(cache->line_size > 0);
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@@ -381,17 +431,55 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
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(cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
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}
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+/* Data structure to hold the configuration info for a given core index */
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+struct core_topology {
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+ /* core complex id of the current core index */
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+ int ccx_id;
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+ /*
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+ * Adjusted core index for this core in the topology
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+ * This can be 0,1,2,3 with max 4 cores in a core complex
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+ */
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+ int core_id;
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+ /* Node id for this core index */
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+ int node_id;
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+ /* Number of nodes in this config */
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+ int num_nodes;
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+};
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+
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+/*
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+ * Build the configuration closely match the EPYC hardware. Using the EPYC
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+ * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
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+ * right now. This could change in future.
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+ * nr_cores : Total number of cores in the config
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+ * core_id : Core index of the current CPU
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+ * topo : Data structure to hold all the config info for this core index
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+ */
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+static void build_core_topology(int nr_cores, int core_id,
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+ struct core_topology *topo)
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+{
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+ int nodes, cores_in_ccx;
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+
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+ /* First get the number of nodes required */
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+ nodes = nodes_in_socket(nr_cores);
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+
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+ cores_in_ccx = cores_in_core_complex(nr_cores);
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+
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+ topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
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+ topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
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+ topo->core_id = core_id % cores_in_ccx;
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+ topo->num_nodes = nodes;
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+}
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+
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/* Encode cache info for CPUID[8000001E] */
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-static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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+static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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- X86CPUTopoIDs topo_ids = {0};
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- unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
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+ struct core_topology topo = {0};
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+ unsigned long nodes;
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int shift;
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- x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
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-
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+ build_core_topology(cs->nr_cores, cpu->core_id, &topo);
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*eax = cpu->apic_id;
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/*
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* CPUID_Fn8000001E_EBX
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@@ -408,8 +496,12 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* 3 Core complex id
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* 1:0 Core id
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*/
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- *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
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- (topo_ids.core_id);
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+ if (cs->nr_threads - 1) {
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+ *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
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+ (topo.ccx_id << 2) | topo.core_id;
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+ } else {
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+ *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
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+ }
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/*
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* CPUID_Fn8000001E_ECX
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* 31:11 Reserved
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@@ -418,8 +510,9 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* 2 Socket id
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* 1:0 Node id
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*/
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- if (nodes <= 4) {
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- *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
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+ if (topo.num_nodes <= 4) {
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+ *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
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+ topo.node_id;
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} else {
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/*
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* Node id fix up. Actual hardware supports up to 4 nodes. But with
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@@ -434,10 +527,10 @@ static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
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* number of nodes. find_last_bit returns last set bit(0 based). Left
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* shift(+1) the socket id to represent all the nodes.
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*/
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- nodes -= 1;
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+ nodes = topo.num_nodes - 1;
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shift = find_last_bit(&nodes, 8);
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- *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
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- topo_ids.node_id;
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+ *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
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+ topo.node_id;
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}
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*edx = 0;
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}
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@@ -5473,7 +5566,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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uint32_t signature[3];
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X86CPUTopoInfo topo_info;
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- topo_info.nodes_per_pkg = env->nr_nodes;
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topo_info.dies_per_pkg = env->nr_dies;
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topo_info.cores_per_die = cs->nr_cores;
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topo_info.threads_per_core = cs->nr_threads;
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@@ -5905,20 +5997,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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}
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switch (count) {
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case 0: /* L1 dcache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 1: /* L1 icache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 2: /* L2 cache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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case 3: /* L3 cache info */
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- encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
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- &topo_info, eax, ebx, ecx, edx);
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+ encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
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+ eax, ebx, ecx, edx);
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break;
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default: /* end of info */
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*eax = *ebx = *ecx = *edx = 0;
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@@ -5927,7 +6019,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0x8000001E:
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assert(cpu->core_id <= 255);
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- encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx);
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+ encode_topo_cpuid8000001e(cs, cpu,
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+ eax, ebx, ecx, edx);
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break;
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case 0xC0000000:
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*eax = env->cpuid_xlevel2;
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--
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2.27.0
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