126 lines
4.6 KiB
Diff
126 lines
4.6 KiB
Diff
From 4009f0bcc8004ce481015d088fe335a16b8d7ce1 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Mon, 17 Feb 2020 16:23:12 +0000
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Subject: [PATCH 2/9] target/i386: add a ucode-rev property
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20200217162316.2464-3-pbonzini@redhat.com>
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Patchwork-id: 93909
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O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 2/6] target/i386: add a ucode-rev property
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Bugzilla: 1791648
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Add the property and plumb it in TCG and HVF (the latter of which
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tried to support returning a constant value but used the wrong MSR).
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Message-Id: <1579544504-3616-3-git-send-email-pbonzini@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 4e45aff398cd1542c2a384a2a3b8600f23337d86)
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 10 ++++++++++
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target/i386/cpu.h | 3 +++
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target/i386/hvf/x86_emu.c | 4 +---
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target/i386/misc_helper.c | 4 ++++
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4 files changed, 18 insertions(+), 3 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 863192c..e505d3e 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -6325,6 +6325,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
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}
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}
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+ if (cpu->ucode_rev == 0) {
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+ /* The default is the same as KVM's. */
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+ if (IS_AMD_CPU(env)) {
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+ cpu->ucode_rev = 0x01000065;
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+ } else {
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+ cpu->ucode_rev = 0x100000000ULL;
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+ }
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+ }
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+
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/* mwait extended info: needed for Core compatibility */
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/* We always wake on interrupt even if host does not have the capability */
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cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
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@@ -7008,6 +7017,7 @@ static Property x86_cpu_properties[] = {
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DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
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DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
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DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
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+ DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
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DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
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DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
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DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index cde2a16..4441061 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -348,6 +348,7 @@ typedef enum X86Seg {
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#define MSR_IA32_SPEC_CTRL 0x48
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#define MSR_VIRT_SSBD 0xc001011f
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#define MSR_IA32_PRED_CMD 0x49
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+#define MSR_IA32_UCODE_REV 0x8b
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#define MSR_IA32_CORE_CAPABILITY 0xcf
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#define MSR_IA32_ARCH_CAPABILITIES 0x10a
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@@ -1621,6 +1622,8 @@ struct X86CPU {
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CPUNegativeOffsetState neg;
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CPUX86State env;
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+ uint64_t ucode_rev;
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+
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uint32_t hyperv_spinlock_attempts;
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char *hyperv_vendor_id;
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bool hyperv_synic_kvm_only;
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diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
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index 3df7672..92ab815 100644
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--- a/target/i386/hvf/x86_emu.c
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+++ b/target/i386/hvf/x86_emu.c
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@@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
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RIP(env) += decode->len;
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}
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-#define MSR_IA32_UCODE_REV 0x00000017
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-
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void simulate_rdmsr(struct CPUState *cpu)
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{
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X86CPU *x86_cpu = X86_CPU(cpu);
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@@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu)
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val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
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break;
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case MSR_IA32_UCODE_REV:
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- val = (0x100000000ULL << 32) | 0x100000000ULL;
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+ val = x86_cpu->ucode_rev;
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break;
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case MSR_EFER:
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val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
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diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
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index 3eff688..aed16fe 100644
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--- a/target/i386/misc_helper.c
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+++ b/target/i386/misc_helper.c
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@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)
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#else
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void helper_wrmsr(CPUX86State *env)
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{
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+ X86CPU *x86_cpu = env_archcpu(env);
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uint64_t val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
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@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)
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env->msr_bndcfgs = val;
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cpu_sync_bndcs_hflags(env);
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break;
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+ case MSR_IA32_UCODE_REV:
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+ val = x86_cpu->ucode_rev;
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+ break;
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default:
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if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
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&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
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--
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1.8.3.1
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