148 lines
4.6 KiB
Diff
148 lines
4.6 KiB
Diff
From dc86ee01fb27b174871ff8be9095ed1a20513772 Mon Sep 17 00:00:00 2001
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From: Babu Moger <babu.moger@amd.com>
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Date: Thu, 8 May 2025 14:58:00 -0500
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Subject: [PATCH 18/57] target/i386: Update EPYC-Rome CPU model for Cache
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property, RAS, SVM feature bits
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RH-Author: John Allen <None>
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RH-MergeRequest: 378: Update EPYC Models and Feature Bits
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RH-Jira: RHEL-52649
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [4/8] f23618215eee3c54d9ba52c5b74f5d574c522649 (johnalle/qemu-kvm-fork)
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Found that some of the cache properties are not set correctly for EPYC models.
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l1d_cache.no_invd_sharing should not be true.
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l1i_cache.no_invd_sharing should not be true.
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L2.self_init should be true.
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L2.inclusive should be true.
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L3.inclusive should not be true.
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L3.no_invd_sharing should be true.
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Fix these cache properties.
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Also add the missing RAS and SVM features bits on AMD EPYC-Rome. The SVM
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feature bits are used in nested guests.
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succor : Software uncorrectable error containment and recovery capability.
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overflow-recov : MCA overflow recovery support.
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lbrv : LBR virtualization
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tsc-scale : MSR based TSC rate control
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vmcb-clean : VMCB clean bits
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flushbyasid : Flush by ASID
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pause-filter : Pause intercept filter
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pfthreshold : PAUSE filter threshold
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v-vmsave-vmload : Virtualized VMLOAD and VMSAVE
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vgif : Virtualized GIF
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Reviewed-by: Maksim Davydov <davydov-max@yandex-team.ru>
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Link: https://lore.kernel.org/r/8265af72057b84c99ac3a02a5487e32759cc69b1.1746734284.git.babu.moger@amd.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 83d940e9700527ff080416ce2fa52ee1f4771d72)
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JIRA: https://issues.redhat.com/browse/RHEL-52649
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Signed-off-by: John Allen <johnalle@redhat.com>
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---
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target/i386/cpu.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 73 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 32c575f63b..a73b5bfca4 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -2328,6 +2328,60 @@ static const CPUCaches epyc_rome_v3_cache_info = {
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},
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};
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+static const CPUCaches epyc_rome_v5_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .share_level = CPU_TOPO_LEVEL_CORE,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .share_level = CPU_TOPO_LEVEL_CORE,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 512 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 1024,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .share_level = CPU_TOPO_LEVEL_CORE,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 16 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 16384,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .no_invd_sharing = true,
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+ .complex_indexing = false,
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+ .share_level = CPU_TOPO_LEVEL_DIE,
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+ },
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+};
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+
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static const CPUCaches epyc_milan_cache_info = {
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.l1d_cache = &(CPUCacheInfo) {
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.type = DATA_CACHE,
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@@ -5270,6 +5324,25 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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},
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},
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+ {
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+ .version = 5,
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+ .props = (PropValue[]) {
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+ { "overflow-recov", "on" },
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+ { "succor", "on" },
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+ { "lbrv", "on" },
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+ { "tsc-scale", "on" },
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+ { "vmcb-clean", "on" },
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+ { "flushbyasid", "on" },
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+ { "pause-filter", "on" },
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+ { "pfthreshold", "on" },
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+ { "v-vmsave-vmload", "on" },
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+ { "vgif", "on" },
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+ { "model-id",
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+ "AMD EPYC-Rome-v5 Processor" },
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+ { /* end of list */ }
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+ },
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+ .cache_info = &epyc_rome_v5_cache_info
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.39.3
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