From 1895c3aa9eb0037eb06745ef499eb7476bebd554 Mon Sep 17 00:00:00 2001 From: Tao Su Date: Thu, 31 Oct 2024 16:52:33 +0800 Subject: [PATCH 08/11] target/i386: Introduce GraniteRapids-v2 model RH-Author: Paolo Bonzini RH-MergeRequest: 281: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets. RH-Jira: RHEL-30316 RHEL-45111 RH-Acked-by: Vitaly Kuznetsov RH-Acked-by: Miroslav Rezanina RH-Commit: [8/9] 5b684731a1d2c2687515eb984398c9dc5bc3fc23 (bonzini/rhel-qemu-kvm) Update GraniteRapids CPU model to add AVX10 and the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b). Tested-by: Xuelian Guo Signed-off-by: Tao Su Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1.su@linux.intel.com Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241031085233.425388-9-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini (cherry picked from commit 1a519388a882fbb352e49cbebb0ed8f62d05842d) Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5042cbaa0e..ad368252d8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4393,6 +4393,23 @@ static const X86CPUDefinition builtin_x86_defs[] = { .model_id = "Intel Xeon Processor (GraniteRapids)", .versions = (X86CPUVersionDefinition[]) { { .version = 1 }, + { + .version = 2, + .props = (PropValue[]) { + { "ss", "on" }, + { "tsc-adjust", "on" }, + { "cldemote", "on" }, + { "movdiri", "on" }, + { "movdir64b", "on" }, + { "avx10", "on" }, + { "avx10-128", "on" }, + { "avx10-256", "on" }, + { "avx10-512", "on" }, + { "avx10-version", "1" }, + { "stepping", "1" }, + { /* end of list */ } + } + }, { /* end of list */ }, }, }, -- 2.48.0