From 04387fbe913b26a3819d711ea91b99be6faa8616 Mon Sep 17 00:00:00 2001 From: "plai@redhat.com" Date: Tue, 26 Nov 2019 19:36:50 +0000 Subject: [PATCH 06/11] x86/cpu: Enable MOVDIR64B cpu feature RH-Author: plai@redhat.com Message-id: <1574797015-32564-3-git-send-email-plai@redhat.com> Patchwork-id: 92691 O-Subject: [RHEL8.2 qemu-kvm PATCH 2/7] x86/cpu: Enable MOVDIR64B cpu feature Bugzilla: 1634827 RH-Acked-by: Eduardo Habkost RH-Acked-by: Michael S. Tsirkin RH-Acked-by: Igor Mammedov From: Liu Jingqi MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity. Direct store is implemented by using write combining (WC) for writing data directly into memory without caching the data. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B The release document ref below link: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Cc: Xu Tao Signed-off-by: Liu Jingqi Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com> Signed-off-by: Eduardo Habkost (cherry picked from commit 1c65775ffc2dbd276a8bffe592feba0e186a151c) Signed-off-by: Paul Lai Resolved Conflicts: target/i386/cpu.c Signed-off-by: Danilo C. L. de Paula --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f2ab558..307b629 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1022,7 +1022,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, NULL, "cldemote", NULL, "movdiri", - NULL, NULL, NULL, NULL, + "movdir64b", NULL, NULL, NULL, }, .cpuid = { .eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6ba0b1e..d33fa8d 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -719,6 +719,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_RDPID (1U << 22) #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */ +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ -- 1.8.3.1