From f2578175ee0e0b0a7a99118e5fdf23ec0ad29ff4 Mon Sep 17 00:00:00 2001 From: Vitaly Kuznetsov Date: Wed, 16 Mar 2022 09:48:04 +0100 Subject: [PATCH 02/12] i386: Add Icelake-Server-v6 CPU model with 5-level EPT support RH-Author: Vitaly Kuznetsov RH-MergeRequest: 127: i386: Add Icelake-Server-v6 CPU model with 5-level EPT support RH-Commit: [2/2] 72eaf5608490f5b1fb94b6decb95d4092c57dd85 RH-Bugzilla: 2056986 RH-Acked-by: Paolo Bonzini RH-Acked-by: Igor Mammedov RH-Acked-by: Cornelia Huck Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2056986 Brew: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=43862707 commit 12cab535db6440af41ed8dfefe908a594321b6ce Author: Vitaly Kuznetsov Date: Mon Feb 21 15:53:15 2022 +0100 i386: Add Icelake-Server-v6 CPU model with 5-level EPT support Windows 11 with WSL2 enabled (Hyper-V) fails to boot with Icelake-Server {-v5} CPU model but boots well with '-cpu host'. Apparently, it expects 5-level paging and 5-level EPT support to come in pair but QEMU's Icelake-Server CPU model lacks the later. Introduce 'Icelake-Server-v6' CPU model with 'vmx-page-walk-5' enabled by default. Signed-off-by: Vitaly Kuznetsov Message-Id: <20220221145316.576138-1-vkuznets@redhat.com> Signed-off-by: Paolo Bonzini Signed-off-by: Vitaly Kuznetsov --- target/i386/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index aa9e636800..6e25d13339 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3505,6 +3505,14 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ } }, }, + { + .version = 6, + .note = "5-level EPT", + .props = (PropValue[]) { + { "vmx-page-walk-5", "on" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, -- 2.27.0