From 4f9094b11eb831317879d9c6108f6f706546fea5 Mon Sep 17 00:00:00 2001 From: Miroslav Rezanina Date: Fri, 19 Oct 2018 13:27:13 +0200 Subject: Add ppc64 machine types Adding changes to add RHEL machine types for ppc64 architecture. Signed-off-by: Miroslav Rezanina --- hw/ppc/spapr.c | 252 ++++++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/spapr_cpu_core.c | 13 +++ include/hw/ppc/spapr.h | 1 + target/ppc/compat.c | 13 ++- target/ppc/cpu.h | 1 + 5 files changed, 279 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 7afd1a1..76a4e83 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3906,6 +3906,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; spapr_caps_add_properties(smc, &error_abort); smc->irq = &spapr_irq_xics; + smc->has_power9_support = true; } static const TypeInfo spapr_machine_info = { @@ -3956,6 +3957,7 @@ static const TypeInfo spapr_machine_info = { } \ type_init(spapr_machine_register_##suffix) +#if 0 /* Disabled for Red Hat Enterprise Linux */ /* * pseries-3.1 */ @@ -4169,6 +4171,7 @@ DEFINE_SPAPR_MACHINE(2_8, "2.8", false); .property = "pre-2.8-migration", \ .value = "on", \ }, +#endif static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, @@ -4219,6 +4222,7 @@ static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, */ } +#if 0 /* Disabled for Red Hat Enterprise Linux */ static void spapr_machine_2_7_instance_options(MachineState *machine) { sPAPRMachineState *spapr = SPAPR_MACHINE(machine); @@ -4378,6 +4382,254 @@ static void spapr_machine_2_1_class_options(MachineClass *mc) SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); } DEFINE_SPAPR_MACHINE(2_1, "2.1", false); +#endif + +/* + * pseries-rhel7.6.0 + */ + +static void spapr_machine_rhel760_instance_options(MachineState *machine) +{ +} + +static void spapr_machine_rhel760_class_options(MachineClass *mc) +{ + /* Defaults for the latest behaviour inherited from the base class */ +} + +DEFINE_SPAPR_MACHINE(rhel760, "rhel7.6.0", true); + +/* + * pseries-rhel7.6.0-sxxm + * + * pseries-rhel7.6.0 with speculative execution exploit mitigations enabled by default + */ +static void spapr_machine_rhel760sxxm_instance_options(MachineState *machine) +{ + spapr_machine_rhel760_instance_options(machine); +} + +static void spapr_machine_rhel760sxxm_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel760_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel760sxxm, "rhel7.6.0-sxxm", false); + +/* + * pseries-rhel7.5.0 + * like SPAPR_COMPAT_2_11 and SPAPR_COMPAT_2_10 + * SPAPR_CAP_HTM already enabled in 7.4 + * + */ +#define SPAPR_COMPAT_RHEL7_5 \ + HW_COMPAT_RHEL7_5 \ + +static void spapr_machine_rhel750_instance_options(MachineState *machine) +{ + spapr_machine_rhel760_instance_options(machine); +} + +static void spapr_machine_rhel750_class_options(MachineClass *mc) +{ + spapr_machine_rhel760_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_RHEL7_5); +} + +DEFINE_SPAPR_MACHINE(rhel750, "rhel7.5.0", false); + +/* + * pseries-rhel7.5.0-sxxm + * + * pseries-rhel7.5.0 with speculative execution exploit mitigations enabled by default + */ +static void spapr_machine_rhel750sxxm_instance_options(MachineState *machine) +{ + spapr_machine_rhel750_instance_options(machine); +} + +static void spapr_machine_rhel750sxxm_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel750_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel750sxxm, "rhel7.5.0-sxxm", false); + +/* + * pseries-rhel7.4.0 + * like SPAPR_COMPAT_2_9 + */ + +#define SPAPR_COMPAT_RHEL7_4 \ + HW_COMPAT_RHEL7_4 \ + { \ + .driver = TYPE_POWERPC_CPU, \ + .property = "pre-2.10-migration", \ + .value = "on", \ + }, \ + +static void spapr_machine_rhel740_instance_options(MachineState *machine) +{ + spapr_machine_rhel750_instance_options(machine); +} + +static void spapr_machine_rhel740_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel750_class_options(mc); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_RHEL7_4); + mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; + smc->has_power9_support = false; + smc->pre_2_10_has_unused_icps = true; + smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; + smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; +} + +DEFINE_SPAPR_MACHINE(rhel740, "rhel7.4.0", false); + +/* + * pseries-rhel7.4.0-sxxm + * + * pseries-rhel7.4.0 with speculative execution exploit mitigations enabled by default + */ +static void spapr_machine_rhel740sxxm_instance_options(MachineState *machine) +{ + spapr_machine_rhel740_instance_options(machine); +} + +static void spapr_machine_rhel740sxxm_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel740_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel740sxxm, "rhel7.4.0-sxxm", false); + +/* + * pseries-rhel7.3.0 + * like SPAPR_COMPAT_2_6/_2_7/_2_8 but "ddw" has been backported to RHEL7_3 + */ +#define SPAPR_COMPAT_RHEL7_3 \ + HW_COMPAT_RHEL7_3 \ + { \ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ + .property = "mem_win_size", \ + .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ + }, \ + { \ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ + .property = "mem64_win_size", \ + .value = "0", \ + }, \ + { \ + .driver = TYPE_POWERPC_CPU, \ + .property = "pre-2.8-migration", \ + .value = "on", \ + }, \ + { \ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ + .property = "pre-2.8-migration", \ + .value = "on", \ + }, \ + { \ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ + .property = "pcie-extended-configuration-space",\ + .value = "off", \ + }, + +static void spapr_machine_rhel730_instance_options(MachineState *machine) +{ + sPAPRMachineState *spapr = SPAPR_MACHINE(machine); + + spapr_machine_rhel740_instance_options(machine); + spapr->use_hotplug_event_source = false; +} + +static void spapr_machine_rhel730_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel740_class_options(mc); + mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_RHEL7_3); + smc->phb_placement = phb_placement_2_7; +} + +DEFINE_SPAPR_MACHINE(rhel730, "rhel7.3.0", false); + +/* + * pseries-rhel7.3.0-sxxm + * + * pseries-rhel7.3.0 with speculative execution exploit mitigations enabled by default + */ +static void spapr_machine_rhel730sxxm_instance_options(MachineState *machine) +{ + spapr_machine_rhel730_instance_options(machine); +} + +static void spapr_machine_rhel730sxxm_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel730_class_options(mc); + smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; + smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; +} + +DEFINE_SPAPR_MACHINE(rhel730sxxm, "rhel7.3.0-sxxm", false); + +/* + * pseries-rhel7.2.0 + */ +/* Should be like SPAPR_COMPAT_2_5 + 2_4 + 2_3, but "dynamic-reconfiguration" + * has been backported to RHEL7_2 so we don't need it here. + */ + +#define SPAPR_COMPAT_RHEL7_2 \ + HW_COMPAT_RHEL7_2 \ + { \ + .driver = "spapr-vlan", \ + .property = "use-rx-buffer-pools", \ + .value = "off", \ + },{ \ + .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ + .property = "ddw",\ + .value = stringify(off),\ + }, + + +static void spapr_machine_rhel720_instance_options(MachineState *machine) +{ + spapr_machine_rhel730_instance_options(machine); +} + +static void spapr_machine_rhel720_class_options(MachineClass *mc) +{ + sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); + + spapr_machine_rhel730_class_options(mc); + smc->use_ohci_by_default = true; + mc->has_hotpluggable_cpus = NULL; + SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_RHEL7_2); +} + +DEFINE_SPAPR_MACHINE(rhel720, "rhel7.2.0", false); static void spapr_machine_register_types(void) { diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index 63a7bb6..fcf6174 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -22,6 +22,7 @@ #include "sysemu/numa.h" #include "sysemu/hw_accel.h" #include "qemu/error-report.h" +#include "cpu-models.h" static void spapr_cpu_reset(void *opaque) { @@ -218,6 +219,7 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, CPUPPCState *env = &cpu->env; CPUState *cs = CPU(cpu); Error *local_err = NULL; + sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); if (local_err) { @@ -230,6 +232,17 @@ static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr, cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr)); kvmppc_set_papr(cpu); + if (!smc->has_power9_support && + (((spapr->max_compat_pvr && + ppc_compat_cmp(spapr->max_compat_pvr, + CPU_POWERPC_LOGICAL_3_00) >= 0)) || + (!spapr->max_compat_pvr && + ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, 0)))) { + error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND, + "POWER9 CPU is not supported by this machine class"); + return; + } + qemu_register_reset(spapr_cpu_reset, cpu); spapr_cpu_reset(cpu); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 6279711..d2370e5 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -106,6 +106,7 @@ struct sPAPRMachineClass { bool pre_2_10_has_unused_icps; bool legacy_irq_allocation; + bool has_power9_support; void (*phb_placement)(sPAPRMachineState *spapr, uint32_t index, uint64_t *buid, hwaddr *pio, hwaddr *mmio32, hwaddr *mmio64, diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 7de4bf3..3e2e353 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -105,8 +105,19 @@ static const CompatInfo *compat_by_pvr(uint32_t pvr) return NULL; } +long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2) +{ + const CompatInfo *compat1 = compat_by_pvr(pvr1); + const CompatInfo *compat2 = compat_by_pvr(pvr2); + + g_assert(compat1); + g_assert(compat2); + + return compat1 - compat2; +} + static bool pcc_compat(PowerPCCPUClass *pcc, uint32_t compat_pvr, - uint32_t min_compat_pvr, uint32_t max_compat_pvr) + uint32_t min_compat_pvr, uint32_t max_compat_pvr) { const CompatInfo *compat = compat_by_pvr(compat_pvr); const CompatInfo *min = compat_by_pvr(min_compat_pvr); diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ab68abe..c559740 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1376,6 +1376,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) /* Compatibility modes */ #if defined(TARGET_PPC64) +long ppc_compat_cmp(uint32_t pvr1, uint32_t pvr2); bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, uint32_t min_compat_pvr, uint32_t max_compat_pvr); bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr, -- 1.8.3.1