From d457fd42e0752855d8370bac1cf3c07cd1fc46a3 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 3 Jul 2024 13:42:49 +0200 Subject: [PATCH 38/38] target/i386: add sha512, sm3, sm4 feature bits RH-Author: Paolo Bonzini RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets RH-Jira: RHEL-30315 RHEL-45110 RH-Acked-by: Vitaly Kuznetsov RH-Acked-by: Miroslav Rezanina RH-Commit: [9/9] 80a6ce9fe3b7225f74a2822ce263d539148cda56 (bonzini/rhel-qemu-kvm) Status: queued for QEMU 10.0 SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by Clearwater Forest processor, add it to QEMU as it does not need any specific enablement. See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/ for reference. Reviewed-by: Tao Su Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e7367cfe82..ff063a9a50 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1114,7 +1114,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { [FEAT_7_1_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { - NULL, NULL, NULL, NULL, + "sha512", "sm3", "sm4", NULL, "avx-vnni", "avx512-bf16", NULL, "cmpccxadd", NULL, NULL, "fzrm", "fsrs", "fsrc", NULL, NULL, NULL, -- 2.39.3