From a246db2fbd892b572fced12da843628f1aab8cd2 Mon Sep 17 00:00:00 2001 From: Tao Su Date: Thu, 31 Oct 2024 16:52:32 +0800 Subject: [PATCH 36/38] target/i386: Add AVX512 state when AVX10 is supported RH-Author: Paolo Bonzini RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets RH-Jira: RHEL-30315 RHEL-45110 RH-Acked-by: Vitaly Kuznetsov RH-Acked-by: Miroslav Rezanina RH-Commit: [7/9] 6f791fae9a3255140795b709435b25159226becf (bonzini/rhel-qemu-kvm) AVX10 state enumeration in CPUID leaf D and enabling in XCR0 register are identical to AVX512 state regardless of the supported vector lengths. Given that some E-cores will support AVX10 but not support AVX512, add AVX512 state components to guest when AVX10 is enabled. Based on a patch by Tao Su Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu Tested-by: Xuelian Guo Signed-off-by: Tao Su Link: https://lore.kernel.org/r/20241031085233.425388-8-tao1.su@linux.intel.com Signed-off-by: Paolo Bonzini (cherry picked from commit 0d7475be3b402c25d74c5a4573cbeb733c8f3559) Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a740429fdd..ddec461dd4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7140,7 +7140,15 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa) return false; } - return (env->features[esa->feature] & esa->bits); + if (env->features[esa->feature] & esa->bits) { + return true; + } + if (esa->feature == FEAT_7_0_EBX && esa->bits == CPUID_7_0_EBX_AVX512F + && (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + return true; + } + + return false; } static void x86_cpu_reset_hold(Object *obj, ResetType type) -- 2.39.3