* Mon Aug 21 2023 Miroslav Rezanina <mrezanin@redhat.com> - 8.0.0-12
- kvm-target-i386-allow-versioned-CPUs-to-specify-new-cach.patch [bz#2094913] - kvm-target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch [bz#2094913] - kvm-target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch [bz#2094913] - kvm-target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch [bz#2094913] - kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch [bz#2094913] - kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch [bz#2094913] - kvm-target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch [bz#2094913] - Resolves: bz#2094913 (Add EPYC-Genoa CPU model in qemu)
This commit is contained in:
Miroslav Rezanina
parent
330a18fc02
commit
a586acaa36
203
kvm-target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch
Normal file
203
kvm-target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch
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@ -0,0 +1,203 @@
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From 03011d00cfb5862edb7394a9b79b269198af5c89 Mon Sep 17 00:00:00 2001
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From: Bandan Das <bsd@redhat.com>
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Date: Wed, 9 Aug 2023 12:48:34 -0400
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Subject: [PATCH 7/7] target/i386: Add EPYC-Genoa model to support Zen 4
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processor series
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RH-Author: Bandan Das <None>
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RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
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RH-Bugzilla: 2094913
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RH-Acked-by: Wei Huang <None>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [7/7] 158091c691169a5d30c7c8005371ee7a0d9fc4ce (bdas1/qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
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commit 166b1741884dd4fd7090b753cd7333868457a29b
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Author: Babu Moger <babu.moger@amd.com>
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Date: Thu May 4 15:53:12 2023 -0500
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target/i386: Add EPYC-Genoa model to support Zen 4 processor series
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Adds the support for AMD EPYC Genoa generation processors. The model
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display for the new processor will be EPYC-Genoa.
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Adds the following new feature bits on top of the feature bits from
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the previous generation EPYC models.
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avx512f : AVX-512 Foundation instruction
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avx512dq : AVX-512 Doubleword & Quadword Instruction
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avx512ifma : AVX-512 Integer Fused Multiply Add instruction
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avx512cd : AVX-512 Conflict Detection instruction
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avx512bw : AVX-512 Byte and Word Instructions
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avx512vl : AVX-512 Vector Length Extension Instructions
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avx512vbmi : AVX-512 Vector Byte Manipulation Instruction
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avx512_vbmi2 : AVX-512 Additional Vector Byte Manipulation Instruction
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gfni : AVX-512 Galois Field New Instructions
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avx512_vnni : AVX-512 Vector Neural Network Instructions
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avx512_bitalg : AVX-512 Bit Algorithms, add bit algorithms Instructions
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avx512_vpopcntdq: AVX-512 AVX-512 Vector Population Count Doubleword and
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Quadword Instructions
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avx512_bf16 : AVX-512 BFLOAT16 instructions
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la57 : 57-bit virtual address support (5-level Page Tables)
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vnmi : Virtual NMI (VNMI) allows the hypervisor to inject the NMI
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into the guest without using Event Injection mechanism
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meaning not required to track the guest NMI and intercepting
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the IRET.
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auto-ibrs : The AMD Zen4 core supports a new feature called Automatic IBRS.
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It is a "set-and-forget" feature that means that, unlike e.g.,
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s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
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resources automatically across CPL transitions.
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Message-Id: <20230504205313.225073-8-babu.moger@amd.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Bandan Das <bsd@redhat.com>
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---
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target/i386/cpu.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 122 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index f1baefe775..b27db050a2 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1973,6 +1973,56 @@ static const CPUCaches epyc_milan_v2_cache_info = {
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},
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};
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+static const CPUCaches epyc_genoa_cache_info = {
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+ .l1d_cache = &(CPUCacheInfo) {
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+ .type = DATA_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l1i_cache = &(CPUCacheInfo) {
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+ .type = INSTRUCTION_CACHE,
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+ .level = 1,
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+ .size = 32 * KiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 64,
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+ .lines_per_tag = 1,
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+ .self_init = 1,
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+ .no_invd_sharing = true,
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+ },
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+ .l2_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 2,
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+ .size = 1 * MiB,
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+ .line_size = 64,
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+ .associativity = 8,
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+ .partitions = 1,
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+ .sets = 2048,
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+ .lines_per_tag = 1,
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+ },
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+ .l3_cache = &(CPUCacheInfo) {
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+ .type = UNIFIED_CACHE,
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+ .level = 3,
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+ .size = 32 * MiB,
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+ .line_size = 64,
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+ .associativity = 16,
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+ .partitions = 1,
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+ .sets = 32768,
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+ .lines_per_tag = 1,
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+ .self_init = true,
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+ .inclusive = true,
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+ .complex_indexing = false,
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+ },
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+};
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+
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/* The following VMX features are not supported by KVM and are left out in the
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* CPU definitions:
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*
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@@ -4493,6 +4543,78 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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+ {
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+ .name = "EPYC-Genoa",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_AMD,
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+ .family = 25,
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+ .model = 17,
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+ .stepping = 0,
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+ .features[FEAT_1_EDX] =
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+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
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+ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
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+ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
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+ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
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+ CPUID_VME | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
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+ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
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+ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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+ CPUID_EXT_PCID | CPUID_EXT_CX16 | CPUID_EXT_FMA |
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+ CPUID_EXT_SSSE3 | CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ |
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+ CPUID_EXT_SSE3,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
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+ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
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+ CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
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+ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
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+ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
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+ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
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+ .features[FEAT_8000_0008_EBX] =
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+ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
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+ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
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+ CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
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+ CPUID_8000_0008_EBX_STIBP_ALWAYS_ON |
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+ CPUID_8000_0008_EBX_AMD_SSBD | CPUID_8000_0008_EBX_AMD_PSFD,
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+ .features[FEAT_8000_0021_EAX] =
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+ CPUID_8000_0021_EAX_No_NESTED_DATA_BP |
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+ CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING |
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+ CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE |
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+ CPUID_8000_0021_EAX_AUTO_IBRS,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
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+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
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+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_AVX512F |
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+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
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+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
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+ CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
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+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
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+ CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
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+ CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
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+ CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
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+ CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
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+ CPUID_7_0_ECX_RDPID,
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+ .features[FEAT_7_0_EDX] =
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+ CPUID_7_0_EDX_FSRM,
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+ .features[FEAT_7_1_EAX] =
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+ CPUID_7_1_EAX_AVX512_BF16,
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .features[FEAT_SVM] =
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+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_VNMI |
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+ CPUID_SVM_SVME_ADDR_CHK,
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+ .xlevel = 0x80000022,
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+ .model_id = "AMD EPYC-Genoa Processor",
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+ .cache_info = &epyc_genoa_cache_info,
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+ },
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};
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/*
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--
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2.39.3
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105
kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch
Normal file
105
kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch
Normal file
@ -0,0 +1,105 @@
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From 95c5cee20741b055dea9ac3ad3176bbaa1eaf705 Mon Sep 17 00:00:00 2001
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From: Bandan Das <bsd@redhat.com>
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Date: Wed, 9 Aug 2023 12:46:25 -0400
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Subject: [PATCH 6/7] target/i386: Add VNMI and automatic IBRS feature bits
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Bandan Das <None>
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RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
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RH-Bugzilla: 2094913
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RH-Acked-by: Wei Huang <None>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [6/7] 24c0fb08973aa2615817f67576550ce2efadb75c (bdas1/qemu-kvm)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
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commit 62a798d4bc2c3e767d94670776c77a7df274d7c5
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Author: Babu Moger <babu.moger@amd.com>
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Date: Thu May 4 15:53:11 2023 -0500
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target/i386: Add VNMI and automatic IBRS feature bits
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Add the following featute bits.
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vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
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guest without using Event Injection mechanism meaning not required to
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track the guest NMI and intercepting the IRET.
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The presence of this feature is indicated via the CPUID function
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0x8000000A_EDX[25].
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automatic-ibrs :
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The AMD Zen4 core supports a new feature called Automatic IBRS.
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|
It is a "set-and-forget" feature that means that, unlike e.g.,
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|
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
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resources automatically across CPL transitions.
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The presence of this feature is indicated via the CPUID function
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0x80000021_EAX[8].
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The documention for the features are available in the links below.
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a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
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Revision B1 Processors
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b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
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40332 4.05 Date October 2022
|
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Signed-off-by: Santosh Shukla <santosh.shukla@amd.com>
|
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Signed-off-by: Kim Phillips <kim.phillips@amd.com>
|
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Signed-off-by: Babu Moger <babu.moger@amd.com>
|
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Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
|
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Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
|
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|
Message-Id: <20230504205313.225073-7-babu.moger@amd.com>
|
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|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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|
|
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Signed-off-by: Bandan Das <bsd@redhat.com>
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---
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target/i386/cpu.c | 4 ++--
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|
target/i386/cpu.h | 3 +++
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2 files changed, 5 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index bbddc682df..f1baefe775 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -806,7 +806,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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|
"pfthreshold", "avic", NULL, "v-vmsave-vmload",
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|
"vgif", NULL, NULL, NULL,
|
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|
NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, "vnmi", NULL, NULL,
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"svme-addr-chk", NULL, NULL, NULL,
|
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|
},
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|
.cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
|
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|
@@ -925,7 +925,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||||
|
.feat_names = {
|
||||||
|
"no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
|
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|
NULL, NULL, "null-sel-clr-base", NULL,
|
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|
- NULL, NULL, NULL, NULL,
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|
+ "auto-ibrs", NULL, NULL, NULL,
|
||||||
|
NULL, NULL, NULL, NULL,
|
||||||
|
NULL, NULL, NULL, NULL,
|
||||||
|
NULL, NULL, NULL, NULL,
|
||||||
|
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
||||||
|
index c37abf62ae..f7d225e4f1 100644
|
||||||
|
--- a/target/i386/cpu.h
|
||||||
|
+++ b/target/i386/cpu.h
|
||||||
|
@@ -773,6 +773,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
||||||
|
#define CPUID_SVM_AVIC (1U << 13)
|
||||||
|
#define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
|
||||||
|
#define CPUID_SVM_VGIF (1U << 16)
|
||||||
|
+#define CPUID_SVM_VNMI (1U << 25)
|
||||||
|
#define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
|
||||||
|
|
||||||
|
/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
|
||||||
|
@@ -948,6 +949,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
||||||
|
#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
|
||||||
|
/* Null Selector Clears Base */
|
||||||
|
#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
|
||||||
|
+/* Automatic IBRS */
|
||||||
|
+#define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
|
||||||
|
|
||||||
|
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
|
||||||
|
#define CPUID_XSAVE_XSAVEC (1U << 1)
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
@ -0,0 +1,94 @@
|
|||||||
|
From 2d7fb99c02a7666f1d8fe70a4749f0b7771a68ed Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bandan Das <bsd@redhat.com>
|
||||||
|
Date: Wed, 9 Aug 2023 12:29:55 -0400
|
||||||
|
Subject: [PATCH 3/7] target/i386: Add a couple of feature bits in
|
||||||
|
8000_0008_EBX
|
||||||
|
|
||||||
|
RH-Author: Bandan Das <None>
|
||||||
|
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
|
||||||
|
RH-Bugzilla: 2094913
|
||||||
|
RH-Acked-by: Wei Huang <None>
|
||||||
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||||
|
RH-Commit: [3/7] b11020b249d4ecc2e3e1ddf4fdc4b52c42ec2642 (bdas1/qemu-kvm)
|
||||||
|
|
||||||
|
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
|
||||||
|
|
||||||
|
commit bb039a230e6a7920d71d21fa9afee2653a678c48
|
||||||
|
Author: Babu Moger <babu.moger@amd.com>
|
||||||
|
Date: Thu May 4 15:53:08 2023 -0500
|
||||||
|
|
||||||
|
target/i386: Add a couple of feature bits in 8000_0008_EBX
|
||||||
|
|
||||||
|
Add the following feature bits.
|
||||||
|
|
||||||
|
amd-psfd : Predictive Store Forwarding Disable:
|
||||||
|
PSF is a hardware-based micro-architectural optimization
|
||||||
|
designed to improve the performance of code execution by
|
||||||
|
predicting address dependencies between loads and stores.
|
||||||
|
While SSBD (Speculative Store Bypass Disable) disables both
|
||||||
|
PSF and speculative store bypass, PSFD only disables PSF.
|
||||||
|
PSFD may be desirable for the software which is concerned
|
||||||
|
with the speculative behavior of PSF but desires a smaller
|
||||||
|
performance impact than setting SSBD.
|
||||||
|
Depends on the following kernel commit:
|
||||||
|
b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable")
|
||||||
|
|
||||||
|
stibp-always-on :
|
||||||
|
Single Thread Indirect Branch Prediction mode has enhanced
|
||||||
|
performance and may be left always on.
|
||||||
|
|
||||||
|
The documentation for the features are available in the links below.
|
||||||
|
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
|
||||||
|
Revision B1 Processors
|
||||||
|
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
|
||||||
|
|
||||||
|
Signed-off-by: Babu Moger <babu.moger@amd.com>
|
||||||
|
Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
|
||||||
|
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
|
||||||
|
Message-Id: <20230504205313.225073-4-babu.moger@amd.com>
|
||||||
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||||
|
|
||||||
|
Signed-off-by: Bandan Das <bsd@redhat.com>
|
||||||
|
---
|
||||||
|
target/i386/cpu.c | 4 ++--
|
||||||
|
target/i386/cpu.h | 4 ++++
|
||||||
|
2 files changed, 6 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||||
|
index 8aa7eb611c..c8f88aefc7 100644
|
||||||
|
--- a/target/i386/cpu.c
|
||||||
|
+++ b/target/i386/cpu.c
|
||||||
|
@@ -911,10 +911,10 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||||
|
NULL, NULL, NULL, NULL,
|
||||||
|
NULL, "wbnoinvd", NULL, NULL,
|
||||||
|
"ibpb", NULL, "ibrs", "amd-stibp",
|
||||||
|
- NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, "stibp-always-on", NULL, NULL,
|
||||||
|
NULL, NULL, NULL, NULL,
|
||||||
|
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
|
||||||
|
- NULL, NULL, NULL, NULL,
|
||||||
|
+ "amd-psfd", NULL, NULL, NULL,
|
||||||
|
},
|
||||||
|
.cpuid = { .eax = 0x80000008, .reg = R_EBX, },
|
||||||
|
.tcg_features = 0,
|
||||||
|
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
||||||
|
index c28b9df217..81d2200543 100644
|
||||||
|
--- a/target/i386/cpu.h
|
||||||
|
+++ b/target/i386/cpu.h
|
||||||
|
@@ -934,8 +934,12 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
||||||
|
#define CPUID_8000_0008_EBX_IBRS (1U << 14)
|
||||||
|
/* Single Thread Indirect Branch Predictors */
|
||||||
|
#define CPUID_8000_0008_EBX_STIBP (1U << 15)
|
||||||
|
+/* STIBP mode has enhanced performance and may be left always on */
|
||||||
|
+#define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
|
||||||
|
/* Speculative Store Bypass Disable */
|
||||||
|
#define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
|
||||||
|
+/* Predictive Store Forwarding Disable */
|
||||||
|
+#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
|
||||||
|
|
||||||
|
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
|
||||||
|
#define CPUID_XSAVE_XSAVEC (1U << 1)
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
126
kvm-target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch
Normal file
126
kvm-target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch
Normal file
@ -0,0 +1,126 @@
|
|||||||
|
From 2a2f74c53258ef67034307b59afe2f4c679afaa2 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bandan Das <bsd@redhat.com>
|
||||||
|
Date: Wed, 9 Aug 2023 12:32:00 -0400
|
||||||
|
Subject: [PATCH 4/7] target/i386: Add feature bits for CPUID_Fn80000021_EAX
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
RH-Author: Bandan Das <None>
|
||||||
|
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
|
||||||
|
RH-Bugzilla: 2094913
|
||||||
|
RH-Acked-by: Wei Huang <None>
|
||||||
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||||
|
RH-Commit: [4/7] 133044a7245226308406a684a875e1f96a394516 (bdas1/qemu-kvm)
|
||||||
|
|
||||||
|
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
|
||||||
|
|
||||||
|
commit b70eec312b185197d639bff689007727e596afd1
|
||||||
|
Author: Babu Moger <babu.moger@amd.com>
|
||||||
|
Date: Thu May 4 15:53:09 2023 -0500
|
||||||
|
|
||||||
|
target/i386: Add feature bits for CPUID_Fn80000021_EAX
|
||||||
|
|
||||||
|
Add the following feature bits.
|
||||||
|
no-nested-data-bp : Processor ignores nested data breakpoints.
|
||||||
|
lfence-always-serializing : LFENCE instruction is always serializing.
|
||||||
|
null-sel-cls-base : Null Selector Clears Base. When this bit is
|
||||||
|
set, a null segment load clears the segment base.
|
||||||
|
|
||||||
|
The documentation for the features are available in the links below.
|
||||||
|
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
|
||||||
|
Revision B1 Processors
|
||||||
|
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
|
||||||
|
40332 4.05 Date October 2022
|
||||||
|
|
||||||
|
Signed-off-by: Babu Moger <babu.moger@amd.com>
|
||||||
|
Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
|
||||||
|
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
|
||||||
|
Message-Id: <20230504205313.225073-5-babu.moger@amd.com>
|
||||||
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||||
|
|
||||||
|
Signed-off-by: Bandan Das <bsd@redhat.com>
|
||||||
|
---
|
||||||
|
target/i386/cpu.c | 24 ++++++++++++++++++++++++
|
||||||
|
target/i386/cpu.h | 8 ++++++++
|
||||||
|
2 files changed, 32 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||||
|
index c8f88aefc7..7ddebbaa3c 100644
|
||||||
|
--- a/target/i386/cpu.c
|
||||||
|
+++ b/target/i386/cpu.c
|
||||||
|
@@ -920,6 +920,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
|
||||||
|
.tcg_features = 0,
|
||||||
|
.unmigratable_flags = 0,
|
||||||
|
},
|
||||||
|
+ [FEAT_8000_0021_EAX] = {
|
||||||
|
+ .type = CPUID_FEATURE_WORD,
|
||||||
|
+ .feat_names = {
|
||||||
|
+ "no-nested-data-bp", NULL, "lfence-always-serializing", NULL,
|
||||||
|
+ NULL, NULL, "null-sel-clr-base", NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ NULL, NULL, NULL, NULL,
|
||||||
|
+ },
|
||||||
|
+ .cpuid = { .eax = 0x80000021, .reg = R_EAX, },
|
||||||
|
+ .tcg_features = 0,
|
||||||
|
+ .unmigratable_flags = 0,
|
||||||
|
+ },
|
||||||
|
[FEAT_XSAVE] = {
|
||||||
|
.type = CPUID_FEATURE_WORD,
|
||||||
|
.feat_names = {
|
||||||
|
@@ -6156,6 +6172,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
||||||
|
*ebx |= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
+ case 0x80000021:
|
||||||
|
+ *eax = env->features[FEAT_8000_0021_EAX];
|
||||||
|
+ *ebx = *ecx = *edx = 0;
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
/* reserved values: zero */
|
||||||
|
*eax = 0;
|
||||||
|
@@ -6585,6 +6605,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
|
||||||
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (env->features[FEAT_8000_0021_EAX]) {
|
||||||
|
+ x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x80000021);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
/* SGX requires CPUID[0x12] for EPC enumeration */
|
||||||
|
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) {
|
||||||
|
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12);
|
||||||
|
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
|
||||||
|
index 81d2200543..c37abf62ae 100644
|
||||||
|
--- a/target/i386/cpu.h
|
||||||
|
+++ b/target/i386/cpu.h
|
||||||
|
@@ -600,6 +600,7 @@ typedef enum FeatureWord {
|
||||||
|
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
|
||||||
|
FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
|
||||||
|
FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
|
||||||
|
+ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */
|
||||||
|
FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
|
||||||
|
FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
|
||||||
|
FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
|
||||||
|
@@ -941,6 +942,13 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
||||||
|
/* Predictive Store Forwarding Disable */
|
||||||
|
#define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
|
||||||
|
|
||||||
|
+/* Processor ignores nested data breakpoints */
|
||||||
|
+#define CPUID_8000_0021_EAX_No_NESTED_DATA_BP (1U << 0)
|
||||||
|
+/* LFENCE is always serializing */
|
||||||
|
+#define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
|
||||||
|
+/* Null Selector Clears Base */
|
||||||
|
+#define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
|
||||||
|
+
|
||||||
|
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
|
||||||
|
#define CPUID_XSAVE_XSAVEC (1U << 1)
|
||||||
|
#define CPUID_XSAVE_XGETBV1 (1U << 2)
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
152
kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch
Normal file
152
kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch
Normal file
@ -0,0 +1,152 @@
|
|||||||
|
From a8180665019d537ee9775614627bf9eb8bd4770e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bandan Das <bsd@redhat.com>
|
||||||
|
Date: Wed, 9 Aug 2023 12:35:33 -0400
|
||||||
|
Subject: [PATCH 5/7] target/i386: Add missing feature bits in EPYC-Milan model
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
RH-Author: Bandan Das <None>
|
||||||
|
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
|
||||||
|
RH-Bugzilla: 2094913
|
||||||
|
RH-Acked-by: Wei Huang <None>
|
||||||
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||||
|
RH-Commit: [5/7] 8f77315c8d7010564423df3e3c594c90fd5f9c00 (bdas1/qemu-kvm)
|
||||||
|
|
||||||
|
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
|
||||||
|
|
||||||
|
commit 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
|
||||||
|
Author: Babu Moger <babu.moger@amd.com>
|
||||||
|
Date: Thu May 4 15:53:10 2023 -0500
|
||||||
|
|
||||||
|
target/i386: Add missing feature bits in EPYC-Milan model
|
||||||
|
|
||||||
|
Add the following feature bits for EPYC-Milan model and bump the version.
|
||||||
|
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
|
||||||
|
vpclmulqdq : Vector VPCLMULQDQ instruction support
|
||||||
|
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
|
||||||
|
performance and may be left Always on
|
||||||
|
amd-psfd : Predictive Store Forward Disable
|
||||||
|
no-nested-data-bp : Processor ignores nested data breakpoints
|
||||||
|
lfence-always-serializing : LFENCE instruction is always serializing
|
||||||
|
null-sel-clr-base : Null Selector Clears Base. When this bit is
|
||||||
|
set, a null segment load clears the segment base
|
||||||
|
|
||||||
|
These new features will be added in EPYC-Milan-v2. The "-cpu help" output
|
||||||
|
after the change will be.
|
||||||
|
|
||||||
|
x86 EPYC-Milan (alias configured by machine type)
|
||||||
|
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
|
||||||
|
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
|
||||||
|
|
||||||
|
The documentation for the features are available in the links below.
|
||||||
|
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
|
||||||
|
Revision B1 Processors
|
||||||
|
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
|
||||||
|
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
|
||||||
|
40332 4.05 Date October 2022
|
||||||
|
|
||||||
|
Signed-off-by: Babu Moger <babu.moger@amd.com>
|
||||||
|
Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
|
||||||
|
Link: https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
|
||||||
|
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
|
||||||
|
Message-Id: <20230504205313.225073-6-babu.moger@amd.com>
|
||||||
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||||
|
|
||||||
|
Signed-off-by: Bandan Das <bsd@redhat.com>
|
||||||
|
---
|
||||||
|
target/i386/cpu.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 70 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||||
|
index 7ddebbaa3c..bbddc682df 100644
|
||||||
|
--- a/target/i386/cpu.c
|
||||||
|
+++ b/target/i386/cpu.c
|
||||||
|
@@ -1923,6 +1923,56 @@ static const CPUCaches epyc_milan_cache_info = {
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const CPUCaches epyc_milan_v2_cache_info = {
|
||||||
|
+ .l1d_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = DATA_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 32 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 64,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l1i_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = INSTRUCTION_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 32 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 64,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l2_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 2,
|
||||||
|
+ .size = 512 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 1024,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ },
|
||||||
|
+ .l3_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 3,
|
||||||
|
+ .size = 32 * MiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 16,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 32768,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = true,
|
||||||
|
+ .inclusive = true,
|
||||||
|
+ .complex_indexing = false,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
/* The following VMX features are not supported by KVM and are left out in the
|
||||||
|
* CPU definitions:
|
||||||
|
*
|
||||||
|
@@ -4422,6 +4472,26 @@ static const X86CPUDefinition builtin_x86_defs[] = {
|
||||||
|
.xlevel = 0x8000001E,
|
||||||
|
.model_id = "AMD EPYC-Milan Processor",
|
||||||
|
.cache_info = &epyc_milan_cache_info,
|
||||||
|
+ .versions = (X86CPUVersionDefinition[]) {
|
||||||
|
+ { .version = 1 },
|
||||||
|
+ {
|
||||||
|
+ .version = 2,
|
||||||
|
+ .props = (PropValue[]) {
|
||||||
|
+ { "model-id",
|
||||||
|
+ "AMD EPYC-Milan-v2 Processor" },
|
||||||
|
+ { "vaes", "on" },
|
||||||
|
+ { "vpclmulqdq", "on" },
|
||||||
|
+ { "stibp-always-on", "on" },
|
||||||
|
+ { "amd-psfd", "on" },
|
||||||
|
+ { "no-nested-data-bp", "on" },
|
||||||
|
+ { "lfence-always-serializing", "on" },
|
||||||
|
+ { "null-sel-clr-base", "on" },
|
||||||
|
+ { /* end of list */ }
|
||||||
|
+ },
|
||||||
|
+ .cache_info = &epyc_milan_v2_cache_info
|
||||||
|
+ },
|
||||||
|
+ { /* end of list */ }
|
||||||
|
+ }
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
192
kvm-target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch
Normal file
192
kvm-target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch
Normal file
@ -0,0 +1,192 @@
|
|||||||
|
From 92f0b5d0c7a841a21cabbc6efc1d7baf0e5a3e0f Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bandan Das <bsd@redhat.com>
|
||||||
|
Date: Wed, 9 Aug 2023 12:26:12 -0400
|
||||||
|
Subject: [PATCH 2/7] target/i386: Add new EPYC CPU versions with updated
|
||||||
|
cache_info
|
||||||
|
|
||||||
|
RH-Author: Bandan Das <None>
|
||||||
|
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
|
||||||
|
RH-Bugzilla: 2094913
|
||||||
|
RH-Acked-by: Wei Huang <None>
|
||||||
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||||
|
RH-Commit: [2/7] 71a2fd907636733f86729bc9328600f6f9306eaf (bdas1/qemu-kvm)
|
||||||
|
|
||||||
|
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
|
||||||
|
|
||||||
|
commit d7c72735f618a7ee27ee109d8b1468193734606a
|
||||||
|
Author: Michael Roth <michael.roth@amd.com>
|
||||||
|
Date: Thu May 4 15:53:07 2023 -0500
|
||||||
|
|
||||||
|
target/i386: Add new EPYC CPU versions with updated cache_info
|
||||||
|
|
||||||
|
Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
|
||||||
|
The only difference vs. older models is an updated cache_info with
|
||||||
|
the 'complex_indexing' bit unset, since this bit is not currently
|
||||||
|
defined for AMD and may cause problems should it be used for
|
||||||
|
something else in the future. Setting this bit will also cause
|
||||||
|
CPUID validation failures when running SEV-SNP guests.
|
||||||
|
|
||||||
|
Signed-off-by: Michael Roth <michael.roth@amd.com>
|
||||||
|
Signed-off-by: Babu Moger <babu.moger@amd.com>
|
||||||
|
Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
Message-Id: <20230504205313.225073-3-babu.moger@amd.com>
|
||||||
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||||
|
|
||||||
|
Signed-off-by: Bandan Das <bsd@redhat.com>
|
||||||
|
---
|
||||||
|
target/i386/cpu.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 118 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||||
|
index 3558c92ed0..8aa7eb611c 100644
|
||||||
|
--- a/target/i386/cpu.c
|
||||||
|
+++ b/target/i386/cpu.c
|
||||||
|
@@ -1707,6 +1707,56 @@ static const CPUCaches epyc_cache_info = {
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
+static CPUCaches epyc_v4_cache_info = {
|
||||||
|
+ .l1d_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = DATA_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 32 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 64,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l1i_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = INSTRUCTION_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 64 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 4,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 256,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l2_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 2,
|
||||||
|
+ .size = 512 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 1024,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ },
|
||||||
|
+ .l3_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 3,
|
||||||
|
+ .size = 8 * MiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 16,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 8192,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = true,
|
||||||
|
+ .inclusive = true,
|
||||||
|
+ .complex_indexing = false,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const CPUCaches epyc_rome_cache_info = {
|
||||||
|
.l1d_cache = &(CPUCacheInfo) {
|
||||||
|
.type = DATA_CACHE,
|
||||||
|
@@ -1757,6 +1807,56 @@ static const CPUCaches epyc_rome_cache_info = {
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const CPUCaches epyc_rome_v3_cache_info = {
|
||||||
|
+ .l1d_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = DATA_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 32 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 64,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l1i_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = INSTRUCTION_CACHE,
|
||||||
|
+ .level = 1,
|
||||||
|
+ .size = 32 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 64,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = 1,
|
||||||
|
+ .no_invd_sharing = true,
|
||||||
|
+ },
|
||||||
|
+ .l2_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 2,
|
||||||
|
+ .size = 512 * KiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 8,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 1024,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ },
|
||||||
|
+ .l3_cache = &(CPUCacheInfo) {
|
||||||
|
+ .type = UNIFIED_CACHE,
|
||||||
|
+ .level = 3,
|
||||||
|
+ .size = 16 * MiB,
|
||||||
|
+ .line_size = 64,
|
||||||
|
+ .associativity = 16,
|
||||||
|
+ .partitions = 1,
|
||||||
|
+ .sets = 16384,
|
||||||
|
+ .lines_per_tag = 1,
|
||||||
|
+ .self_init = true,
|
||||||
|
+ .inclusive = true,
|
||||||
|
+ .complex_indexing = false,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const CPUCaches epyc_milan_cache_info = {
|
||||||
|
.l1d_cache = &(CPUCacheInfo) {
|
||||||
|
.type = DATA_CACHE,
|
||||||
|
@@ -4112,6 +4212,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
|
||||||
|
{ /* end of list */ }
|
||||||
|
}
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .version = 4,
|
||||||
|
+ .props = (PropValue[]) {
|
||||||
|
+ { "model-id",
|
||||||
|
+ "AMD EPYC-v4 Processor" },
|
||||||
|
+ { /* end of list */ }
|
||||||
|
+ },
|
||||||
|
+ .cache_info = &epyc_v4_cache_info
|
||||||
|
+ },
|
||||||
|
{ /* end of list */ }
|
||||||
|
}
|
||||||
|
},
|
||||||
|
@@ -4231,6 +4340,15 @@ static const X86CPUDefinition builtin_x86_defs[] = {
|
||||||
|
{ /* end of list */ }
|
||||||
|
}
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .version = 3,
|
||||||
|
+ .props = (PropValue[]) {
|
||||||
|
+ { "model-id",
|
||||||
|
+ "AMD EPYC-Rome-v3 Processor" },
|
||||||
|
+ { /* end of list */ }
|
||||||
|
+ },
|
||||||
|
+ .cache_info = &epyc_rome_v3_cache_info
|
||||||
|
+ },
|
||||||
|
{ /* end of list */ }
|
||||||
|
}
|
||||||
|
},
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
116
kvm-target-i386-allow-versioned-CPUs-to-specify-new-cach.patch
Normal file
116
kvm-target-i386-allow-versioned-CPUs-to-specify-new-cach.patch
Normal file
@ -0,0 +1,116 @@
|
|||||||
|
From 457e74c076e0fe7b64631dfd4369d167f0762c9a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bandan Das <bsd@redhat.com>
|
||||||
|
Date: Wed, 9 Aug 2023 12:22:41 -0400
|
||||||
|
Subject: [PATCH 1/7] target/i386: allow versioned CPUs to specify new
|
||||||
|
cache_info
|
||||||
|
|
||||||
|
RH-Author: Bandan Das <None>
|
||||||
|
RH-MergeRequest: 198: Add EPYC-Genoa CPU model in qemu
|
||||||
|
RH-Bugzilla: 2094913
|
||||||
|
RH-Acked-by: Wei Huang <None>
|
||||||
|
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
||||||
|
RH-Commit: [1/7] 6070e07a4bb070d1c15a811b2bd3195929c18d61 (bdas1/qemu-kvm)
|
||||||
|
|
||||||
|
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2094913
|
||||||
|
|
||||||
|
commit cca0a000d06f897411a8af4402e5d0522bbe450b
|
||||||
|
Author: Michael Roth <michael.roth@amd.com>
|
||||||
|
Date: Thu May 4 15:53:06 2023 -0500
|
||||||
|
|
||||||
|
target/i386: allow versioned CPUs to specify new cache_info
|
||||||
|
|
||||||
|
New EPYC CPUs versions require small changes to their cache_info's.
|
||||||
|
Because current QEMU x86 CPU definition does not support versioned
|
||||||
|
cach_info, we would have to declare a new CPU type for each such case.
|
||||||
|
To avoid the dup work, add "cache_info" in X86CPUVersionDefinition",
|
||||||
|
to allow new cache_info pointers to be specified for a new CPU version.
|
||||||
|
|
||||||
|
Co-developed-by: Wei Huang <wei.huang2@amd.com>
|
||||||
|
Signed-off-by: Wei Huang <wei.huang2@amd.com>
|
||||||
|
Signed-off-by: Michael Roth <michael.roth@amd.com>
|
||||||
|
Signed-off-by: Babu Moger <babu.moger@amd.com>
|
||||||
|
Acked-by: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
Message-Id: <20230504205313.225073-2-babu.moger@amd.com>
|
||||||
|
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
||||||
|
|
||||||
|
Signed-off-by: Bandan Das <bsd@redhat.com>
|
||||||
|
---
|
||||||
|
target/i386/cpu.c | 35 ++++++++++++++++++++++++++++++++---
|
||||||
|
1 file changed, 32 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
|
||||||
|
index 4ac3046313..3558c92ed0 100644
|
||||||
|
--- a/target/i386/cpu.c
|
||||||
|
+++ b/target/i386/cpu.c
|
||||||
|
@@ -1598,6 +1598,7 @@ typedef struct X86CPUVersionDefinition {
|
||||||
|
const char *alias;
|
||||||
|
const char *note;
|
||||||
|
PropValue *props;
|
||||||
|
+ const CPUCaches *const cache_info;
|
||||||
|
} X86CPUVersionDefinition;
|
||||||
|
|
||||||
|
/* Base definition for a CPU model */
|
||||||
|
@@ -5213,6 +5214,31 @@ static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
|
||||||
|
assert(vdef->version == version);
|
||||||
|
}
|
||||||
|
|
||||||
|
+static const CPUCaches *x86_cpu_get_versioned_cache_info(X86CPU *cpu,
|
||||||
|
+ X86CPUModel *model)
|
||||||
|
+{
|
||||||
|
+ const X86CPUVersionDefinition *vdef;
|
||||||
|
+ X86CPUVersion version = x86_cpu_model_resolve_version(model);
|
||||||
|
+ const CPUCaches *cache_info = model->cpudef->cache_info;
|
||||||
|
+
|
||||||
|
+ if (version == CPU_VERSION_LEGACY) {
|
||||||
|
+ return cache_info;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
|
||||||
|
+ if (vdef->cache_info) {
|
||||||
|
+ cache_info = vdef->cache_info;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (vdef->version == version) {
|
||||||
|
+ break;
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ assert(vdef->version == version);
|
||||||
|
+ return cache_info;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* Load data from X86CPUDefinition into a X86CPU object.
|
||||||
|
* Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
|
||||||
|
@@ -5245,7 +5271,7 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
|
||||||
|
}
|
||||||
|
|
||||||
|
/* legacy-cache defaults to 'off' if CPU model provides cache info */
|
||||||
|
- cpu->legacy_cache = !def->cache_info;
|
||||||
|
+ cpu->legacy_cache = !x86_cpu_get_versioned_cache_info(cpu, model);
|
||||||
|
|
||||||
|
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
|
||||||
|
|
||||||
|
@@ -6724,14 +6750,17 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
|
||||||
|
|
||||||
|
/* Cache information initialization */
|
||||||
|
if (!cpu->legacy_cache) {
|
||||||
|
- if (!xcc->model || !xcc->model->cpudef->cache_info) {
|
||||||
|
+ const CPUCaches *cache_info =
|
||||||
|
+ x86_cpu_get_versioned_cache_info(cpu, xcc->model);
|
||||||
|
+
|
||||||
|
+ if (!xcc->model || !cache_info) {
|
||||||
|
g_autofree char *name = x86_cpu_class_get_model_name(xcc);
|
||||||
|
error_setg(errp,
|
||||||
|
"CPU model '%s' doesn't support legacy-cache=off", name);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
|
||||||
|
- *xcc->model->cpudef->cache_info;
|
||||||
|
+ *cache_info;
|
||||||
|
} else {
|
||||||
|
/* Build legacy cache information */
|
||||||
|
env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
|
||||||
|
--
|
||||||
|
2.39.3
|
||||||
|
|
||||||
@ -149,7 +149,7 @@ Obsoletes: %{name}-block-ssh <= %{epoch}:%{version} \
|
|||||||
Summary: QEMU is a machine emulator and virtualizer
|
Summary: QEMU is a machine emulator and virtualizer
|
||||||
Name: qemu-kvm
|
Name: qemu-kvm
|
||||||
Version: 8.0.0
|
Version: 8.0.0
|
||||||
Release: 11%{?rcrel}%{?dist}%{?cc_suffix}
|
Release: 12%{?rcrel}%{?dist}%{?cc_suffix}
|
||||||
# Epoch because we pushed a qemu-1.0 package. AIUI this can't ever be dropped
|
# Epoch because we pushed a qemu-1.0 package. AIUI this can't ever be dropped
|
||||||
# Epoch 15 used for RHEL 8
|
# Epoch 15 used for RHEL 8
|
||||||
# Epoch 17 used for RHEL 9 (due to release versioning offset in RHEL 8.5)
|
# Epoch 17 used for RHEL 9 (due to release versioning offset in RHEL 8.5)
|
||||||
@ -518,6 +518,20 @@ Patch177: kvm-qemu-options.hx-Update-the-reduced-phys-bits-documen.patch
|
|||||||
Patch178: kvm-i386-sev-Update-checks-and-information-related-to-re.patch
|
Patch178: kvm-i386-sev-Update-checks-and-information-related-to-re.patch
|
||||||
# For bz#2214839 - [AMDSERVER 9.3 Bug] Qemu SEV reduced-phys-bits fixes
|
# For bz#2214839 - [AMDSERVER 9.3 Bug] Qemu SEV reduced-phys-bits fixes
|
||||||
Patch179: kvm-i386-cpu-Update-how-the-EBX-register-of-CPUID-0x8000.patch
|
Patch179: kvm-i386-cpu-Update-how-the-EBX-register-of-CPUID-0x8000.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch180: kvm-target-i386-allow-versioned-CPUs-to-specify-new-cach.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch181: kvm-target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch182: kvm-target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch183: kvm-target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch184: kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch185: kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch
|
||||||
|
# For bz#2094913 - Add EPYC-Genoa CPU model in qemu
|
||||||
|
Patch186: kvm-target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch
|
||||||
|
|
||||||
%if %{have_clang}
|
%if %{have_clang}
|
||||||
BuildRequires: clang
|
BuildRequires: clang
|
||||||
@ -1579,6 +1593,17 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \
|
|||||||
%endif
|
%endif
|
||||||
|
|
||||||
%changelog
|
%changelog
|
||||||
|
* Mon Aug 21 2023 Miroslav Rezanina <mrezanin@redhat.com> - 8.0.0-12
|
||||||
|
- kvm-target-i386-allow-versioned-CPUs-to-specify-new-cach.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-new-EPYC-CPU-versions-with-updated-c.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-a-couple-of-feature-bits-in-8000_000.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-feature-bits-for-CPUID_Fn80000021_EA.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-missing-feature-bits-in-EPYC-Milan-m.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-VNMI-and-automatic-IBRS-feature-bits.patch [bz#2094913]
|
||||||
|
- kvm-target-i386-Add-EPYC-Genoa-model-to-support-Zen-4-pr.patch [bz#2094913]
|
||||||
|
- Resolves: bz#2094913
|
||||||
|
(Add EPYC-Genoa CPU model in qemu)
|
||||||
|
|
||||||
* Mon Aug 07 2023 Miroslav Rezanina <mrezanin@redhat.com> - 8.0.0-11
|
* Mon Aug 07 2023 Miroslav Rezanina <mrezanin@redhat.com> - 8.0.0-11
|
||||||
- kvm-block-blkio-enable-the-completion-eventfd.patch [bz#2225354 bz#2225439]
|
- kvm-block-blkio-enable-the-completion-eventfd.patch [bz#2225354 bz#2225439]
|
||||||
- kvm-block-blkio-do-not-use-open-flags-in-qemu_open.patch [bz#2225354 bz#2225439]
|
- kvm-block-blkio-do-not-use-open-flags-in-qemu_open.patch [bz#2225354 bz#2225439]
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user