From 9196fca5998e6179ec0bfb54c3b041e73afc0404 Mon Sep 17 00:00:00 2001 From: Miroslav Rezanina Date: Mon, 20 Oct 2025 08:14:11 +0200 Subject: [PATCH] * Mon Oct 20 2025 Miroslav Rezanina - 10.1.0-3 - kvm-arm-kvm-report-registers-we-failed-to-set.patch [RHEL-119368] - kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch [RHEL-116443] - kvm-target-i386-add-compatibility-property-for-arch_capa.patch [RHEL-120253] - kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch [RHEL-120253] - Resolves: RHEL-119368 ([rhel10] Backport "arm/kvm: report registers we failed to set") - Resolves: RHEL-116443 (qemu crash after hot-unplug disk from the multifunction enabled bus,crash point PCIDevice *vf = dev->exp.sriov_pf.vf[i]) - Resolves: RHEL-120253 (Backport fixes for PDCM and ARCH_CAPABILITIES migration incompatibility) --- ...vm-report-registers-we-failed-to-set.patch | 154 ++++++++++++++++++ ...pcie_sriov_pf_exit-safe-on-non-SR-IO.patch | 73 +++++++++ ...compatibility-property-for-arch_capa.patch | 135 +++++++++++++++ ...compatibility-property-for-pdcm-feat.patch | 115 +++++++++++++ qemu-kvm.spec | 22 ++- 5 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 kvm-arm-kvm-report-registers-we-failed-to-set.patch create mode 100644 kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch create mode 100644 kvm-target-i386-add-compatibility-property-for-arch_capa.patch create mode 100644 kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch diff --git a/kvm-arm-kvm-report-registers-we-failed-to-set.patch b/kvm-arm-kvm-report-registers-we-failed-to-set.patch new file mode 100644 index 0000000..9f956e9 --- /dev/null +++ b/kvm-arm-kvm-report-registers-we-failed-to-set.patch @@ -0,0 +1,154 @@ +From d635b553683b9a057d7a1a4b7e3348c88dcab6d6 Mon Sep 17 00:00:00 2001 +From: Cornelia Huck +Date: Thu, 11 Sep 2025 17:41:59 +0200 +Subject: [PATCH 1/4] arm/kvm: report registers we failed to set + +RH-Author: Eric Auger +RH-MergeRequest: 410: arm/kvm: report registers we failed to set +RH-Jira: RHEL-119368 +RH-Acked-by: Cornelia Huck +RH-Acked-by: Sebastian Ott +RH-Acked-by: Gavin Shan +RH-Acked-by: Donald Dutile +RH-Commit: [1/1] 82b4496284ff0a4dd2dd0eae7bb1cf114dded61e (eauger1/centos-qemu-kvm) + +If we fail migration because of a mismatch of some registers between +source and destination, the error message is not very informative: + +qemu-system-aarch64: error while loading state for instance 0x0 ofdevice 'cpu' +qemu-system-aarch64: Failed to put registers after init: Invalid argument + +At least try to give the user a hint which registers had a problem, +even if they cannot really do anything about it right now. + +Sample output: + +Could not set register op0:3 op1:0 crn:0 crm:0 op2:0 to c00fac31 (is 413fd0c1) + +We could be even more helpful once we support writable ID registers, +at which point the user might actually be able to configure something +that is migratable. + +Suggested-by: Eric Auger +Reviewed-by: Sebastian Ott +Signed-off-by: Cornelia Huck +Message-id: 20250911154159.158046-1-cohuck@redhat.com +Signed-off-by: Peter Maydell +(cherry picked from commit 19f6dcfe6b8b2a3523362812fc696ab83050d316) +Signed-off-by: Eric Auger +--- + target/arm/kvm.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 86 insertions(+) + +diff --git a/target/arm/kvm.c b/target/arm/kvm.c +index 6672344855..c1ec6654ca 100644 +--- a/target/arm/kvm.c ++++ b/target/arm/kvm.c +@@ -900,6 +900,58 @@ bool write_kvmstate_to_list(ARMCPU *cpu) + return ok; + } + ++/* pretty-print a KVM register */ ++#define CP_REG_ARM64_SYSREG_OP(_reg, _op) \ ++ ((uint8_t)((_reg & CP_REG_ARM64_SYSREG_ ## _op ## _MASK) >> \ ++ CP_REG_ARM64_SYSREG_ ## _op ## _SHIFT)) ++ ++static gchar *kvm_print_sve_register_name(uint64_t regidx) ++{ ++ uint16_t sve_reg = regidx & 0x000000000000ffff; ++ ++ if (regidx == KVM_REG_ARM64_SVE_VLS) { ++ return g_strdup_printf("SVE VLS"); ++ } ++ /* zreg, preg, ffr */ ++ switch (sve_reg & 0xfc00) { ++ case 0: ++ return g_strdup_printf("SVE zreg n:%d slice:%d", ++ (sve_reg & 0x03e0) >> 5, sve_reg & 0x001f); ++ case 0x04: ++ return g_strdup_printf("SVE preg n:%d slice:%d", ++ (sve_reg & 0x01e0) >> 5, sve_reg & 0x001f); ++ case 0x06: ++ return g_strdup_printf("SVE ffr slice:%d", sve_reg & 0x001f); ++ default: ++ return g_strdup_printf("SVE ???"); ++ } ++} ++ ++static gchar *kvm_print_register_name(uint64_t regidx) ++{ ++ switch ((regidx & KVM_REG_ARM_COPROC_MASK)) { ++ case KVM_REG_ARM_CORE: ++ return g_strdup_printf("core reg %"PRIx64, regidx); ++ case KVM_REG_ARM_DEMUX: ++ return g_strdup_printf("demuxed reg %"PRIx64, regidx); ++ case KVM_REG_ARM64_SYSREG: ++ return g_strdup_printf("op0:%d op1:%d crn:%d crm:%d op2:%d", ++ CP_REG_ARM64_SYSREG_OP(regidx, OP0), ++ CP_REG_ARM64_SYSREG_OP(regidx, OP1), ++ CP_REG_ARM64_SYSREG_OP(regidx, CRN), ++ CP_REG_ARM64_SYSREG_OP(regidx, CRM), ++ CP_REG_ARM64_SYSREG_OP(regidx, OP2)); ++ case KVM_REG_ARM_FW: ++ return g_strdup_printf("fw reg %d", (int)(regidx & 0xffff)); ++ case KVM_REG_ARM64_SVE: ++ return kvm_print_sve_register_name(regidx); ++ case KVM_REG_ARM_FW_FEAT_BMAP: ++ return g_strdup_printf("fw feat reg %d", (int)(regidx & 0xffff)); ++ default: ++ return g_strdup_printf("%"PRIx64, regidx); ++ } ++} ++ + bool write_list_to_kvmstate(ARMCPU *cpu, int level) + { + CPUState *cs = CPU(cpu); +@@ -927,11 +979,45 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) + g_assert_not_reached(); + } + if (ret) { ++ gchar *reg_str = kvm_print_register_name(regidx); ++ + /* We might fail for "unknown register" and also for + * "you tried to set a register which is constant with + * a different value from what it actually contains". + */ + ok = false; ++ switch (ret) { ++ case -ENOENT: ++ error_report("Could not set register %s: unknown to KVM", ++ reg_str); ++ break; ++ case -EINVAL: ++ if ((regidx & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) { ++ if (!kvm_get_one_reg(cs, regidx, &v32)) { ++ error_report("Could not set register %s to %x (is %x)", ++ reg_str, (uint32_t)cpu->cpreg_values[i], ++ v32); ++ } else { ++ error_report("Could not set register %s to %x", ++ reg_str, (uint32_t)cpu->cpreg_values[i]); ++ } ++ } else /* U64 */ { ++ uint64_t v64; ++ ++ if (!kvm_get_one_reg(cs, regidx, &v64)) { ++ error_report("Could not set register %s to %"PRIx64" (is %"PRIx64")", ++ reg_str, cpu->cpreg_values[i], v64); ++ } else { ++ error_report("Could not set register %s to %"PRIx64, ++ reg_str, cpu->cpreg_values[i]); ++ } ++ } ++ break; ++ default: ++ error_report("Could not set register %s: %s", ++ reg_str, strerror(-ret)); ++ } ++ g_free(reg_str); + } + } + return ok; +-- +2.47.3 + diff --git a/kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch b/kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch new file mode 100644 index 0000000..8790d13 --- /dev/null +++ b/kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch @@ -0,0 +1,73 @@ +From db20fe92c8cc22e3317787d6c83056126e912f3a Mon Sep 17 00:00:00 2001 +From: Stefan Hajnoczi +Date: Wed, 24 Sep 2025 11:51:53 -0400 +Subject: [PATCH 2/4] pcie_sriov: make pcie_sriov_pf_exit() safe on non-SR-IOV + devices + +RH-Author: Stefan Hajnoczi +RH-MergeRequest: 408: pcie_sriov: make pcie_sriov_pf_exit() safe on non-SR-IOV devices +RH-Jira: RHEL-116443 +RH-Acked-by: Miroslav Rezanina +RH-Commit: [1/1] a4fea6ad073c9fa5fdc7f20b3dfeab4e4acef73f (stefanha/centos-stream-qemu-kvm) + +Commit 3f9cfaa92c96 ("virtio-pci: Implement SR-IOV PF") added an +unconditional call from virtio_pci_exit() to pcie_sriov_pf_exit(). + +pcie_sriov_pf_exit() reads from the SR-IOV Capability in Configuration +Space: + + uint8_t *cfg = dev->config + dev->exp.sriov_cap; + ... + unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This results in undefined behavior when dev->exp.sriov_cap is 0 because +this is not an SR-IOV device. For example, unparent_vfs() segfaults when +total_vfs happens to be non-zero. + +Fix this by returning early from pcie_sriov_pf_exit() when +dev->exp.sriov_cap is 0 because this is not an SR-IOV device. + +Cc: Akihiko Odaki +Cc: Michael S. Tsirkin +Reported-by: Qing Wang +Buglink: https://issues.redhat.com/browse/RHEL-116443 +Signed-off-by: Stefan Hajnoczi +Reviewed-by: Akihiko Odaki +Fixes: cab1398a60eb ("pcie_sriov: Reuse SR-IOV VF device instances") +Reviewed-by: Michael S. Tsirkin +Message-ID: <20250924155153.579495-1-stefanha@redhat.com> +Signed-off-by: Michael S. Tsirkin +(cherry picked from commit bab681f752048c3bc22d561b1d314c7ec16419c9) +Signed-off-by: Stefan Hajnoczi +--- + hw/pci/pcie_sriov.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c +index 8a4bf0d6f7..cf1b5b5c05 100644 +--- a/hw/pci/pcie_sriov.c ++++ b/hw/pci/pcie_sriov.c +@@ -195,7 +195,9 @@ bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, + + void pcie_sriov_pf_exit(PCIDevice *dev) + { +- uint8_t *cfg = dev->config + dev->exp.sriov_cap; ++ if (dev->exp.sriov_cap == 0) { ++ return; ++ } + + if (dev->exp.sriov_pf.vf_user_created) { + uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID); +@@ -211,6 +213,8 @@ void pcie_sriov_pf_exit(PCIDevice *dev) + pci_config_set_device_id(dev->exp.sriov_pf.vf[i]->config, vf_dev_id); + } + } else { ++ uint8_t *cfg = dev->config + dev->exp.sriov_cap; ++ + unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); + } + } +-- +2.47.3 + diff --git a/kvm-target-i386-add-compatibility-property-for-arch_capa.patch b/kvm-target-i386-add-compatibility-property-for-arch_capa.patch new file mode 100644 index 0000000..78aa945 --- /dev/null +++ b/kvm-target-i386-add-compatibility-property-for-arch_capa.patch @@ -0,0 +1,135 @@ +From ae1b11511be8c6ea7ac3b6dc46e106bb19829b0f Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Thu, 9 Oct 2025 16:49:59 +0200 +Subject: [PATCH 3/4] target/i386: add compatibility property for + arch_capabilities + +RH-Author: Paolo Bonzini +RH-MergeRequest: 411: fix x86-64 migration regression in QEMU 10.1 +RH-Jira: RHEL-120253 +RH-Acked-by: Miroslav Rezanina +RH-Commit: [1/2] 6bfa7c38398623ac7c3392c0ad17312e6f641f4d (bonzini/qemu-kvm-centos) + +JIRA: https://issues.redhat.com/browse/RHEL-120253 + +Prior to v10.1, if requested by user, arch-capabilities is always on +despite the fact that CPUID advertises it to be off/unvailable. +This causes a migration issue for VMs that are run on a machine +without arch-capabilities and expect this feature to be present +on the destination host with QEMU 10.1. + +Add a compatibility property to restore the legacy behavior for all +machines with version prior to 10.1. + +To preserve the functionality (added by 10.1) of turning off +ARCH_CAPABILITIES where Windows does not like it, use directly +the guest CPU vendor: x86_cpu_get_supported_feature_word is not +KVM-specific and therefore should not necessarily use the host +CPUID. + +Co-authored-by: Hector Cao +Signed-off-by: Hector Cao +Fixes: d3a24134e37 ("target/i386: do not expose ARCH_CAPABILITIES on AMD CPU", 2025-07-17) +Signed-off-by: Paolo Bonzini +(cherry picked from commit e9efa4a77168ac2816bf9471f878252ce6224710) +Signed-off-by: Paolo Bonzini +--- + hw/i386/pc.c | 2 ++ + target/i386/cpu.c | 17 +++++++++++++++++ + target/i386/cpu.h | 6 ++++++ + target/i386/kvm/kvm.c | 6 +----- + 4 files changed, 26 insertions(+), 5 deletions(-) + +diff --git a/hw/i386/pc.c b/hw/i386/pc.c +index 439abe8f46..625a89d097 100644 +--- a/hw/i386/pc.c ++++ b/hw/i386/pc.c +@@ -84,6 +84,7 @@ + GlobalProperty pc_compat_10_0[] = { + { TYPE_X86_CPU, "x-consistent-cache", "false" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, ++ { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, + }; + const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); + +@@ -299,6 +300,7 @@ GlobalProperty pc_rhel_10_2_compat[] = { + /* pc_rhel_10_2_compat from pc_compat_10_0 */ + { TYPE_X86_CPU, "x-consistent-cache", "false" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, ++ { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, + }; + const size_t pc_rhel_10_2_compat_len = G_N_ELEMENTS(pc_compat_10_0); + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index 9c756a05f2..de288dc5ac 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -7559,6 +7559,20 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) + #endif + break; + ++ case FEAT_7_0_EDX: ++ /* ++ * Windows does not like ARCH_CAPABILITIES on AMD machines at all. ++ * Do not show the fake ARCH_CAPABILITIES MSR that KVM sets up, ++ * except if needed for migration. ++ * ++ * When arch_cap_always_on is removed, this tweak can move to ++ * kvm_arch_get_supported_cpuid. ++ */ ++ if (cpu && IS_AMD_CPU(&cpu->env) && !cpu->arch_cap_always_on) { ++ unavail = CPUID_7_0_EDX_ARCH_CAPABILITIES; ++ } ++ break; ++ + default: + break; + } +@@ -10024,6 +10038,9 @@ static const Property x86_cpu_properties[] = { + true), + DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), + DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false), ++ ++ DEFINE_PROP_BOOL("x-arch-cap-always-on", X86CPU, ++ arch_cap_always_on, false), + }; + + #ifndef CONFIG_USER_ONLY +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index f977fc49a7..b966bc997c 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -2314,6 +2314,12 @@ struct ArchCPU { + /* Forcefully disable KVM PV features not exposed in guest CPUIDs */ + bool kvm_pv_enforce_cpuid; + ++ /* ++ * Expose arch-capabilities unconditionally even on AMD models, for backwards ++ * compatibility with QEMU <10.1. ++ */ ++ bool arch_cap_always_on; ++ + /* Number of physical address bits supported */ + uint32_t phys_bits; + +diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c +index 0eb39d22d6..baa2f80beb 100644 +--- a/target/i386/kvm/kvm.c ++++ b/target/i386/kvm/kvm.c +@@ -503,12 +503,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, + * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts. + * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is + * returned by KVM_GET_MSR_INDEX_LIST. +- * +- * But also, because Windows does not like ARCH_CAPABILITIES on AMD +- * mcahines at all, do not show the fake ARCH_CAPABILITIES MSR that +- * KVM sets up. + */ +- if (!has_msr_arch_capabs || !(edx & CPUID_7_0_EDX_ARCH_CAPABILITIES)) { ++ if (!has_msr_arch_capabs) { + ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES; + } + } else if (function == 7 && index == 1 && reg == R_EAX) { +-- +2.47.3 + diff --git a/kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch b/kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch new file mode 100644 index 0000000..dfd644c --- /dev/null +++ b/kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch @@ -0,0 +1,115 @@ +From 0d2ec98960c89003d3040818b5c5493cd636b98d Mon Sep 17 00:00:00 2001 +From: Hector Cao +Date: Tue, 23 Sep 2025 12:16:41 +0200 +Subject: [PATCH 4/4] target/i386: add compatibility property for pdcm feature + +RH-Author: Paolo Bonzini +RH-MergeRequest: 411: fix x86-64 migration regression in QEMU 10.1 +RH-Jira: RHEL-120253 +RH-Acked-by: Miroslav Rezanina +RH-Commit: [2/2] 9d76b45215d7ae2bc5ea2e61fe01780059d6d44c (bonzini/qemu-kvm-centos) + +JIRA: https://issues.redhat.com/browse/RHEL-120253 + +The pdcm feature is supposed to be disabled when PMU is not +available. Up until v10.1, pdcm feature is enabled even when PMU +is off. This behavior has been fixed but this change breaks the +migration of VMs that are run with QEMU < 10.0 and expect the pdcm +feature to be enabled on the destination host. + +This commit restores the legacy behavior for machines with version +prior to 10.1 to allow the migration from older QEMU to QEMU 10.1. + +Signed-off-by: Hector Cao +Link: https://lore.kernel.org/r/20250910115733.21149-3-hector.cao@canonical.com +Fixes: e68ec298090 ("i386/cpu: Move adjustment of CPUID_EXT_PDCM before feature_dependencies[] check", 2025-06-20) +[Move property from migration object to CPU. - Paolo] +Signed-off-by: Paolo Bonzini +(cherry picked from commit 6529f31e0dccadb532c80b36e3efe7aef83f9cad) +Signed-off-by: Paolo Bonzini +--- + hw/i386/pc.c | 2 ++ + target/i386/cpu.c | 15 ++++++++++++--- + target/i386/cpu.h | 6 ++++++ + 3 files changed, 20 insertions(+), 3 deletions(-) + +diff --git a/hw/i386/pc.c b/hw/i386/pc.c +index 625a89d097..446d4a7c93 100644 +--- a/hw/i386/pc.c ++++ b/hw/i386/pc.c +@@ -85,6 +85,7 @@ GlobalProperty pc_compat_10_0[] = { + { TYPE_X86_CPU, "x-consistent-cache", "false" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, + { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, ++ { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" }, + }; + const size_t pc_compat_10_0_len = G_N_ELEMENTS(pc_compat_10_0); + +@@ -301,6 +302,7 @@ GlobalProperty pc_rhel_10_2_compat[] = { + { TYPE_X86_CPU, "x-consistent-cache", "false" }, + { TYPE_X86_CPU, "x-vendor-cpuid-only-v2", "false" }, + { TYPE_X86_CPU, "x-arch-cap-always-on", "true" }, ++ { TYPE_X86_CPU, "x-pdcm-on-even-without-pmu", "true" }, + }; + const size_t pc_rhel_10_2_compat_len = G_N_ELEMENTS(pc_compat_10_0); + +diff --git a/target/i386/cpu.c b/target/i386/cpu.c +index de288dc5ac..dfcdfd3da6 100644 +--- a/target/i386/cpu.c ++++ b/target/i386/cpu.c +@@ -7928,6 +7928,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, + /* Fixup overflow: max value for bits 23-16 is 255. */ + *ebx |= MIN(num, 255) << 16; + } ++ if (cpu->pdcm_on_even_without_pmu) { ++ if (!cpu->enable_pmu) { ++ *ecx &= ~CPUID_EXT_PDCM; ++ } ++ } + break; + case 2: { /* cache info: needed for Pentium Pro compatibility */ + const CPUCaches *caches; +@@ -8978,9 +8983,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp) + } + } + +- /* PDCM is fixed1 bit for TDX */ +- if (!cpu->enable_pmu && !is_tdx_vm()) { +- env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; ++ if (!cpu->pdcm_on_even_without_pmu) { ++ /* PDCM is fixed1 bit for TDX */ ++ if (!cpu->enable_pmu && !is_tdx_vm()) { ++ env->features[FEAT_1_ECX] &= ~CPUID_EXT_PDCM; ++ } + } + + for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { +@@ -10041,6 +10048,8 @@ static const Property x86_cpu_properties[] = { + + DEFINE_PROP_BOOL("x-arch-cap-always-on", X86CPU, + arch_cap_always_on, false), ++ DEFINE_PROP_BOOL("x-pdcm-on-even-without-pmu", X86CPU, ++ pdcm_on_even_without_pmu, false), + }; + + #ifndef CONFIG_USER_ONLY +diff --git a/target/i386/cpu.h b/target/i386/cpu.h +index b966bc997c..2187e61654 100644 +--- a/target/i386/cpu.h ++++ b/target/i386/cpu.h +@@ -2320,6 +2320,12 @@ struct ArchCPU { + */ + bool arch_cap_always_on; + ++ /* ++ * Backwards compatibility with QEMU <10.1. The PDCM feature is now disabled when ++ * PMU is not available, but prior to 10.1 it was enabled even if PMU is off. ++ */ ++ bool pdcm_on_even_without_pmu; ++ + /* Number of physical address bits supported */ + uint32_t phys_bits; + +-- +2.47.3 + diff --git a/qemu-kvm.spec b/qemu-kvm.spec index ae196e6..d336d81 100644 --- a/qemu-kvm.spec +++ b/qemu-kvm.spec @@ -143,7 +143,7 @@ Obsoletes: %{name}-block-ssh <= %{epoch}:%{version} \ Summary: QEMU is a machine emulator and virtualizer Name: qemu-kvm Version: 10.1.0 -Release: 2%{?rcrel}%{?dist}%{?cc_suffix} +Release: 3%{?rcrel}%{?dist}%{?cc_suffix} # Epoch because we pushed a qemu-1.0 package. AIUI this can't ever be dropped # Epoch 15 used for RHEL 8 # Epoch 17 used for RHEL 9 (due to release versioning offset in RHEL 8.5) @@ -188,6 +188,14 @@ Patch0020: 0020-qcow2-Deprecation-warning-when-opening-v2-images-rw.patch Patch0021: 0021-file-posix-Define-DM_MPATH_PROBE_PATHS.patch # For RHEL-112882 - [DEV Task]: Assertion `core->delayed_causes == 0' failed with e1000e NIC Patch22: kvm-e1000e-Prevent-crash-from-legacy-interrupt-firing-af.patch +# For RHEL-119368 - [rhel10] Backport "arm/kvm: report registers we failed to set" +Patch23: kvm-arm-kvm-report-registers-we-failed-to-set.patch +# For RHEL-116443 - qemu crash after hot-unplug disk from the multifunction enabled bus,crash point PCIDevice *vf = dev->exp.sriov_pf.vf[i] +Patch24: kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch +# For RHEL-120253 - Backport fixes for PDCM and ARCH_CAPABILITIES migration incompatibility +Patch25: kvm-target-i386-add-compatibility-property-for-arch_capa.patch +# For RHEL-120253 - Backport fixes for PDCM and ARCH_CAPABILITIES migration incompatibility +Patch26: kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch %if %{have_clang} BuildRequires: clang @@ -1267,6 +1275,18 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \ %endif %changelog +* Mon Oct 20 2025 Miroslav Rezanina - 10.1.0-3 +- kvm-arm-kvm-report-registers-we-failed-to-set.patch [RHEL-119368] +- kvm-pcie_sriov-make-pcie_sriov_pf_exit-safe-on-non-SR-IO.patch [RHEL-116443] +- kvm-target-i386-add-compatibility-property-for-arch_capa.patch [RHEL-120253] +- kvm-target-i386-add-compatibility-property-for-pdcm-feat.patch [RHEL-120253] +- Resolves: RHEL-119368 + ([rhel10] Backport "arm/kvm: report registers we failed to set") +- Resolves: RHEL-116443 + (qemu crash after hot-unplug disk from the multifunction enabled bus,crash point PCIDevice *vf = dev->exp.sriov_pf.vf[i]) +- Resolves: RHEL-120253 + (Backport fixes for PDCM and ARCH_CAPABILITIES migration incompatibility) + * Mon Sep 15 2025 Miroslav Rezanina - 10.1.0-2 - kvm-e1000e-Prevent-crash-from-legacy-interrupt-firing-af.patch [RHEL-112882] - Resolves: RHEL-112882