From 32e2137667c0fc654437bdea069e6bfa86b873eb Mon Sep 17 00:00:00 2001 From: Miroslav Rezanina Date: Mon, 20 Mar 2023 01:59:30 -0400 Subject: [PATCH] * Mon Mar 20 2023 Miroslav Rezanina - 7.2.0-13 - kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch [bz#2173590] - kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch [bz#2173590] - kvm-target-i386-Fix-BEXTR-instruction.patch [bz#2173590] - kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch [bz#2173590] - kvm-target-i386-fix-ADOX-followed-by-ADCX.patch [bz#2173590] - kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch [bz#2173590] - kvm-target-i386-Fix-BZHI-instruction.patch [bz#2173590] - kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch [bz#2156876] - Resolves: bz#2173590 (bugs in emulation of BMI instructions (for libguestfs without KVM)) - Resolves: bz#2156876 ([virtual network][rhel7.9_guest] qemu-kvm: vhost vring error in virtqueue 1: Invalid argument (22)) --- ...-fail-DEVIOTLB_UNMAP-without-dt-mode.patch | 64 ++++ ...-32-bit-AD-CO-X-insns-in-64-bit-mode.patch | 144 +++++++++ kvm-target-i386-Fix-BEXTR-instruction.patch | 110 +++++++ kvm-target-i386-Fix-BZHI-instruction.patch | 77 +++++ ...i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch | 60 ++++ ...arget-i386-fix-ADOX-followed-by-ADCX.patch | 205 ++++++++++++ ...operand-size-of-unary-SSE-operations.patch | 77 +++++ ...Introduce-and-use-reg_t-consistently.patch | 299 ++++++++++++++++++ qemu-kvm.spec | 32 +- 9 files changed, 1067 insertions(+), 1 deletion(-) create mode 100644 kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch create mode 100644 kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch create mode 100644 kvm-target-i386-Fix-BEXTR-instruction.patch create mode 100644 kvm-target-i386-Fix-BZHI-instruction.patch create mode 100644 kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch create mode 100644 kvm-target-i386-fix-ADOX-followed-by-ADCX.patch create mode 100644 kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch create mode 100644 kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch diff --git a/kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch b/kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch new file mode 100644 index 0000000..0f321e4 --- /dev/null +++ b/kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch @@ -0,0 +1,64 @@ +From cadcc1c6a001622d971c86d44925516905e3d104 Mon Sep 17 00:00:00 2001 +From: Jason Wang +Date: Thu, 23 Feb 2023 14:59:21 +0800 +Subject: [PATCH 8/8] intel-iommu: fail DEVIOTLB_UNMAP without dt mode + +RH-Author: Laurent Vivier +RH-MergeRequest: 157: intel-iommu: fail DEVIOTLB_UNMAP without dt mode +RH-Bugzilla: 2156876 +RH-Acked-by: Eric Auger +RH-Acked-by: Peter Xu +RH-Acked-by: MST +RH-Commit: [1/1] eb9dbae6140ef4ba10d90b9e66abd75540f6892d (lvivier/qemu-kvm-centos) + +Without dt mode, device IOTLB notifier won't work since guest won't +send device IOTLB invalidation descriptor in this case. Let's fail +early instead of misbehaving silently. + +Reviewed-by: Laurent Vivier +Tested-by: Laurent Vivier +Tested-by: Viktor Prutyanov +Buglink: https://bugzilla.redhat.com/2156876 +Signed-off-by: Jason Wang +Message-Id: <20230223065924.42503-3-jasowang@redhat.com> +Reviewed-by: Peter Xu +Reviewed-by: Michael S. Tsirkin +Signed-off-by: Michael S. Tsirkin +(cherry picked from commit 09adb0e021207b60a0c51a68939b4539d98d3ef3) + +Conflict in hw/i386/intel_iommu.c because of missing commit: + + 4ce27463ccce ("intel-iommu: fail MAP notifier without caching mode") +--- + hw/i386/intel_iommu.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c +index a08ee85edf..d2983f40d3 100644 +--- a/hw/i386/intel_iommu.c ++++ b/hw/i386/intel_iommu.c +@@ -3179,6 +3179,7 @@ static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, + { + VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); + IntelIOMMUState *s = vtd_as->iommu_state; ++ X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s); + + /* TODO: add support for VFIO and vhost users */ + if (s->snoop_control) { +@@ -3186,6 +3187,13 @@ static int vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, + "Snoop Control with vhost or VFIO is not supported"); + return -ENOTSUP; + } ++ if (!x86_iommu->dt_supported && (new & IOMMU_NOTIFIER_DEVIOTLB_UNMAP)) { ++ error_setg_errno(errp, ENOTSUP, ++ "device %02x.%02x.%x requires device IOTLB mode", ++ pci_bus_num(vtd_as->bus), PCI_SLOT(vtd_as->devfn), ++ PCI_FUNC(vtd_as->devfn)); ++ return -ENOTSUP; ++ } + + /* Update per-address-space notifier flags */ + vtd_as->notifier_flags = new; +-- +2.39.1 + diff --git a/kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch b/kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch new file mode 100644 index 0000000..52e73e7 --- /dev/null +++ b/kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch @@ -0,0 +1,144 @@ +From e419493e6ec188461aa6f06c1b1cdc8a698859df Mon Sep 17 00:00:00 2001 +From: Richard Henderson +Date: Sat, 14 Jan 2023 15:21:03 -1000 +Subject: [PATCH 6/8] target/i386: Fix 32-bit AD[CO]X insns in 64-bit mode +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [6/7] 0fa4d3858319d4f877a5b3f31776121a72e2c57a (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +Failure to truncate the inputs results in garbage for the carry-out. + +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1373 +Signed-off-by: Richard Henderson +Reviewed-by: Philippe Mathieu-Daudé +Message-Id: <20230115012103.3131796-1-richard.henderson@linaro.org> +Signed-off-by: Paolo Bonzini +(cherry picked from commit 6fbef9426bac7184b5d5887589d8386e732865eb) +--- + target/i386/tcg/emit.c.inc | 2 + + tests/tcg/x86_64/Makefile.target | 3 ++ + tests/tcg/x86_64/adox.c | 69 ++++++++++++++++++++++++++++++++ + 3 files changed, 74 insertions(+) + create mode 100644 tests/tcg/x86_64/adox.c + +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index 0d7c6e80ae..e61ae9a2e9 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1037,6 +1037,8 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op) + #ifdef TARGET_X86_64 + case MO_32: + /* If TL is 64-bit just do everything in 64-bit arithmetic. */ ++ tcg_gen_ext32u_tl(s->T0, s->T0); ++ tcg_gen_ext32u_tl(s->T1, s->T1); + tcg_gen_add_i64(s->T0, s->T0, s->T1); + tcg_gen_add_i64(s->T0, s->T0, carry_in); + tcg_gen_shri_i64(carry_out, s->T0, 32); +diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target +index 4eac78293f..e64aab1b81 100644 +--- a/tests/tcg/x86_64/Makefile.target ++++ b/tests/tcg/x86_64/Makefile.target +@@ -12,11 +12,14 @@ ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET)) + X86_64_TESTS += vsyscall + X86_64_TESTS += noexec + X86_64_TESTS += cmpxchg ++X86_64_TESTS += adox + TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 + else + TESTS=$(MULTIARCH_TESTS) + endif + ++adox: CFLAGS=-O2 ++ + run-test-i386-ssse3: QEMU_OPTS += -cpu max + run-plugin-test-i386-ssse3-%: QEMU_OPTS += -cpu max + +diff --git a/tests/tcg/x86_64/adox.c b/tests/tcg/x86_64/adox.c +new file mode 100644 +index 0000000000..36be644c8b +--- /dev/null ++++ b/tests/tcg/x86_64/adox.c +@@ -0,0 +1,69 @@ ++/* See if ADOX give expected results */ ++ ++#include ++#include ++#include ++ ++static uint64_t adoxq(bool *c_out, uint64_t a, uint64_t b, bool c) ++{ ++ asm ("addl $0x7fffffff, %k1\n\t" ++ "adoxq %2, %0\n\t" ++ "seto %b1" ++ : "+r"(a), "=&r"(c) : "r"(b), "1"((int)c)); ++ *c_out = c; ++ return a; ++} ++ ++static uint64_t adoxl(bool *c_out, uint64_t a, uint64_t b, bool c) ++{ ++ asm ("addl $0x7fffffff, %k1\n\t" ++ "adoxl %k2, %k0\n\t" ++ "seto %b1" ++ : "+r"(a), "=&r"(c) : "r"(b), "1"((int)c)); ++ *c_out = c; ++ return a; ++} ++ ++int main() ++{ ++ uint64_t r; ++ bool c; ++ ++ r = adoxq(&c, 0, 0, 0); ++ assert(r == 0); ++ assert(c == 0); ++ ++ r = adoxl(&c, 0, 0, 0); ++ assert(r == 0); ++ assert(c == 0); ++ ++ r = adoxl(&c, 0x100000000, 0, 0); ++ assert(r == 0); ++ assert(c == 0); ++ ++ r = adoxq(&c, 0, 0, 1); ++ assert(r == 1); ++ assert(c == 0); ++ ++ r = adoxl(&c, 0, 0, 1); ++ assert(r == 1); ++ assert(c == 0); ++ ++ r = adoxq(&c, -1, -1, 0); ++ assert(r == -2); ++ assert(c == 1); ++ ++ r = adoxl(&c, -1, -1, 0); ++ assert(r == 0xfffffffe); ++ assert(c == 1); ++ ++ r = adoxq(&c, -1, -1, 1); ++ assert(r == -1); ++ assert(c == 1); ++ ++ r = adoxl(&c, -1, -1, 1); ++ assert(r == 0xffffffff); ++ assert(c == 1); ++ ++ return 0; ++} +-- +2.39.1 + diff --git a/kvm-target-i386-Fix-BEXTR-instruction.patch b/kvm-target-i386-Fix-BEXTR-instruction.patch new file mode 100644 index 0000000..0c28c7e --- /dev/null +++ b/kvm-target-i386-Fix-BEXTR-instruction.patch @@ -0,0 +1,110 @@ +From a019c203f0148e5fbb20e102a17453806f5296b6 Mon Sep 17 00:00:00 2001 +From: Richard Henderson +Date: Sat, 14 Jan 2023 13:05:42 -1000 +Subject: [PATCH 3/8] target/i386: Fix BEXTR instruction + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [3/7] bd1e3b26c72d7152b44be2d34308fd40dc106424 (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +There were two problems here: not limiting the input to operand bits, +and not correctly handling large extraction length. + +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1372 +Signed-off-by: Richard Henderson +Message-Id: <20230114230542.3116013-3-richard.henderson@linaro.org> +Cc: qemu-stable@nongnu.org +Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) +Signed-off-by: Paolo Bonzini +(cherry picked from commit b14c0098975264ed03144f145bca0179a6763a07) +--- + target/i386/tcg/emit.c.inc | 22 +++++++++++----------- + tests/tcg/i386/test-i386-bmi2.c | 12 ++++++++++++ + 2 files changed, 23 insertions(+), 11 deletions(-) + +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index 7037ff91c6..99f6ba6e19 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1078,30 +1078,30 @@ static void gen_ANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + static void gen_BEXTR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { + MemOp ot = decode->op[0].ot; +- TCGv bound, zero; ++ TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); ++ TCGv zero = tcg_constant_tl(0); ++ TCGv mone = tcg_constant_tl(-1); + + /* + * Extract START, and shift the operand. + * Shifts larger than operand size get zeros. + */ + tcg_gen_ext8u_tl(s->A0, s->T1); ++ if (TARGET_LONG_BITS == 64 && ot == MO_32) { ++ tcg_gen_ext32u_tl(s->T0, s->T0); ++ } + tcg_gen_shr_tl(s->T0, s->T0, s->A0); + +- bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); +- zero = tcg_constant_tl(0); + tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero); + + /* +- * Extract the LEN into a mask. Lengths larger than +- * operand size get all ones. ++ * Extract the LEN into an inverse mask. Lengths larger than ++ * operand size get all zeros, length 0 gets all ones. + */ + tcg_gen_extract_tl(s->A0, s->T1, 8, 8); +- tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->A0, bound, s->A0, bound); +- +- tcg_gen_movi_tl(s->T1, 1); +- tcg_gen_shl_tl(s->T1, s->T1, s->A0); +- tcg_gen_subi_tl(s->T1, s->T1, 1); +- tcg_gen_and_tl(s->T0, s->T0, s->T1); ++ tcg_gen_shl_tl(s->T1, mone, s->A0); ++ tcg_gen_movcond_tl(TCG_COND_LEU, s->T1, s->A0, bound, s->T1, zero); ++ tcg_gen_andc_tl(s->T0, s->T0, s->T1); + + gen_op_update1_cc(s); + set_cc_op(s, CC_OP_LOGICB + ot); +diff --git a/tests/tcg/i386/test-i386-bmi2.c b/tests/tcg/i386/test-i386-bmi2.c +index 3c3ef85513..982d4abda4 100644 +--- a/tests/tcg/i386/test-i386-bmi2.c ++++ b/tests/tcg/i386/test-i386-bmi2.c +@@ -99,6 +99,9 @@ int main(int argc, char *argv[]) { + result = bextrq(mask, 0x10f8); + assert(result == 0); + ++ result = bextrq(0xfedcba9876543210ull, 0x7f00); ++ assert(result == 0xfedcba9876543210ull); ++ + result = blsiq(0x30); + assert(result == 0x10); + +@@ -164,6 +167,15 @@ int main(int argc, char *argv[]) { + result = bextrl(mask, 0x1038); + assert(result == 0); + ++ result = bextrl((reg_t)0x8f635a775ad3b9b4ull, 0x3018); ++ assert(result == 0x5a); ++ ++ result = bextrl((reg_t)0xfedcba9876543210ull, 0x7f00); ++ assert(result == 0x76543210u); ++ ++ result = bextrl(-1, 0); ++ assert(result == 0); ++ + result = blsil(0xffff); + assert(result == 1); + +-- +2.39.1 + diff --git a/kvm-target-i386-Fix-BZHI-instruction.patch b/kvm-target-i386-Fix-BZHI-instruction.patch new file mode 100644 index 0000000..bcf79f4 --- /dev/null +++ b/kvm-target-i386-Fix-BZHI-instruction.patch @@ -0,0 +1,77 @@ +From d49e5d193dfccf6f5cfa98ccce5bd491478d563d Mon Sep 17 00:00:00 2001 +From: Richard Henderson +Date: Sat, 14 Jan 2023 13:32:06 -1000 +Subject: [PATCH 7/8] target/i386: Fix BZHI instruction + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [7/7] ad6b343c09c0304ac32cc68670c49d1fc12d8cf8 (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +We did not correctly handle N >= operand size. + +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1374 +Signed-off-by: Richard Henderson +Message-Id: <20230114233206.3118472-1-richard.henderson@linaro.org> +Signed-off-by: Paolo Bonzini +(cherry picked from commit 9ad2ba6e8e7fc195d0dd0b76ab38bd2fceb1bdd4) +--- + target/i386/tcg/emit.c.inc | 14 +++++++------- + tests/tcg/i386/test-i386-bmi2.c | 3 +++ + 2 files changed, 10 insertions(+), 7 deletions(-) + +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index e61ae9a2e9..0d01e13002 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1147,20 +1147,20 @@ static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + static void gen_BZHI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { + MemOp ot = decode->op[0].ot; +- TCGv bound; ++ TCGv bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); ++ TCGv zero = tcg_constant_tl(0); ++ TCGv mone = tcg_constant_tl(-1); + +- tcg_gen_ext8u_tl(s->T1, cpu_regs[s->vex_v]); +- bound = tcg_constant_tl(ot == MO_64 ? 63 : 31); ++ tcg_gen_ext8u_tl(s->T1, s->T1); + + /* + * Note that since we're using BMILG (in order to get O + * cleared) we need to store the inverse into C. + */ +- tcg_gen_setcond_tl(TCG_COND_LT, cpu_cc_src, s->T1, bound); +- tcg_gen_movcond_tl(TCG_COND_GT, s->T1, s->T1, bound, bound, s->T1); ++ tcg_gen_setcond_tl(TCG_COND_LEU, cpu_cc_src, s->T1, bound); + +- tcg_gen_movi_tl(s->A0, -1); +- tcg_gen_shl_tl(s->A0, s->A0, s->T1); ++ tcg_gen_shl_tl(s->A0, mone, s->T1); ++ tcg_gen_movcond_tl(TCG_COND_LEU, s->A0, s->T1, bound, s->A0, zero); + tcg_gen_andc_tl(s->T0, s->T0, s->A0); + + gen_op_update1_cc(s); +diff --git a/tests/tcg/i386/test-i386-bmi2.c b/tests/tcg/i386/test-i386-bmi2.c +index 982d4abda4..0244df7987 100644 +--- a/tests/tcg/i386/test-i386-bmi2.c ++++ b/tests/tcg/i386/test-i386-bmi2.c +@@ -123,6 +123,9 @@ int main(int argc, char *argv[]) { + result = bzhiq(mask, 0x1f); + assert(result == (mask & ~(-1 << 30))); + ++ result = bzhiq(mask, 0x40); ++ assert(result == mask); ++ + result = rorxq(0x2132435465768798, 8); + assert(result == 0x9821324354657687); + +-- +2.39.1 + diff --git a/kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch b/kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch new file mode 100644 index 0000000..7f3051f --- /dev/null +++ b/kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch @@ -0,0 +1,60 @@ +From cb2b591e1677db2837810eaedac534a7ff3a7b1c Mon Sep 17 00:00:00 2001 +From: Richard Henderson +Date: Sat, 14 Jan 2023 08:06:01 -1000 +Subject: [PATCH 4/8] target/i386: Fix C flag for BLSI, BLSMSK, BLSR + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [4/7] 173e23c492c830da6c5a4be0cfc20a69ac655b59 (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +We forgot to set cc_src, which is used for computing C. + +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1370 +Signed-off-by: Richard Henderson +Message-Id: <20230114180601.2993644-1-richard.henderson@linaro.org> +Cc: qemu-stable@nongnu.org +Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) +Signed-off-by: Paolo Bonzini +(cherry picked from commit 99282098dc74c2055bde5652bde6cf0067d0c370) +--- + target/i386/tcg/emit.c.inc | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index 99f6ba6e19..4d7702c106 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1111,6 +1111,7 @@ static void gen_BLSI(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { + MemOp ot = decode->op[0].ot; + ++ tcg_gen_mov_tl(cpu_cc_src, s->T0); + tcg_gen_neg_tl(s->T1, s->T0); + tcg_gen_and_tl(s->T0, s->T0, s->T1); + tcg_gen_mov_tl(cpu_cc_dst, s->T0); +@@ -1121,6 +1122,7 @@ static void gen_BLSMSK(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode + { + MemOp ot = decode->op[0].ot; + ++ tcg_gen_mov_tl(cpu_cc_src, s->T0); + tcg_gen_subi_tl(s->T1, s->T0, 1); + tcg_gen_xor_tl(s->T0, s->T0, s->T1); + tcg_gen_mov_tl(cpu_cc_dst, s->T0); +@@ -1131,6 +1133,7 @@ static void gen_BLSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) + { + MemOp ot = decode->op[0].ot; + ++ tcg_gen_mov_tl(cpu_cc_src, s->T0); + tcg_gen_subi_tl(s->T1, s->T0, 1); + tcg_gen_and_tl(s->T0, s->T0, s->T1); + tcg_gen_mov_tl(cpu_cc_dst, s->T0); +-- +2.39.1 + diff --git a/kvm-target-i386-fix-ADOX-followed-by-ADCX.patch b/kvm-target-i386-fix-ADOX-followed-by-ADCX.patch new file mode 100644 index 0000000..72ae8ee --- /dev/null +++ b/kvm-target-i386-fix-ADOX-followed-by-ADCX.patch @@ -0,0 +1,205 @@ +From 54d3e58aabf9716f9a07aeb7044d7b7997e28123 Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Tue, 31 Jan 2023 09:48:03 +0100 +Subject: [PATCH 5/8] target/i386: fix ADOX followed by ADCX + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [5/7] 64dbe4e602f08e4a88fdeacee5a8993ca4383563 (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +When ADCX is followed by ADOX or vice versa, the second instruction's +carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX +operation. Retrieving the carry from EFLAGS is handled by this bit +of gen_ADCOX: + + tcg_gen_extract_tl(carry_in, cpu_cc_src, + ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1); + +Unfortunately, in this case cc_op has been overwritten by the previous +"if" statement to CC_OP_ADCOX. This works by chance when the first +instruction is ADCX; however, if the first instruction is ADOX, +ADCX will incorrectly take its carry from OF instead of CF. + +Fix by moving the computation of the new cc_op at the end of the function. +The included exhaustive test case fails without this patch and passes +afterwards. + +Because ADCX/ADOX need not be invoked through the VEX prefix, this +regression bisects to commit 16fc5726a6e2 ("target/i386: reimplement +0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a +little earlier, when BMI instructions were rewritten using the new +decoder framework. + +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471 +Reported-by: Paul Jolly +Fixes: 1d0b926150e5 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18) +Cc: qemu-stable@nongnu.org +Signed-off-by: Paolo Bonzini +(cherry picked from commit 60c7dd22e1383754d5f150bc9f7c2785c662a7b6) +--- + target/i386/tcg/emit.c.inc | 20 +++++---- + tests/tcg/i386/Makefile.target | 6 ++- + tests/tcg/i386/test-i386-adcox.c | 75 ++++++++++++++++++++++++++++++++ + 3 files changed, 91 insertions(+), 10 deletions(-) + create mode 100644 tests/tcg/i386/test-i386-adcox.c + +diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc +index 4d7702c106..0d7c6e80ae 100644 +--- a/target/i386/tcg/emit.c.inc ++++ b/target/i386/tcg/emit.c.inc +@@ -1015,6 +1015,7 @@ VSIB_AVX(VPGATHERQ, vpgatherq) + + static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op) + { ++ int opposite_cc_op; + TCGv carry_in = NULL; + TCGv carry_out = (cc_op == CC_OP_ADCX ? cpu_cc_dst : cpu_cc_src2); + TCGv zero; +@@ -1022,14 +1023,8 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op) + if (cc_op == s->cc_op || s->cc_op == CC_OP_ADCOX) { + /* Re-use the carry-out from a previous round. */ + carry_in = carry_out; +- cc_op = s->cc_op; +- } else if (s->cc_op == CC_OP_ADCX || s->cc_op == CC_OP_ADOX) { +- /* Merge with the carry-out from the opposite instruction. */ +- cc_op = CC_OP_ADCOX; +- } +- +- /* If we don't have a carry-in, get it out of EFLAGS. */ +- if (!carry_in) { ++ } else { ++ /* We don't have a carry-in, get it out of EFLAGS. */ + if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) { + gen_compute_eflags(s); + } +@@ -1053,7 +1048,14 @@ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_op) + tcg_gen_add2_tl(s->T0, carry_out, s->T0, carry_out, s->T1, zero); + break; + } +- set_cc_op(s, cc_op); ++ ++ opposite_cc_op = cc_op == CC_OP_ADCX ? CC_OP_ADOX : CC_OP_ADCX; ++ if (s->cc_op == CC_OP_ADCOX || s->cc_op == opposite_cc_op) { ++ /* Merge with the carry-out from the opposite instruction. */ ++ set_cc_op(s, CC_OP_ADCOX); ++ } else { ++ set_cc_op(s, cc_op); ++ } + } + + static void gen_ADCX(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) +diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target +index 81831cafbc..bafd8c2180 100644 +--- a/tests/tcg/i386/Makefile.target ++++ b/tests/tcg/i386/Makefile.target +@@ -14,7 +14,7 @@ config-cc.mak: Makefile + I386_SRCS=$(notdir $(wildcard $(I386_SRC)/*.c)) + ALL_X86_TESTS=$(I386_SRCS:.c=) + SKIP_I386_TESTS=test-i386-ssse3 test-avx test-3dnow test-mmx +-X86_64_TESTS:=$(filter test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS)) ++X86_64_TESTS:=$(filter test-i386-adcox test-i386-bmi2 $(SKIP_I386_TESTS), $(ALL_X86_TESTS)) + + test-i386-sse-exceptions: CFLAGS += -msse4.1 -mfpmath=sse + run-test-i386-sse-exceptions: QEMU_OPTS += -cpu max +@@ -28,6 +28,10 @@ test-i386-bmi2: CFLAGS=-O2 + run-test-i386-bmi2: QEMU_OPTS += -cpu max + run-plugin-test-i386-bmi2-%: QEMU_OPTS += -cpu max + ++test-i386-adcox: CFLAGS=-O2 ++run-test-i386-adcox: QEMU_OPTS += -cpu max ++run-plugin-test-i386-adcox-%: QEMU_OPTS += -cpu max ++ + # + # hello-i386 is a barebones app + # +diff --git a/tests/tcg/i386/test-i386-adcox.c b/tests/tcg/i386/test-i386-adcox.c +new file mode 100644 +index 0000000000..16169efff8 +--- /dev/null ++++ b/tests/tcg/i386/test-i386-adcox.c +@@ -0,0 +1,75 @@ ++/* See if various BMI2 instructions give expected results */ ++#include ++#include ++#include ++ ++#define CC_C 1 ++#define CC_O (1 << 11) ++ ++#ifdef __x86_64__ ++#define REG uint64_t ++#else ++#define REG uint32_t ++#endif ++ ++void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand) ++{ ++ REG flags; ++ REG out_adcx, out_adox; ++ ++ asm("pushf; pop %0" : "=r"(flags)); ++ flags &= ~(CC_C | CC_O); ++ flags |= (in_c ? CC_C : 0); ++ flags |= (in_o ? CC_O : 0); ++ ++ out_adcx = adcx_operand; ++ out_adox = adox_operand; ++ asm("push %0; popf;" ++ "adox %3, %2;" ++ "adcx %3, %1;" ++ "pushf; pop %0" ++ : "+r" (flags), "+r" (out_adcx), "+r" (out_adox) ++ : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox)); ++ ++ assert(out_adcx == in_c + adcx_operand - 1); ++ assert(out_adox == in_o + adox_operand - 1); ++ assert(!!(flags & CC_C) == (in_c || adcx_operand)); ++ assert(!!(flags & CC_O) == (in_o || adox_operand)); ++} ++ ++void test_adcx_adox(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand) ++{ ++ REG flags; ++ REG out_adcx, out_adox; ++ ++ asm("pushf; pop %0" : "=r"(flags)); ++ flags &= ~(CC_C | CC_O); ++ flags |= (in_c ? CC_C : 0); ++ flags |= (in_o ? CC_O : 0); ++ ++ out_adcx = adcx_operand; ++ out_adox = adox_operand; ++ asm("push %0; popf;" ++ "adcx %3, %1;" ++ "adox %3, %2;" ++ "pushf; pop %0" ++ : "+r" (flags), "+r" (out_adcx), "+r" (out_adox) ++ : "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox)); ++ ++ assert(out_adcx == in_c + adcx_operand - 1); ++ assert(out_adox == in_o + adox_operand - 1); ++ assert(!!(flags & CC_C) == (in_c || adcx_operand)); ++ assert(!!(flags & CC_O) == (in_o || adox_operand)); ++} ++ ++int main(int argc, char *argv[]) { ++ /* try all combinations of input CF, input OF, CF from op1+op2, OF from op2+op1 */ ++ int i; ++ for (i = 0; i <= 15; i++) { ++ printf("%d\n", i); ++ test_adcx_adox(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8)); ++ test_adox_adcx(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8)); ++ } ++ return 0; ++} ++ +-- +2.39.1 + diff --git a/kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch b/kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch new file mode 100644 index 0000000..81a0003 --- /dev/null +++ b/kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch @@ -0,0 +1,77 @@ +From f4ddcdd2395e0944c20f6683c66068ed0ac7d757 Mon Sep 17 00:00:00 2001 +From: Paolo Bonzini +Date: Sat, 7 Jan 2023 18:14:20 +0100 +Subject: [PATCH 1/8] target/i386: fix operand size of unary SSE operations + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [1/7] 7041f3e30e19add6bd8e5355d8bebf92390a5c2e (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +VRCPSS, VRSQRTSS and VCVTSx2Sx have a 32-bit or 64-bit memory operand, +which is represented in the decoding tables by X86_VEX_REPScalar. Add it +to the tables, and make validate_vex() handle the case of an instruction +that is in exception type 4 without the REP prefix and exception type 5 +with it; this is the cas of VRCP and VRSQRT. + +Reported-by: yongwoo +Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1377 +Signed-off-by: Paolo Bonzini +(cherry picked from commit 3d304620ec6c95f31db17acc132f42f243369299) +--- + target/i386/tcg/decode-new.c.inc | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc +index 80c579164f..d5fd8d965c 100644 +--- a/target/i386/tcg/decode-new.c.inc ++++ b/target/i386/tcg/decode-new.c.inc +@@ -105,6 +105,7 @@ + #define vex3 .vex_class = 3, + #define vex4 .vex_class = 4, + #define vex4_unal .vex_class = 4, .vex_special = X86_VEX_SSEUnaligned, ++#define vex4_rep5 .vex_class = 4, .vex_special = X86_VEX_REPScalar, + #define vex5 .vex_class = 5, + #define vex6 .vex_class = 6, + #define vex7 .vex_class = 7, +@@ -839,8 +840,8 @@ static const X86OpEntry opcodes_0F[256] = { + + [0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66), + [0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), +- [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3), +- [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex5 p_00_f3), ++ [0x52] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), ++ [0x53] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3), + [0x54] = X86_OP_ENTRY3(PAND, V,x, H,x, W,x, vex4 p_00_66), /* vand */ + [0x55] = X86_OP_ENTRY3(PANDN, V,x, H,x, W,x, vex4 p_00_66), /* vandn */ + [0x56] = X86_OP_ENTRY3(POR, V,x, H,x, W,x, vex4 p_00_66), /* vor */ +@@ -878,7 +879,7 @@ static const X86OpEntry opcodes_0F[256] = { + + [0x58] = X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), + [0x59] = X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), +- [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex3 p_00_66_f3_f2), ++ [0x5a] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), + [0x5b] = X86_OP_GROUP0(0F5B), + [0x5c] = X86_OP_ENTRY3(VSUB, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), + [0x5d] = X86_OP_ENTRY3(VMIN, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), +@@ -1447,9 +1448,9 @@ static bool validate_vex(DisasContext *s, X86DecodedInsn *decode) + * Instructions which differ between 00/66 and F2/F3 in the + * exception classification and the size of the memory operand. + */ +- assert(e->vex_class == 1 || e->vex_class == 2); ++ assert(e->vex_class == 1 || e->vex_class == 2 || e->vex_class == 4); + if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { +- e->vex_class = 3; ++ e->vex_class = e->vex_class < 4 ? 3 : 5; + if (s->vex_l) { + goto illegal; + } +-- +2.39.1 + diff --git a/kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch b/kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch new file mode 100644 index 0000000..14388fe --- /dev/null +++ b/kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch @@ -0,0 +1,299 @@ +From 120db3dfeb88c447f0e115c19b7ede704f8f80cb Mon Sep 17 00:00:00 2001 +From: Richard Henderson +Date: Sat, 14 Jan 2023 13:05:41 -1000 +Subject: [PATCH 2/8] tests/tcg/i386: Introduce and use reg_t consistently +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +RH-Author: Paolo Bonzini +RH-MergeRequest: 154: target/i386: fix bugs in emulation of BMI instructions +RH-Bugzilla: 2173590 +RH-Acked-by: Emanuele Giuseppe Esposito +RH-Acked-by: Vitaly Kuznetsov +RH-Acked-by: Bandan Das +RH-Commit: [2/7] 843a677555414170392db21c828bef3dc3c29300 (bonzini/rhel-qemu-kvm) + +Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2173590 +Upstream-Status: merged + +Define reg_t based on the actual register width. +Define the inlines using that type. This will allow +input registers to 32-bit insns to be set to 64-bit +values on x86-64, which allows testing various edge cases. + +Signed-off-by: Richard Henderson +Reviewed-by: Philippe Mathieu-Daudé +Message-Id: <20230114230542.3116013-2-richard.henderson@linaro.org> +Signed-off-by: Paolo Bonzini +(cherry picked from commit 5d62d6649cd367b5b4a3676e7514d2f9ca86cb03) +--- + tests/tcg/i386/test-i386-bmi2.c | 182 ++++++++++++++++---------------- + 1 file changed, 93 insertions(+), 89 deletions(-) + +diff --git a/tests/tcg/i386/test-i386-bmi2.c b/tests/tcg/i386/test-i386-bmi2.c +index 5fadf47510..3c3ef85513 100644 +--- a/tests/tcg/i386/test-i386-bmi2.c ++++ b/tests/tcg/i386/test-i386-bmi2.c +@@ -3,34 +3,40 @@ + #include + #include + ++#ifdef __x86_64 ++typedef uint64_t reg_t; ++#else ++typedef uint32_t reg_t; ++#endif ++ + #define insn1q(name, arg0) \ +-static inline uint64_t name##q(uint64_t arg0) \ ++static inline reg_t name##q(reg_t arg0) \ + { \ +- uint64_t result64; \ ++ reg_t result64; \ + asm volatile (#name "q %1, %0" : "=r"(result64) : "rm"(arg0)); \ + return result64; \ + } + + #define insn1l(name, arg0) \ +-static inline uint32_t name##l(uint32_t arg0) \ ++static inline reg_t name##l(reg_t arg0) \ + { \ +- uint32_t result32; \ ++ reg_t result32; \ + asm volatile (#name "l %k1, %k0" : "=r"(result32) : "rm"(arg0)); \ + return result32; \ + } + + #define insn2q(name, arg0, c0, arg1, c1) \ +-static inline uint64_t name##q(uint64_t arg0, uint64_t arg1) \ ++static inline reg_t name##q(reg_t arg0, reg_t arg1) \ + { \ +- uint64_t result64; \ ++ reg_t result64; \ + asm volatile (#name "q %2, %1, %0" : "=r"(result64) : c0(arg0), c1(arg1)); \ + return result64; \ + } + + #define insn2l(name, arg0, c0, arg1, c1) \ +-static inline uint32_t name##l(uint32_t arg0, uint32_t arg1) \ ++static inline reg_t name##l(reg_t arg0, reg_t arg1) \ + { \ +- uint32_t result32; \ ++ reg_t result32; \ + asm volatile (#name "l %k2, %k1, %k0" : "=r"(result32) : c0(arg0), c1(arg1)); \ + return result32; \ + } +@@ -65,130 +71,128 @@ insn1l(blsr, src) + int main(int argc, char *argv[]) { + uint64_t ehlo = 0x202020204f4c4845ull; + uint64_t mask = 0xa080800302020001ull; +- uint32_t result32; ++ reg_t result; + + #ifdef __x86_64 +- uint64_t result64; +- + /* 64 bits */ +- result64 = andnq(mask, ehlo); +- assert(result64 == 0x002020204d4c4844); ++ result = andnq(mask, ehlo); ++ assert(result == 0x002020204d4c4844); + +- result64 = pextq(ehlo, mask); +- assert(result64 == 133); ++ result = pextq(ehlo, mask); ++ assert(result == 133); + +- result64 = pdepq(result64, mask); +- assert(result64 == (ehlo & mask)); ++ result = pdepq(result, mask); ++ assert(result == (ehlo & mask)); + +- result64 = pextq(-1ull, mask); +- assert(result64 == 511); /* mask has 9 bits set */ ++ result = pextq(-1ull, mask); ++ assert(result == 511); /* mask has 9 bits set */ + +- result64 = pdepq(-1ull, mask); +- assert(result64 == mask); ++ result = pdepq(-1ull, mask); ++ assert(result == mask); + +- result64 = bextrq(mask, 0x3f00); +- assert(result64 == (mask & ~INT64_MIN)); ++ result = bextrq(mask, 0x3f00); ++ assert(result == (mask & ~INT64_MIN)); + +- result64 = bextrq(mask, 0x1038); +- assert(result64 == 0xa0); ++ result = bextrq(mask, 0x1038); ++ assert(result == 0xa0); + +- result64 = bextrq(mask, 0x10f8); +- assert(result64 == 0); ++ result = bextrq(mask, 0x10f8); ++ assert(result == 0); + +- result64 = blsiq(0x30); +- assert(result64 == 0x10); ++ result = blsiq(0x30); ++ assert(result == 0x10); + +- result64 = blsiq(0x30ull << 32); +- assert(result64 == 0x10ull << 32); ++ result = blsiq(0x30ull << 32); ++ assert(result == 0x10ull << 32); + +- result64 = blsmskq(0x30); +- assert(result64 == 0x1f); ++ result = blsmskq(0x30); ++ assert(result == 0x1f); + +- result64 = blsrq(0x30); +- assert(result64 == 0x20); ++ result = blsrq(0x30); ++ assert(result == 0x20); + +- result64 = blsrq(0x30ull << 32); +- assert(result64 == 0x20ull << 32); ++ result = blsrq(0x30ull << 32); ++ assert(result == 0x20ull << 32); + +- result64 = bzhiq(mask, 0x3f); +- assert(result64 == (mask & ~INT64_MIN)); ++ result = bzhiq(mask, 0x3f); ++ assert(result == (mask & ~INT64_MIN)); + +- result64 = bzhiq(mask, 0x1f); +- assert(result64 == (mask & ~(-1 << 30))); ++ result = bzhiq(mask, 0x1f); ++ assert(result == (mask & ~(-1 << 30))); + +- result64 = rorxq(0x2132435465768798, 8); +- assert(result64 == 0x9821324354657687); ++ result = rorxq(0x2132435465768798, 8); ++ assert(result == 0x9821324354657687); + +- result64 = sarxq(0xffeeddccbbaa9988, 8); +- assert(result64 == 0xffffeeddccbbaa99); ++ result = sarxq(0xffeeddccbbaa9988, 8); ++ assert(result == 0xffffeeddccbbaa99); + +- result64 = sarxq(0x77eeddccbbaa9988, 8 | 64); +- assert(result64 == 0x0077eeddccbbaa99); ++ result = sarxq(0x77eeddccbbaa9988, 8 | 64); ++ assert(result == 0x0077eeddccbbaa99); + +- result64 = shrxq(0xffeeddccbbaa9988, 8); +- assert(result64 == 0x00ffeeddccbbaa99); ++ result = shrxq(0xffeeddccbbaa9988, 8); ++ assert(result == 0x00ffeeddccbbaa99); + +- result64 = shrxq(0x77eeddccbbaa9988, 8 | 192); +- assert(result64 == 0x0077eeddccbbaa99); ++ result = shrxq(0x77eeddccbbaa9988, 8 | 192); ++ assert(result == 0x0077eeddccbbaa99); + +- result64 = shlxq(0xffeeddccbbaa9988, 8); +- assert(result64 == 0xeeddccbbaa998800); ++ result = shlxq(0xffeeddccbbaa9988, 8); ++ assert(result == 0xeeddccbbaa998800); + #endif + + /* 32 bits */ +- result32 = andnl(mask, ehlo); +- assert(result32 == 0x04d4c4844); ++ result = andnl(mask, ehlo); ++ assert(result == 0x04d4c4844); + +- result32 = pextl((uint32_t) ehlo, mask); +- assert(result32 == 5); ++ result = pextl((uint32_t) ehlo, mask); ++ assert(result == 5); + +- result32 = pdepl(result32, mask); +- assert(result32 == (uint32_t)(ehlo & mask)); ++ result = pdepl(result, mask); ++ assert(result == (uint32_t)(ehlo & mask)); + +- result32 = pextl(-1u, mask); +- assert(result32 == 7); /* mask has 3 bits set */ ++ result = pextl(-1u, mask); ++ assert(result == 7); /* mask has 3 bits set */ + +- result32 = pdepl(-1u, mask); +- assert(result32 == (uint32_t)mask); ++ result = pdepl(-1u, mask); ++ assert(result == (uint32_t)mask); + +- result32 = bextrl(mask, 0x1f00); +- assert(result32 == (mask & ~INT32_MIN)); ++ result = bextrl(mask, 0x1f00); ++ assert(result == (mask & ~INT32_MIN)); + +- result32 = bextrl(ehlo, 0x1018); +- assert(result32 == 0x4f); ++ result = bextrl(ehlo, 0x1018); ++ assert(result == 0x4f); + +- result32 = bextrl(mask, 0x1038); +- assert(result32 == 0); ++ result = bextrl(mask, 0x1038); ++ assert(result == 0); + +- result32 = blsil(0xffff); +- assert(result32 == 1); ++ result = blsil(0xffff); ++ assert(result == 1); + +- result32 = blsmskl(0x300); +- assert(result32 == 0x1ff); ++ result = blsmskl(0x300); ++ assert(result == 0x1ff); + +- result32 = blsrl(0xffc); +- assert(result32 == 0xff8); ++ result = blsrl(0xffc); ++ assert(result == 0xff8); + +- result32 = bzhil(mask, 0xf); +- assert(result32 == 1); ++ result = bzhil(mask, 0xf); ++ assert(result == 1); + +- result32 = rorxl(0x65768798, 8); +- assert(result32 == 0x98657687); ++ result = rorxl(0x65768798, 8); ++ assert(result == 0x98657687); + +- result32 = sarxl(0xffeeddcc, 8); +- assert(result32 == 0xffffeedd); ++ result = sarxl(0xffeeddcc, 8); ++ assert(result == 0xffffeedd); + +- result32 = sarxl(0x77eeddcc, 8 | 32); +- assert(result32 == 0x0077eedd); ++ result = sarxl(0x77eeddcc, 8 | 32); ++ assert(result == 0x0077eedd); + +- result32 = shrxl(0xffeeddcc, 8); +- assert(result32 == 0x00ffeedd); ++ result = shrxl(0xffeeddcc, 8); ++ assert(result == 0x00ffeedd); + +- result32 = shrxl(0x77eeddcc, 8 | 128); +- assert(result32 == 0x0077eedd); ++ result = shrxl(0x77eeddcc, 8 | 128); ++ assert(result == 0x0077eedd); + +- result32 = shlxl(0xffeeddcc, 8); +- assert(result32 == 0xeeddcc00); ++ result = shlxl(0xffeeddcc, 8); ++ assert(result == 0xeeddcc00); + + return 0; + } +-- +2.39.1 + diff --git a/qemu-kvm.spec b/qemu-kvm.spec index 5061083..f230c8c 100644 --- a/qemu-kvm.spec +++ b/qemu-kvm.spec @@ -148,7 +148,7 @@ Obsoletes: %{name}-block-ssh <= %{epoch}:%{version} \ Summary: QEMU is a machine emulator and virtualizer Name: qemu-kvm Version: 7.2.0 -Release: 12%{?rcrel}%{?dist}%{?cc_suffix} +Release: 13%{?rcrel}%{?dist}%{?cc_suffix} # Epoch because we pushed a qemu-1.0 package. AIUI this can't ever be dropped # Epoch 15 used for RHEL 8 # Epoch 17 used for RHEL 9 (due to release versioning offset in RHEL 8.5) @@ -400,6 +400,22 @@ Patch125: kvm-physmem-add-missing-memory-barrier.patch Patch126: kvm-async-update-documentation-of-the-memory-barriers.patch # For bz#2175660 - Guest hangs when starting or rebooting Patch127: kvm-async-clarify-usage-of-barriers-in-the-polling-case.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch128: kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch129: kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch130: kvm-target-i386-Fix-BEXTR-instruction.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch131: kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch132: kvm-target-i386-fix-ADOX-followed-by-ADCX.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch133: kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch +# For bz#2173590 - bugs in emulation of BMI instructions (for libguestfs without KVM) +Patch134: kvm-target-i386-Fix-BZHI-instruction.patch +# For bz#2156876 - [virtual network][rhel7.9_guest] qemu-kvm: vhost vring error in virtqueue 1: Invalid argument (22) +Patch135: kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch %if %{have_clang} BuildRequires: clang @@ -1430,6 +1446,20 @@ useradd -r -u 107 -g qemu -G kvm -d / -s /sbin/nologin \ %endif %changelog +* Mon Mar 20 2023 Miroslav Rezanina - 7.2.0-13 +- kvm-target-i386-fix-operand-size-of-unary-SSE-operations.patch [bz#2173590] +- kvm-tests-tcg-i386-Introduce-and-use-reg_t-consistently.patch [bz#2173590] +- kvm-target-i386-Fix-BEXTR-instruction.patch [bz#2173590] +- kvm-target-i386-Fix-C-flag-for-BLSI-BLSMSK-BLSR.patch [bz#2173590] +- kvm-target-i386-fix-ADOX-followed-by-ADCX.patch [bz#2173590] +- kvm-target-i386-Fix-32-bit-AD-CO-X-insns-in-64-bit-mode.patch [bz#2173590] +- kvm-target-i386-Fix-BZHI-instruction.patch [bz#2173590] +- kvm-intel-iommu-fail-DEVIOTLB_UNMAP-without-dt-mode.patch [bz#2156876] +- Resolves: bz#2173590 + (bugs in emulation of BMI instructions (for libguestfs without KVM)) +- Resolves: bz#2156876 + ([virtual network][rhel7.9_guest] qemu-kvm: vhost vring error in virtqueue 1: Invalid argument (22)) + * Sun Mar 12 2023 Miroslav Rezanina - 7.2.0-12 - kvm-scsi-protect-req-aiocb-with-AioContext-lock.patch [bz#2155748] - kvm-dma-helpers-prevent-dma_blk_cb-vs-dma_aio_cancel-rac.patch [bz#2155748]