2023-06-22 20:10:36 +00:00
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From 716e77e02fe25d40f09b8f2af1ff68238f7d7058 Mon Sep 17 00:00:00 2001
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2023-05-24 18:04:22 +00:00
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From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= <clg@redhat.com>
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Date: Tue, 23 May 2023 12:34:33 +0200
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2023-06-22 20:10:36 +00:00
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Subject: [PATCH 04/22] target/s390x: Fix SRDA CC calculation
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2023-05-24 18:04:22 +00:00
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Cédric Le Goater <clg@redhat.com>
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RH-MergeRequest: 279: Backport latest s390x-related fixes from upstream QEMU for qemu-kvm in RHEL 8.9
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2023-06-22 20:10:36 +00:00
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RH-Bugzilla: 2169308 2209605
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2023-05-24 18:04:22 +00:00
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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2023-06-22 20:10:36 +00:00
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RH-Acked-by: David Hildenbrand <david@redhat.com>
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Commit: [3/21] 95b2ba26003baa51f85f07e8860f875349c72b86
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2023-05-24 18:04:22 +00:00
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Bugzilla: https://bugzilla.redhat.com/2169308
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commit 57556b28afde4b039bb12bfc274bd8df9022d946
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Author: Ilya Leoshkevich <iii@linux.ibm.com>
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Date: Wed Jan 12 17:50:13 2022 +0100
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target/s390x: Fix SRDA CC calculation
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SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
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cout_s64() relies on o->out being the shift result, however,
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wout_r1_D32() clobbers it.
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Fix by using a temporary.
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Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
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Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
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Reviewed-by: David Hildenbrand <david@redhat.com>
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Message-Id: <20220112165016.226996-3-iii@linux.ibm.com>
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Signed-off-by: Thomas Huth <thuth@redhat.com>
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Signed-off-by: Cédric Le Goater <clg@redhat.com>
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---
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target/s390x/tcg/translate.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
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index dcc249a197..c5e59b68af 100644
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--- a/target/s390x/tcg/translate.c
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+++ b/target/s390x/tcg/translate.c
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@@ -5420,9 +5420,11 @@ static void wout_r1_P32(DisasContext *s, DisasOps *o)
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static void wout_r1_D32(DisasContext *s, DisasOps *o)
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{
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int r1 = get_field(s, r1);
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+ TCGv_i64 t = tcg_temp_new_i64();
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store_reg32_i64(r1 + 1, o->out);
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- tcg_gen_shri_i64(o->out, o->out, 32);
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- store_reg32_i64(r1, o->out);
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+ tcg_gen_shri_i64(t, o->out, 32);
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+ store_reg32_i64(r1, t);
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+ tcg_temp_free_i64(t);
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}
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#define SPEC_wout_r1_D32 SPEC_r1_even
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--
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2.37.3
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