60 lines
2.3 KiB
Diff
60 lines
2.3 KiB
Diff
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From 32437dacd0f0d5076af2d549317b92432ee52abd Mon Sep 17 00:00:00 2001
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From: Tao Su <tao1.su@linux.intel.com>
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Date: Thu, 31 Oct 2024 16:52:33 +0800
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Subject: [PATCH 37/38] target/i386: Introduce GraniteRapids-v2 model
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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RH-MergeRequest: 280: Add support for the AVX10.1, SHA512, SM3 and SM4 instruction sets
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RH-Jira: RHEL-30315 RHEL-45110
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RH-Acked-by: Vitaly Kuznetsov <vkuznets@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Commit: [8/9] c53ba67dd616c9f376db0ab4f1478dd50f5dd874 (bonzini/rhel-qemu-kvm)
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Update GraniteRapids CPU model to add AVX10 and the missing features(ss,
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tsc-adjust, cldemote, movdiri, movdir64b).
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Tested-by: Xuelian Guo <xuelian.guo@intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Link: https://lore.kernel.org/r/20241028024512.156724-7-tao1.su@linux.intel.com
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Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Link: https://lore.kernel.org/r/20241031085233.425388-9-tao1.su@linux.intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 1a519388a882fbb352e49cbebb0ed8f62d05842d)
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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---
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target/i386/cpu.c | 17 +++++++++++++++++
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1 file changed, 17 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index ddec461dd4..e7367cfe82 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -4385,6 +4385,23 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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.model_id = "Intel Xeon Processor (GraniteRapids)",
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.versions = (X86CPUVersionDefinition[]) {
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{ .version = 1 },
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+ {
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+ .version = 2,
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+ .props = (PropValue[]) {
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+ { "ss", "on" },
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+ { "tsc-adjust", "on" },
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+ { "cldemote", "on" },
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+ { "movdiri", "on" },
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+ { "movdir64b", "on" },
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+ { "avx10", "on" },
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+ { "avx10-128", "on" },
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+ { "avx10-256", "on" },
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+ { "avx10-512", "on" },
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+ { "avx10-version", "1" },
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+ { "stepping", "1" },
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+ { /* end of list */ }
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+ }
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+ },
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{ /* end of list */ },
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},
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},
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--
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2.39.3
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