1153dbfd9b
Update to qatlib 26.02.0 @ fe4bb4b6 Add patch to force 32 bit MMIO CSR reads for GCC 16.1 Resolves: RHEL-115834 Signed-off-by: Vladislav Dronov <vdronov@redhat.com>
33 lines
1.4 KiB
Diff
33 lines
1.4 KiB
Diff
diff --git a/quickassist/lookaside/access_layer/src/qat_direct/include/adf_platform_common.h b/quickassist/lookaside/access_layer/src/qat_direct/include/adf_platform_common.h
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index 6956a5e02502..449ba2978a93 100644
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--- a/quickassist/lookaside/access_layer/src/qat_direct/include/adf_platform_common.h
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+++ b/quickassist/lookaside/access_layer/src/qat_direct/include/adf_platform_common.h
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@@ -258,8 +258,21 @@ static inline unsigned int modulo(unsigned int data, unsigned int shift)
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#define ICP_ADF_CSR_WR(csrAddr, csrOffset, val) \
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(void)((*((volatile Cpa32U *)(((Cpa8U *)csrAddr) + csrOffset)) = (val)))
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-/* CSR read macro */
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-#define ICP_ADF_CSR_RD(csrAddr, csrOffset) \
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- (*((volatile Cpa32U *)(((Cpa8U *)csrAddr) + csrOffset)))
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+/*
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+ * Force MMIO loads to remain 32-bit wide. GCC 16 may otherwise narrow a
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+ * volatile 32-bit CSR read to a byte access when only one bit is tested,
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+ * which breaks QAT mailbox CSRs that require DWORD transactions.
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+ */
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+static inline unsigned int icp_adf_csr_rd(void *csrAddr, unsigned int csrOffset)
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+{
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+ const volatile void *addr = ((char *)csrAddr) + csrOffset;
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+ unsigned int val;
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+
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+ __asm__ __volatile__("movl (%1), %0" : "=r"(val) : "r"(addr) : "memory");
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+
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+ return val;
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+}
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+
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+#define ICP_ADF_CSR_RD(csrAddr, csrOffset) icp_adf_csr_rd(csrAddr, csrOffset)
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#endif /* ADF_PLATFORM_COMMON_H */
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--
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2.54.0
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