48 lines
1.6 KiB
Diff
48 lines
1.6 KiB
Diff
From 575b84a7bcbd63f54d933804ea5036642b93c0f7 Mon Sep 17 00:00:00 2001
|
|
From: zherczeg <zherczeg@2f5784b3-3f2a-0410-8824-cb99058d5e15>
|
|
Date: Fri, 1 Jul 2016 09:06:38 +0000
|
|
Subject: [PATCH] Fix register overwite in JIT when SSE2 acceleration is
|
|
enabled.
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
git-svn-id: svn://vcs.exim.org/pcre/code/trunk@1660 2f5784b3-3f2a-0410-8824-cb99058d5e15
|
|
|
|
Petr Písař: Ported to 8.39.
|
|
|
|
diff --git a/pcre_jit_compile.c b/pcre_jit_compile.c
|
|
index 4f15a27..46ce6c6 100644
|
|
--- a/pcre_jit_compile.c
|
|
+++ b/pcre_jit_compile.c
|
|
@@ -4004,12 +4004,12 @@ sljit_emit_op_custom(compiler, instruction, 4);
|
|
|
|
if (load_twice)
|
|
{
|
|
- OP1(SLJIT_MOV, TMP3, 0, TMP2, 0);
|
|
+ OP1(SLJIT_MOV, RETURN_ADDR, 0, TMP2, 0);
|
|
instruction[3] = 0xc0 | (tmp2_ind << 3) | 1;
|
|
sljit_emit_op_custom(compiler, instruction, 4);
|
|
|
|
OP2(SLJIT_OR, TMP1, 0, TMP1, 0, TMP2, 0);
|
|
- OP1(SLJIT_MOV, TMP2, 0, TMP3, 0);
|
|
+ OP1(SLJIT_MOV, TMP2, 0, RETURN_ADDR, 0);
|
|
}
|
|
|
|
OP2(SLJIT_ASHR, TMP1, 0, TMP1, 0, TMP2, 0);
|
|
diff --git a/pcre_jit_test.c b/pcre_jit_test.c
|
|
index 9b61ec0..034cb52 100644
|
|
--- a/pcre_jit_test.c
|
|
+++ b/pcre_jit_test.c
|
|
@@ -687,6 +687,7 @@ static struct regression_test_case regression_test_cases[] = {
|
|
{ PCRE_FIRSTLINE | PCRE_NEWLINE_LF | PCRE_DOTALL, 0 | F_NOMATCH, "ab.", "ab" },
|
|
{ MUA | PCRE_FIRSTLINE, 1 | F_NOMATCH, "^[a-d0-9]", "\nxx\nd" },
|
|
{ PCRE_NEWLINE_ANY | PCRE_FIRSTLINE | PCRE_DOTALL, 0, "....a", "012\n0a" },
|
|
+ { MUA | PCRE_FIRSTLINE, 0, "[aC]", "a" },
|
|
|
|
/* Recurse. */
|
|
{ MUA, 0, "(a)(?1)", "aa" },
|
|
--
|
|
2.5.5
|
|
|