From bb401e048b436b9ed5f32f55f4ca5833a73bef00 Mon Sep 17 00:00:00 2001 From: Michal Hlavinka Date: Mon, 1 Jun 2026 17:38:57 +0200 Subject: [PATCH] improvements to PCIe link speed downgrade reporting (RHEL-176385) Resolves: RHEL-176385 --- pciutils-3.7-speed-reporting.patch | 41 ++++++++++++++++++++++++++++++ pciutils-3.7.0-cxllinkstatus.patch | 4 +-- pciutils.spec | 14 +++++++--- 3 files changed, 54 insertions(+), 5 deletions(-) create mode 100644 pciutils-3.7-speed-reporting.patch diff --git a/pciutils-3.7-speed-reporting.patch b/pciutils-3.7-speed-reporting.patch new file mode 100644 index 0000000..3525a94 --- /dev/null +++ b/pciutils-3.7-speed-reporting.patch @@ -0,0 +1,41 @@ +diff --git a/ls-caps.c b/ls-caps.c +index 91acb599..79b61cd8 100644 +--- a/ls-caps.c ++++ b/ls-caps.c +@@ -771,13 +771,16 @@ static char *link_speed(int speed) + } + } + +-static char *link_compare(int sta, int cap) ++static char *link_compare(int type, int sta, int cap) + { +- if (sta < cap) +- return "downgraded"; + if (sta > cap) +- return "strange"; +- return "ok"; ++ return " (overdriven)"; ++ if (sta == cap) ++ return ""; ++ if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_DOWNSTREAM) || ++ (type == PCI_EXP_TYPE_PCIE_BRIDGE)) ++ return ""; ++ return " (downgraded)"; + } + + static char *aspm_support(int code) +@@ -850,11 +853,11 @@ static void cap_express_link(struct device *d, int where, int type) + w = get_conf_word(d, where + PCI_EXP_LNKSTA); + sta_speed = w & PCI_EXP_LNKSTA_SPEED; + sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; +- printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n", ++ printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n", + link_speed(sta_speed), +- link_compare(sta_speed, cap_speed), ++ link_compare(type, sta_speed, cap_speed), + sta_width, +- link_compare(sta_width, cap_width)); ++ link_compare(type, sta_width, cap_width)); + printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", + FLAG(w, PCI_EXP_LNKSTA_TR_ERR), + FLAG(w, PCI_EXP_LNKSTA_TRAIN), diff --git a/pciutils-3.7.0-cxllinkstatus.patch b/pciutils-3.7.0-cxllinkstatus.patch index 7a84fb9..1806135 100644 --- a/pciutils-3.7.0-cxllinkstatus.patch +++ b/pciutils-3.7.0-cxllinkstatus.patch @@ -104,9 +104,9 @@ diff -up pciutils-3.7.0/ls-caps.c.cxxsup pciutils-3.7.0/ls-caps.c + sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4; + printf("\t\tLnkSta:\tSpeed %s%s, Width x%d%s\n", + link_speed(sta_speed), -+ link_compare(sta_speed, cap_speed), ++ link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_speed, cap_speed), + sta_width, -+ link_compare(sta_width, cap_width)); ++ link_compare(PCI_EXP_TYPE_ROOT_INT_EP, sta_width, cap_width)); + printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n", + FLAG(w, PCI_EXP_LNKSTA_TR_ERR), + FLAG(w, PCI_EXP_LNKSTA_TRAIN), diff --git a/pciutils.spec b/pciutils.spec index 27690b9..3c13452 100644 --- a/pciutils.spec +++ b/pciutils.spec @@ -1,6 +1,6 @@ Name: pciutils Version: 3.7.0 -Release: 7%{?dist} +Release: 8%{?dist} Summary: PCI bus related utilities License: GPLv2+ URL: https://mj.ucw.cz/sw/pciutils/ @@ -21,8 +21,12 @@ Patch3: pciutils-3.7.0-decodercec.patch Patch4: pciutils-3.7.0-pcie6datarate1of2.patch Patch5: pciutils-3.7.0-pcie6datarate2of2.patch +# for < 3.8.0, RHEL-176385 +# https://github.com/pciutils/pciutils/commit/9f7681202fcfaefd02e202eb64c01eb9e962729d +Patch6: pciutils-3.7-speed-reporting.patch + #cxl1.1 device link status, from upstream, for < 3.13, #RHEL-29162 -Patch6: pciutils-3.7.0-cxllinkstatus.patch +Patch7: pciutils-3.7.0-cxllinkstatus.patch Requires: hwdata Requires: %{name}-libs = %{version}-%{release} @@ -63,7 +67,8 @@ devices connected to the PCI bus. %patch -P 3 -p 1 %patch -P 4 -p 1 %patch -P 5 -p 1 -%patch -P 6 -p 1 -b .cxxsup +%patch -P 6 -p 1 -b .speed-reporting +%patch -P 7 -p 1 -b .cxxsup %build %make_build SHARED="no" ZLIB="no" LIBKMOD=yes STRIP="" OPT="$RPM_OPT_FLAGS" LDFLAGS="$RPM_LD_FLAGS" PREFIX="/usr" LIBDIR="%{_libdir}" IDSDIR="/usr/share/hwdata" PCI_IDS="pci.ids" @@ -115,6 +120,9 @@ install -p -m 644 lib/libpci.pc $RPM_BUILD_ROOT%{_libdir}/pkgconfig %{_mandir}/man7/* %changelog +* Mon Jun 01 2026 Michal Hlavinka - 3.7.0-8 +- improvements to PCIe link speed downgrade reporting (RHEL-176385) + * Sat Nov 02 2024 Michal Hlavinka - 3.7.0-7 - add support for cxl1.1 device link status information (#RHEL-29162)