206 lines
8.8 KiB
Diff
206 lines
8.8 KiB
Diff
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commit 61616f7ddaaef1b79df85f0a3e969c886604de6c
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Author: Heike Jagode <jagode@icl.utk.edu>
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Date: Mon Apr 2 17:47:31 2018 -0400
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PAPI preset event support for Intel Knights Mill.
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index faa4ae2f5..bb11f61d3 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -851,8 +851,10 @@ PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD
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#
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#
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# Intel MIC / Xeon-Phi / Knights Landing
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+# Intel Knights Mill
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#
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CPU,knl
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+CPU,knm
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PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
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PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
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PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
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@@ -885,6 +887,7 @@ PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED:JCC,BR_INST_RETIRED:TAKEN_JCC
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PRESET,PAPI_RES_STL,NOT_DERIVED,RS_FULL_STALL:ANY
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PRESET,PAPI_STL_ICY,NOT_DERIVED,NO_ALLOC_CYCLES:ANY
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#
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+# End of knl,knm list
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CPU,Intel Core2
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CPU,Intel Core
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commit 85003c716d76eff47607fa0967537c6cf63d8348
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Author: Steve Walk <swalk.cavium@gmail.com>
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Date: Fri Jun 8 15:50:50 2018 -0400
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enable Cavium ThunderX2 support
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index bb11f61d3..46827f180 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1841,6 +1841,31 @@ PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS
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PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
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PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
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PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL
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+
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+#####################
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+# ARM ThunderX2 #
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+#####################
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+CPU,arm_thunderx2
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+#
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+PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
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+PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
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+PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
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+PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC
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+PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
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+PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED
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+PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED
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+PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE_RD,L1D_CACHE_WR
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+PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
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+PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
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+PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
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+PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
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+PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
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+PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE
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+PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
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+PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
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+PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
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+PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
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+
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#
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CPU,mips_74k
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#
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commit 111d01df256f691c2a2d2e14028fa4ebc9e63bed
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Author: Vince Weaver <vincent.weaver@maine.edu>
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Date: Tue Jan 22 17:09:29 2019 -0500
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papi_events: add cascade lake X support
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index f5bcf1a46..009074449 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -724,9 +724,11 @@ CPU,hsw_ep
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CPU,bdw
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CPU,bdw_ep
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CPU,skl
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-CPU,skx
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# Note, libpfm4 treats Kaby Lake as just a form of skylake
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CPU,kbl
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+CPU,skx
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+# Note, libpfm4 treats Cascade Lake-X as just a form of skylake-X
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+CPU,clx
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PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:THREAD_P
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PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P
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PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
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commit d5a1a9ae2e4102e03063e76e242d4a3547cd5df3
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Author: Vince Weaver <vincent.weaver@maine.edu>
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Date: Wed Jan 23 16:58:10 2019 -0500
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papi_events: the skylake events are actually split in two, make sure cascadelake gets both cases too
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 009074449..361813847 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -832,6 +832,7 @@ PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH
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CPU,skl
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CPU,skx
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+CPU,clx
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# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE
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PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
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# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE
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@@ -849,7 +850,7 @@ PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ_UOPS_NOT_DELIVERED:CYCLES_0_UOPS_DELIV_CORE
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PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD
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-# End of hsw,bdw,skl list
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+# End of hsw,bdw,skl,clx list
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#
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#
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# Intel MIC / Xeon-Phi / Knights Landing
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commit c9d0702caf582179cf89f28d987a68e48b9af0e9
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Author: Daniel Barry <dbarry@vols.utk.edu>
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Date: Mon May 20 16:31:45 2019 -0400
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I have added PAPI POWER9 event definitions for PAPI_L2_DCR, PAPI_L2_DCW, PAPI_BR_CN, PAPI_BR_NTK, PAPI_BR_UCN, and PAPI_BR_TKN.
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These events have been tested. Their patterns of behavior were measured during the execution of performance benchmarks on Summit's POWER9 processors.
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The patterns of behavior for the corresponding events on Intel Haswell processors were measured during the execution of the same performance benchmarks.
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The respective events from each architecture behave similarly.
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 361813847..f658931ed 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1588,6 +1588,8 @@ PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_CMPL
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PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
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PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS
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PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS
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+PRESET,PAPI_L2_DCR,NOT_DERIVED,PM_DATA_FROM_L2
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+PRESET,PAPI_L2_DCW,NOT_DERIVED,PM_L2_ST_HIT
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PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
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PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
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PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
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@@ -1617,6 +1619,10 @@ PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN
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PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN
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PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL
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PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED
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+PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND
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+PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PM_BR_CMPL,PM_BR_UNCOND,PM_BR_TAKEN_CMPL
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+PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND
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+PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL
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PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
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#
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CPU,ultra12
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commit 6440c5995a10db05959325b1192368734bfa7e5b
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Author: Carl Love <cel@us.ibm.com>
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Date: Wed Aug 14 07:52:50 2019 -0400
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Per Carl Love, "The POWER9 event PM_BR_TAKEN_CMPL includes conditional and unconditional branches. The equation for event PAPI_BR_NTK should not include the event PM_BR_UNCOND as PM_BR_TAKEN_CMPL already counts unconditional branches. The POWER9 event PM_LD_REF_L1 includes hits and misses to the L1. Thus we should not be adding PM_LS_MISS_L1_ALT when calculating PAPI_LD_INS on POWER9."
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The definitions for these preset events were changed accordingly, and their patterns of behavior were measured during the execution of performance benchmarks on the IBM POWER9 processors on Summit. The patterns of behavior for the corresponding events on the Intel Skylake and Broadwell processors were measured during the execution of the same performance benchmarks. The respective events from each architecture behave similarly. In addition, the new definitions pass the PAPI validation tests.
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Signed-off-by: Daniel Barry <dbarry@vols.utk.edu>
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index f658931ed..8df74866e 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -1613,14 +1613,14 @@ PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
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PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
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PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP
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PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN
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-PRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1_ALT
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+PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
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PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN
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PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN
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PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN
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PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL
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PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED
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PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND
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-PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PM_BR_CMPL,PM_BR_UNCOND,PM_BR_TAKEN_CMPL
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+PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|,PM_BR_CMPL,PM_BR_TAKEN_CMPL
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PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND
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PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL
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PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
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commit 20890adcb59a1c1648cb70be65332c03a3781e1a
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Author: Anthony Castaldo <TonyCastaldo@icl.utk.edu>
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Date: Thu Jan 16 16:43:51 2020 -0500
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Added two machine types to papi_events.csv to be in line with
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libpfm4 update to support amd64_fam17h_zen1 and zen2.
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diff --git a/src/papi_events.csv b/src/papi_events.csv
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index 97446ad2c..8e96adfbd 100644
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--- a/src/papi_events.csv
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+++ b/src/papi_events.csv
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@@ -396,6 +396,8 @@ PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE
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#
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#
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CPU,amd64_fam17h
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+CPU,amd64_fam17h_zen1
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+CPU,amd64_fam17h_zen2
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#
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PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
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PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
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