riscv: Further fixes for https://github.com/nojb/riscv-ocaml/issues/2

0001-Don-t-add-rpaths-to-libraries.patch

@@ -1,7 +1,7 @@
 From fc5ac0d955afce294fe58a20cab8e9dda572de78 Mon Sep 17 00:00:00 2001
 From: "Richard W.M. Jones" <rjones@redhat.com>
 Date: Tue, 24 Jun 2014 10:00:15 +0100
-Subject: [PATCH 1/9] Don't add rpaths to libraries.
+Subject: [PATCH 01/10] Don't add rpaths to libraries.
 
 ---
  tools/Makefile.shared | 6 +++---

0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch

@@ -1,7 +1,7 @@
 From 61bdb02cedd1be6ecdc37bc4a80ffe3f19aa5521 Mon Sep 17 00:00:00 2001
 From: "Richard W.M. Jones" <rjones@redhat.com>
 Date: Tue, 29 May 2012 20:40:36 +0100
-Subject: [PATCH 2/9] ocamlbyteinfo, ocamlplugininfo: Useful utilities from
+Subject: [PATCH 02/10] ocamlbyteinfo, ocamlplugininfo: Useful utilities from
  Debian, sent upstream.
 
 See:

0003-configure-Allow-user-defined-C-compiler-flags.patch

@@ -1,7 +1,7 @@
 From 2f93494aea56c9216bb561800a6861b653f409ce Mon Sep 17 00:00:00 2001
 From: "Richard W.M. Jones" <rjones@redhat.com>
 Date: Tue, 29 May 2012 20:44:18 +0100
-Subject: [PATCH 3/9] configure: Allow user defined C compiler flags.
+Subject: [PATCH 03/10] configure: Allow user defined C compiler flags.
 
 ---
  configure | 4 ++++

0004-Don-t-rewrite-Werror.patch

@@ -1,7 +1,7 @@
 From cdd42ba82210bfaa97cfa010eaac3d805b80cb49 Mon Sep 17 00:00:00 2001
 From: "Richard W.M. Jones" <rjones@redhat.com>
 Date: Thu, 3 Nov 2016 19:50:20 +0000
-Subject: [PATCH 4/9] Don't rewrite -Werror.
+Subject: [PATCH 04/10] Don't rewrite -Werror.
 
 In Fedora our CFLAGS contains -Wall -Werror=format-security.
 

0005-PR-7405-s390x-Fix-address-of-caml_raise_exn-in-nativ.patch

@@ -1,7 +1,7 @@
 From d4a20446fc8d00223b0c23726618407e451472e8 Mon Sep 17 00:00:00 2001
 From: "Richard W.M. Jones" <rjones@redhat.com>
 Date: Wed, 9 Nov 2016 11:01:15 -0500
-Subject: [PATCH 5/9] PR#7405: s390x: Fix address of caml_raise_exn in native
+Subject: [PATCH 05/10] PR#7405: s390x: Fix address of caml_raise_exn in native
  dynlink modules.
 
 This commit started as Fedora patch e732c39340e86939530a087744caa8d8f1247878.

0006-Adapt-config.guess-for-RISC-V.patch

@@ -1,7 +1,7 @@
 From 427232f0f36bfcaafcb1ec2f8da3d1daad0b1121 Mon Sep 17 00:00:00 2001
 From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
 Date: Tue, 8 Nov 2016 23:56:50 +0100
-Subject: [PATCH 6/9] Adapt config.guess for RISC-V
+Subject: [PATCH 06/10] Adapt config.guess for RISC-V
 
 ---
  config/gnu/config.guess | 5 ++++-

0007-Add-RISC-V-backend-runtime.patch

@@ -1,7 +1,7 @@
 From cc3aa63c6892479851786af89b956004491dc84c Mon Sep 17 00:00:00 2001
 From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
 Date: Fri, 4 Nov 2016 20:39:09 +0100
-Subject: [PATCH 7/9] Add RISC-V backend & runtime
+Subject: [PATCH 07/10] Add RISC-V backend & runtime
 
 ---
  README.adoc                 |   1 +

0008-Try-fix-for-andi-ori-xori-immediates-1.patch

@@ -1,7 +1,7 @@
 From f1be77d69e28ad3bd128c6c757d966e90bbf73d3 Mon Sep 17 00:00:00 2001
 From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
 Date: Thu, 10 Nov 2016 14:12:53 +0100
-Subject: [PATCH 8/9] Try fix for andi/ori/xori immediates (#1)
+Subject: [PATCH 08/10] Try fix for andi/ori/xori immediates (#1)
 
 ---
  asmcomp/riscv/selection.ml | 13 -------------

0009-Fix-immediates-range-when-adjusting-indexing-sp.patch

@@ -1,7 +1,7 @@
 From b81417ea168c3cf9454eeb41f1f723b66b3210aa Mon Sep 17 00:00:00 2001
 From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
 Date: Tue, 22 Nov 2016 22:30:35 +0100
-Subject: [PATCH 9/9] Fix immediates' range when adjusting/indexing sp
+Subject: [PATCH 09/10] Fix immediates' range when adjusting/indexing sp
 
 ---
  asmcomp/riscv/arch.ml      |  3 +++

0010-Another-immediate-range-fix.patch

@@ -0,0 +1,131 @@
+From ab30529b723d451fd0ea8ac64d24fc417af55541 Mon Sep 17 00:00:00 2001
+From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
+Date: Wed, 23 Nov 2016 12:38:28 +0100
+Subject: [PATCH 10/10] Another immediate range fix
+
+---
+ asmcomp/riscv/emit.mlp | 57 ++++++++++++++++++++++++++++++--------------------
+ 1 file changed, 34 insertions(+), 23 deletions(-)
+
+diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
+index 97c49ce..6cc1908 100644
+--- a/asmcomp/riscv/emit.mlp
++++ b/asmcomp/riscv/emit.mlp
+@@ -85,14 +85,6 @@ let emit_reg = function
+   | {loc = Reg r} -> emit_string (register_name r)
+   | _ -> fatal_error "Emit.emit_reg"
+ 
+-(* Output a stack reference *)
+-
+-let emit_stack r =
+-  match r.loc with
+-    Stack s ->
+-      let ofs = slot_offset s (register_class r) in `{emit_int ofs}(sp)`
+-  | _ -> fatal_error "Emit.emit_stack"
+-
+ (* Adjust sp by the given byte amount *)
+ 
+ let emit_stack_adjustment = function
+@@ -103,7 +95,27 @@ let emit_stack_adjustment = function
+       `	li	{emit_reg reg_tmp1}, {emit_int n}\n`;
+       `	add	sp, sp, {emit_reg reg_tmp1}\n`
+ 
+-let emit_store src ofs =
++let reload_ra n =
++  let ofs = n - size_addr in
++  if is_immediate ofs then
++    `	{emit_string lg}	ra, {emit_int ofs}(sp)\n`
++  else begin
++    `	li	{emit_reg reg_tmp1}, {emit_int ofs}\n`;
++    `	add	{emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
++    `	{emit_string lg}	ra, 0({emit_reg reg_tmp1})\n`
++  end
++
++let store_ra n =
++  let ofs = n - size_addr in
++  if is_immediate ofs then
++    `	{emit_string stg}	ra, {emit_int(n - size_addr)}(sp)\n`
++  else begin
++    `	li	{emit_reg reg_tmp1}, {emit_int ofs}\n`;
++    `	add	{emit_reg reg_tmp1}, sp, {emit_reg reg_tmp1}\n`;
++    `	{emit_string stg}	ra, 0({emit_reg reg_tmp1})\n`
++  end
++
++let emit_store stg src ofs =
+   if is_immediate ofs then
+     `	{emit_string stg}	{emit_reg src}, {emit_int ofs}(sp)\n`
+   else begin
+@@ -112,7 +124,7 @@ let emit_store src ofs =
+     `	{emit_string stg}	{emit_reg src}, 0({emit_reg reg_tmp1})\n`
+   end
+ 
+-let emit_load dst ofs =
++let emit_load lg dst ofs =
+   if is_immediate ofs then
+     `	{emit_string lg}	{emit_reg dst}, {emit_int ofs}(sp)\n`
+   else begin
+@@ -265,14 +277,16 @@ let emit_instr i =
+             `	fmv.d   {emit_reg dst}, {emit_reg src}\n`
+         | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack s} ->
+             let ofs = slot_offset s (register_class dst) in
+-            emit_store src ofs
+-        | {loc = Reg _; typ = Float}, {loc = Stack _} ->
+-            `	fsd	{emit_reg src}, {emit_stack dst}\n`
++            emit_store stg src ofs
++        | {loc = Reg _; typ = Float}, {loc = Stack s} ->
++            let ofs = slot_offset s (register_class dst) in
++            emit_store "fsd" src ofs
+         | {loc = Stack s; typ = (Val | Int | Addr)}, {loc = Reg _} ->
+             let ofs = slot_offset s (register_class src) in
+-            emit_load dst ofs
+-        | {loc = Stack _; typ = Float}, {loc = Reg _} ->
+-            `	fld	{emit_reg dst}, {emit_stack src}\n`
++            emit_load lg dst ofs
++        | {loc = Stack s; typ = Float}, {loc = Reg _} ->
++            let ofs = slot_offset s (register_class src) in
++            emit_load "fld" dst ofs
+         | _ ->
+             fatal_error "Emit: Imove"
+       end
+@@ -292,8 +306,7 @@ let emit_instr i =
+       record_frame ~label i.live false i.dbg
+   | Lop(Itailcall_ind {label_after = _}) ->
+       let n = frame_size() in
+-      if !contains_calls then
+-        `	{emit_string lg}	ra, {emit_int(n - size_addr)}(sp)\n`;
++      if !contains_calls then reload_ra n;
+       emit_stack_adjustment n;
+       `	jr	{emit_reg i.arg.(0)}\n`
+   | Lop(Itailcall_imm {func; label_after = _}) ->
+@@ -301,8 +314,7 @@ let emit_instr i =
+         `	j	{emit_label !tailrec_entry_point}\n`
+       end else begin
+         let n = frame_size() in
+-        if !contains_calls then
+-          `	{emit_string lg}	ra, {emit_int(n - size_addr)}(sp)\n`;
++        if !contains_calls then reload_ra n;
+         emit_stack_adjustment n;
+         `	tail	{emit_symbol func}\n`
+       end
+@@ -424,7 +436,7 @@ let emit_instr i =
+       `	{emit_string instr}	{emit_reg i.res.(0)}, {emit_reg i.arg.(0)}, {emit_reg i.arg.(1)}, {emit_reg i.arg.(2)}\n`
+   | Lreloadretaddr ->
+       let n = frame_size () in
+-      `	{emit_string lg}	ra, {emit_int(n - size_addr)}(sp)\n`
++      reload_ra n
+   | Lreturn ->
+       let n = frame_size() in
+       emit_stack_adjustment n;
+@@ -542,8 +554,7 @@ let fundecl fundecl =
+   `{emit_symbol fundecl.fun_name}:\n`;
+   let n = frame_size() in
+   emit_stack_adjustment (-n);
+-  if !contains_calls then
+-    `	{emit_string stg}	ra, {emit_int(n - size_addr)}(sp)\n`;
++  if !contains_calls then store_ra n;
+   `{emit_label !tailrec_entry_point}:\n`;
+   emit_all fundecl.fun_body;
+   List.iter emit_call_gc !call_gc_sites;
+-- 
+2.9.3
+

ocaml.spec

@@ -27,7 +27,7 @@
 
 Name:           ocaml
 Version:        4.04.0
-Release:        6%{?dist}
+Release:        7%{?dist}
 
 Summary:        OCaml compiler and programming environment
 
@@ -67,6 +67,7 @@ Patch0006:      0006-Adapt-config.guess-for-RISC-V.patch
 Patch0007:      0007-Add-RISC-V-backend-runtime.patch
 Patch0008:      0008-Try-fix-for-andi-ori-xori-immediates-1.patch
 Patch0009:      0009-Fix-immediates-range-when-adjusting-indexing-sp.patch
+Patch0010:      0010-Another-immediate-range-fix.patch
 
 BuildRequires:  binutils-devel
 BuildRequires:  ncurses-devel
@@ -453,8 +454,8 @@ fi
 
 
 %changelog
-* Wed Nov 23 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-6
+* Wed Nov 23 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-7
-- riscv: Further fix for https://github.com/nojb/riscv-ocaml/issues/2
+- riscv: Further fixes for https://github.com/nojb/riscv-ocaml/issues/2
 
 * Tue Nov 22 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-5
 - Update RISC-V support to fix