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Update RISC-V support to fix

Browse Source 
https://github.com/nojb/riscv-ocaml/issues/2
This commit is contained in:
Richard W.M. Jones 2016-11-22 22:21:33 +00:00
parent a48061fc04
commit 1b4063eb57
10 changed files with 226 additions and 72 deletions
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2
0001-Don-t-add-rpaths-to-libraries.patch
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@ -1,7 +1,7 @@
From fc5ac0d955afce294fe58a20cab8e9dda572de78 Mon Sep 17 00:00:00 2001 From fc5ac0d955afce294fe58a20cab8e9dda572de78 Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com> From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 24 Jun 2014 10:00:15 +0100 Date: Tue, 24 Jun 2014 10:00:15 +0100
Subject: [PATCH 1/7] Don't add rpaths to libraries. Subject: [PATCH 1/9] Don't add rpaths to libraries.
--- ---
tools/Makefile.shared | 6 +++--- tools/Makefile.shared | 6 +++---

2
0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch
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@ -1,7 +1,7 @@
From 61bdb02cedd1be6ecdc37bc4a80ffe3f19aa5521 Mon Sep 17 00:00:00 2001 From 61bdb02cedd1be6ecdc37bc4a80ffe3f19aa5521 Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com> From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 29 May 2012 20:40:36 +0100 Date: Tue, 29 May 2012 20:40:36 +0100
Subject: [PATCH 2/7] ocamlbyteinfo, ocamlplugininfo: Useful utilities from Subject: [PATCH 2/9] ocamlbyteinfo, ocamlplugininfo: Useful utilities from
Debian, sent upstream. Debian, sent upstream.
See: See:

2
0003-configure-Allow-user-defined-C-compiler-flags.patch
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@ -1,7 +1,7 @@
From 2f93494aea56c9216bb561800a6861b653f409ce Mon Sep 17 00:00:00 2001 From 2f93494aea56c9216bb561800a6861b653f409ce Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com> From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Tue, 29 May 2012 20:44:18 +0100 Date: Tue, 29 May 2012 20:44:18 +0100
Subject: [PATCH 3/7] configure: Allow user defined C compiler flags. Subject: [PATCH 3/9] configure: Allow user defined C compiler flags.
--- ---
configure | 4 ++++ configure | 4 ++++

2
0004-Don-t-rewrite-Werror.patch
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@ -1,7 +1,7 @@
From cdd42ba82210bfaa97cfa010eaac3d805b80cb49 Mon Sep 17 00:00:00 2001 From cdd42ba82210bfaa97cfa010eaac3d805b80cb49 Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com> From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Thu, 3 Nov 2016 19:50:20 +0000 Date: Thu, 3 Nov 2016 19:50:20 +0000
Subject: [PATCH 4/7] Don't rewrite -Werror. Subject: [PATCH 4/9] Don't rewrite -Werror.
In Fedora our CFLAGS contains -Wall -Werror=format-security. In Fedora our CFLAGS contains -Wall -Werror=format-security.

4
0006-PR-7405-s390x-Fix-address-of-caml_raise_exn-in-nativ.patch → 0005-PR-7405-s390x-Fix-address-of-caml_raise_exn-in-nativ.patch
View File

@ -1,7 +1,7 @@
From d82ea2b77261e030be5a75d0277ce5b62b52b751 Mon Sep 17 00:00:00 2001 From d4a20446fc8d00223b0c23726618407e451472e8 Mon Sep 17 00:00:00 2001
From: "Richard W.M. Jones" <rjones@redhat.com> From: "Richard W.M. Jones" <rjones@redhat.com>
Date: Wed, 9 Nov 2016 11:01:15 -0500 Date: Wed, 9 Nov 2016 11:01:15 -0500
Subject: [PATCH 6/7] PR#7405: s390x: Fix address of caml_raise_exn in native Subject: [PATCH 5/9] PR#7405: s390x: Fix address of caml_raise_exn in native
dynlink modules. dynlink modules.
This commit started as Fedora patch e732c39340e86939530a087744caa8d8f1247878. This commit started as Fedora patch e732c39340e86939530a087744caa8d8f1247878.

35
0006-Adapt-config.guess-for-RISC-V.patch Normal file
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@ -0,0 +1,35 @@
From 427232f0f36bfcaafcb1ec2f8da3d1daad0b1121 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Tue, 8 Nov 2016 23:56:50 +0100
Subject: [PATCH 6/9] Adapt config.guess for RISC-V
---
config/gnu/config.guess | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/config/gnu/config.guess b/config/gnu/config.guess
index b79252d..8335398 100755
--- a/config/gnu/config.guess
+++ b/config/gnu/config.guess
@@ -2,7 +2,7 @@
# Attempt to guess a canonical system name.
# Copyright 1992-2013 Free Software Foundation, Inc.
-timestamp='2013-06-10'
+timestamp='2016-10-23'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1001,6 +1001,9 @@ EOF
ppcle:Linux:*:*)
echo powerpcle-unknown-linux-${LIBC}
exit ;;
+ riscv*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux
+ exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
exit ;;
--
2.9.3

73
0005-RISC-V-support-2016-11-08.patch → 0007-Add-RISC-V-backend-runtime.patch
View File

@ -1,14 +1,8 @@
From 4d586c823b021c3091aab7bb3f88f1678c194558 Mon Sep 17 00:00:00 2001 From cc3aa63c6892479851786af89b956004491dc84c Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com> From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Fri, 4 Nov 2016 20:39:09 +0100 Date: Fri, 4 Nov 2016 20:39:09 +0100
Subject: [PATCH 5/7] RISC-V support 2016-11-08 Subject: [PATCH 7/9] Add RISC-V backend & runtime
This commit contains the squashed commits from:
https://github.com/nojb/riscv-ocaml/commits/trunk
since tag 4.04.0 (OCaml 4.04.0), as at the date given in the subject
line.
--- ---
README.adoc | 1 + README.adoc | 1 +
asmcomp/riscv/CSE.ml | 36 +++ asmcomp/riscv/CSE.ml | 36 +++
@ -20,9 +14,8 @@ line.
asmcomp/riscv/selection.ml | 85 ++++++ asmcomp/riscv/selection.ml | 85 ++++++
asmrun/riscv.S | 424 ++++++++++++++++++++++++++++++ asmrun/riscv.S | 424 ++++++++++++++++++++++++++++++
byterun/caml/stack.h | 5 + byterun/caml/stack.h | 5 +
config/gnu/config.guess | 7 +-
configure | 5 +- configure | 5 +-
12 files changed, 1596 insertions(+), 3 deletions(-) 11 files changed, 1591 insertions(+), 1 deletion(-)
create mode 100644 asmcomp/riscv/CSE.ml create mode 100644 asmcomp/riscv/CSE.ml
create mode 100644 asmcomp/riscv/arch.ml create mode 100644 asmcomp/riscv/arch.ml
create mode 100644 asmcomp/riscv/emit.mlp create mode 100644 asmcomp/riscv/emit.mlp
@ -46,7 +39,7 @@ index 480b025..cb6eebf 100644
the compiler may work under other operating systems with little work. the compiler may work under other operating systems with little work.
diff --git a/asmcomp/riscv/CSE.ml b/asmcomp/riscv/CSE.ml diff --git a/asmcomp/riscv/CSE.ml b/asmcomp/riscv/CSE.ml
new file mode 100644 new file mode 100644
index 0000000..b0b51a6 index 0000000..302811a
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/CSE.ml +++ b/asmcomp/riscv/CSE.ml
@@ -0,0 +1,36 @@ @@ -0,0 +1,36 @@
@ -56,7 +49,7 @@ index 0000000..b0b51a6
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 2014 Institut National de Recherche en Informatique et *) +(* Copyright 2106 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -88,7 +81,7 @@ index 0000000..b0b51a6
+ (new cse)#fundecl f + (new cse)#fundecl f
diff --git a/asmcomp/riscv/arch.ml b/asmcomp/riscv/arch.ml diff --git a/asmcomp/riscv/arch.ml b/asmcomp/riscv/arch.ml
new file mode 100644 new file mode 100644
index 0000000..e2a4f38 index 0000000..61a38b1
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/arch.ml +++ b/asmcomp/riscv/arch.ml
@@ -0,0 +1,84 @@ @@ -0,0 +1,84 @@
@ -98,7 +91,7 @@ index 0000000..e2a4f38
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1996 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -178,7 +171,7 @@ index 0000000..e2a4f38
+ printreg arg.(0) printreg arg.(1) printreg arg.(2) + printreg arg.(0) printreg arg.(1) printreg arg.(2)
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
new file mode 100644 new file mode 100644
index 0000000..f03c09c index 0000000..6d0e3ae
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/emit.mlp +++ b/asmcomp/riscv/emit.mlp
@@ -0,0 +1,616 @@ @@ -0,0 +1,616 @@
@ -188,7 +181,7 @@ index 0000000..f03c09c
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1996 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -800,7 +793,7 @@ index 0000000..f03c09c
+ } + }
diff --git a/asmcomp/riscv/proc.ml b/asmcomp/riscv/proc.ml diff --git a/asmcomp/riscv/proc.ml b/asmcomp/riscv/proc.ml
new file mode 100644 new file mode 100644
index 0000000..840d240 index 0000000..c0b0dcd
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/proc.ml +++ b/asmcomp/riscv/proc.ml
@@ -0,0 +1,301 @@ @@ -0,0 +1,301 @@
@ -810,7 +803,7 @@ index 0000000..840d240
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1996 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -1107,7 +1100,7 @@ index 0000000..840d240
+let init () = () +let init () = ()
diff --git a/asmcomp/riscv/reload.ml b/asmcomp/riscv/reload.ml diff --git a/asmcomp/riscv/reload.ml b/asmcomp/riscv/reload.ml
new file mode 100644 new file mode 100644
index 0000000..8042d20 index 0000000..85b9703
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/reload.ml +++ b/asmcomp/riscv/reload.ml
@@ -0,0 +1,16 @@ @@ -0,0 +1,16 @@
@ -1117,7 +1110,7 @@ index 0000000..8042d20
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1996 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -1129,7 +1122,7 @@ index 0000000..8042d20
+ (new Reloadgen.reload_generic)#fundecl f + (new Reloadgen.reload_generic)#fundecl f
diff --git a/asmcomp/riscv/scheduling.ml b/asmcomp/riscv/scheduling.ml diff --git a/asmcomp/riscv/scheduling.ml b/asmcomp/riscv/scheduling.ml
new file mode 100644 new file mode 100644
index 0000000..41c6b26 index 0000000..e436be1
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/scheduling.ml +++ b/asmcomp/riscv/scheduling.ml
@@ -0,0 +1,19 @@ @@ -0,0 +1,19 @@
@ -1139,7 +1132,7 @@ index 0000000..41c6b26
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1996 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -1154,7 +1147,7 @@ index 0000000..41c6b26
+let fundecl f = f +let fundecl f = f
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
new file mode 100644 new file mode 100644
index 0000000..da69f09 index 0000000..60ec5cb
--- /dev/null --- /dev/null
+++ b/asmcomp/riscv/selection.ml +++ b/asmcomp/riscv/selection.ml
@@ -0,0 +1,85 @@ @@ -0,0 +1,85 @@
@ -1164,7 +1157,7 @@ index 0000000..da69f09
+(* *) +(* *)
+(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *) +(* Nicolas Ojeda Bar <n.oje.bar@gmail.com> *)
+(* *) +(* *)
+(* Copyright 1997 Institut National de Recherche en Informatique et *) +(* Copyright 2016 Institut National de Recherche en Informatique et *)
+(* en Automatique. All rights reserved. This file is distributed *) +(* en Automatique. All rights reserved. This file is distributed *)
+(* under the terms of the Q Public License version 1.0. *) +(* under the terms of the Q Public License version 1.0. *)
+(* *) +(* *)
@ -1689,38 +1682,6 @@ index fd9d528..781c251 100644
/* Structure of OCaml callback contexts */ /* Structure of OCaml callback contexts */
struct caml_context { struct caml_context {
diff --git a/config/gnu/config.guess b/config/gnu/config.guess
index b79252d..4d1d4e8 100755
--- a/config/gnu/config.guess
+++ b/config/gnu/config.guess
@@ -2,7 +2,7 @@
# Attempt to guess a canonical system name.
# Copyright 1992-2013 Free Software Foundation, Inc.
-timestamp='2013-06-10'
+timestamp='2016-10-23'
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
@@ -1001,6 +1001,9 @@ EOF
ppcle:Linux:*:*)
echo powerpcle-unknown-linux-${LIBC}
exit ;;
+ riscv*:Linux:*:*)
+ echo ${UNAME_MACHINE}-unknown-linux
+ exit ;;
s390:Linux:*:* | s390x:Linux:*:*)
echo ${UNAME_MACHINE}-ibm-linux-${LIBC}
exit ;;
@@ -1011,7 +1014,7 @@ EOF
echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
sparc:Linux:*:* | sparc64:Linux:*:*)
- echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
+v echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
exit ;;
tile*:Linux:*:*)
echo ${UNAME_MACHINE}-unknown-linux-${LIBC}
diff --git a/configure b/configure diff --git a/configure b/configure
index 41c9315..eb3e1f3 100755 index 41c9315..eb3e1f3 100755
--- a/configure --- a/configure

7
0007-Try-fix-for-andi-ori-xori-immediates-1.patch → 0008-Try-fix-for-andi-ori-xori-immediates-1.patch
View File

@ -1,15 +1,14 @@
From fcb3b532e59bef94af09047b0199a1c32caeaa27 Mon Sep 17 00:00:00 2001 From f1be77d69e28ad3bd128c6c757d966e90bbf73d3 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com> From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Thu, 10 Nov 2016 14:12:53 +0100 Date: Thu, 10 Nov 2016 14:12:53 +0100
Subject: [PATCH 7/7] Try fix for andi/ori/xori immediates (#1) Subject: [PATCH 8/9] Try fix for andi/ori/xori immediates (#1)
(cherry picked from commit 4e01c71358c8f7571914c09369a402e6e290f6c9)
--- ---
asmcomp/riscv/selection.ml | 13 ------------- asmcomp/riscv/selection.ml | 13 -------------
1 file changed, 13 deletions(-) 1 file changed, 13 deletions(-)
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
index da69f09..a1cbb82 100644 index 60ec5cb..ad2b26e 100644
--- a/asmcomp/riscv/selection.ml --- a/asmcomp/riscv/selection.ml
+++ b/asmcomp/riscv/selection.ml +++ b/asmcomp/riscv/selection.ml
@@ -36,11 +36,6 @@ method! select_operation op args = @@ -36,11 +36,6 @@ method! select_operation op args =

154
0009-Fix-immediates-range-when-adjusting-indexing-sp.patch Normal file
View File

@ -0,0 +1,154 @@
From a045766e1fc85d3f0c378415c58577d5156e10f4 Mon Sep 17 00:00:00 2001
From: Nicolas Ojeda Bar <n.oje.bar@gmail.com>
Date: Tue, 22 Nov 2016 22:30:35 +0100
Subject: [PATCH 9/9] Fix immediates' range when adjusting/indexing sp
---
asmcomp/riscv/arch.ml | 3 +++
asmcomp/riscv/emit.mlp | 51 ++++++++++++++++++++++++++++++++++------------
asmcomp/riscv/selection.ml | 2 +-
3 files changed, 42 insertions(+), 14 deletions(-)
diff --git a/asmcomp/riscv/arch.ml b/asmcomp/riscv/arch.ml
index 61a38b1..22c807c 100644
--- a/asmcomp/riscv/arch.ml
+++ b/asmcomp/riscv/arch.ml
@@ -32,6 +32,9 @@ let spacetime_node_hole_pointer_is_live_before = function
type addressing_mode =
| Iindexed of int (* reg + displ *)
+let is_immediate n =
+ (n <= 2047) && (n >= -2048)
+
(* Sizes, endianness *)
let big_endian = false
diff --git a/asmcomp/riscv/emit.mlp b/asmcomp/riscv/emit.mlp
index 6d0e3ae..932a28c 100644
--- a/asmcomp/riscv/emit.mlp
+++ b/asmcomp/riscv/emit.mlp
@@ -93,6 +93,32 @@ let emit_stack r =
let ofs = slot_offset s (register_class r) in `{emit_int ofs}(sp)`
| _ -> fatal_error "Emit.emit_stack"
+(* Adjust sp by the given byte amount *)
+
+let emit_stack_adjustment = function
+ | 0 -> ()
+ | n when is_immediate n ->
+ ` addi sp, sp, {emit_int n}\n`
+ | n ->
+ ` li {emit_reg reg_tmp1}, {emit_int n}\n`;
+ ` add sp, sp, {emit_reg reg_tmp1}\n`
+
+let emit_store src ofs =
+ if is_immediate ofs then
+ ` {emit_string stg} {emit_reg src}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` {emit_string stg} {emit_reg src}, 0({emit_reg reg_tmp1})\n`
+ end
+
+let emit_load dst ofs =
+ if is_immediate ofs then
+ ` {emit_string lg} {emit_reg dst}, {emit_int ofs}(sp)\n`
+ else begin
+ ` li {emit_reg reg_tmp1}, {emit_int ofs}\n`;
+ ` {emit_string lg} {emit_reg dst}, 0({emit_reg reg_tmp1})\n`
+ end
+
(* Record live pointers at call points *)
let record_frame_label ?label live raise_ dbg =
@@ -218,6 +244,7 @@ let name_for_specific = function
(* Name of current function *)
let function_name = ref ""
+
(* Entry point for tail recursive calls *)
let tailrec_entry_point = ref 0
@@ -234,12 +261,14 @@ let emit_instr i =
` mv {emit_reg dst}, {emit_reg src}\n`
| {loc = Reg _; typ = Float}, {loc = Reg _; typ = Float} ->
` fmv.d {emit_reg dst}, {emit_reg src}\n`
- | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack _} ->
- ` {emit_string stg} {emit_reg src}, {emit_stack dst}\n`
+ | {loc = Reg _; typ = (Val | Int | Addr)}, {loc = Stack s} ->
+ let ofs = slot_offset s (register_class dst) in
+ emit_store src ofs
| {loc = Reg _; typ = Float}, {loc = Stack _} ->
` fsd {emit_reg src}, {emit_stack dst}\n`
- | {loc = Stack _; typ = (Val | Int | Addr)}, {loc = Reg _ } ->
- ` {emit_string lg} {emit_reg dst}, {emit_stack src}\n`
+ | {loc = Stack s; typ = (Val | Int | Addr)}, {loc = Reg _} ->
+ let ofs = slot_offset s (register_class src) in
+ emit_load dst ofs
| {loc = Stack _; typ = Float}, {loc = Reg _} ->
` fld {emit_reg dst}, {emit_stack src}\n`
| _ ->
@@ -263,8 +292,7 @@ let emit_instr i =
let n = frame_size() in
if !contains_calls then
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` jr {emit_reg i.arg.(0)}\n`
| Lop(Itailcall_imm {func; label_after = _}) ->
if func = !function_name then begin
@@ -273,8 +301,7 @@ let emit_instr i =
let n = frame_size() in
if !contains_calls then
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`;
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` tail {emit_symbol func}\n`
end
| Lop(Iextcall{func; alloc = true; label_after = label}) ->
@@ -285,7 +312,7 @@ let emit_instr i =
` call {emit_symbol func}\n`
| Lop(Istackoffset n) ->
assert (n mod 16 = 0);
- ` addi sp, sp, {emit_int (-n)}\n`;
+ emit_stack_adjustment (-n);
stack_offset := !stack_offset + n
| Lop(Iload(Single, Iindexed ofs)) ->
` flw {emit_reg i.res.(0)}, {emit_int ofs}({emit_reg i.arg.(0)})\n`;
@@ -398,8 +425,7 @@ let emit_instr i =
` {emit_string lg} ra, {emit_int(n - size_addr)}(sp)\n`
| Lreturn ->
let n = frame_size() in
- if n > 0 then
- ` addi sp, sp, {emit_int n}\n`;
+ emit_stack_adjustment n;
` ret\n`
| Llabel lbl ->
`{emit_label lbl}:\n`
@@ -513,8 +539,7 @@ let fundecl fundecl =
` .align 2\n`;
`{emit_symbol fundecl.fun_name}:\n`;
let n = frame_size() in
- if n > 0 then
- ` addi sp, sp, {emit_int(-n)}\n`;
+ emit_stack_adjustment (-n);
if !contains_calls then
` {emit_string stg} ra, {emit_int(n - size_addr)}(sp)\n`;
`{emit_label !tailrec_entry_point}:\n`;
diff --git a/asmcomp/riscv/selection.ml b/asmcomp/riscv/selection.ml
index ad2b26e..2832336 100644
--- a/asmcomp/riscv/selection.ml
+++ b/asmcomp/riscv/selection.ml
@@ -22,7 +22,7 @@ class selector = object (self)
inherit Selectgen.selector_generic as super
-method is_immediate n = (n <= 0x7FF) && (n >= -0x800)
+method is_immediate n = is_immediate n
method select_addressing _ = function
| Cop(Cadda, [arg; Cconst_int n]) when self#is_immediate n ->
--
2.9.3

17
ocaml.spec
View File

@ -27,7 +27,7 @@
Name: ocaml Name: ocaml
Version: 4.04.0 Version: 4.04.0
Release: 4%{?dist} Release: 5%{?dist}
Summary: OCaml compiler and programming environment Summary: OCaml compiler and programming environment
@ -60,12 +60,13 @@ Patch0001: 0001-Don-t-add-rpaths-to-libraries.patch
Patch0002: 0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch Patch0002: 0002-ocamlbyteinfo-ocamlplugininfo-Useful-utilities-from-.patch
Patch0003: 0003-configure-Allow-user-defined-C-compiler-flags.patch Patch0003: 0003-configure-Allow-user-defined-C-compiler-flags.patch
Patch0004: 0004-Don-t-rewrite-Werror.patch Patch0004: 0004-Don-t-rewrite-Werror.patch
# Out of tree patch from Patch0005: 0005-PR-7405-s390x-Fix-address-of-caml_raise_exn-in-nativ.patch
# Out of tree patches from
# https://github.com/nojb/riscv-ocaml # https://github.com/nojb/riscv-ocaml
Patch0005: 0005-RISC-V-support-2016-11-08.patch Patch0006: 0006-Adapt-config.guess-for-RISC-V.patch
Patch0006: 0006-PR-7405-s390x-Fix-address-of-caml_raise_exn-in-nativ.patch Patch0007: 0007-Add-RISC-V-backend-runtime.patch
# https://github.com/nojb/riscv-ocaml/issues/1 Patch0008: 0008-Try-fix-for-andi-ori-xori-immediates-1.patch
Patch0007: 0007-Try-fix-for-andi-ori-xori-immediates-1.patch Patch0009: 0009-Fix-immediates-range-when-adjusting-indexing-sp.patch
BuildRequires: binutils-devel BuildRequires: binutils-devel
BuildRequires: ncurses-devel BuildRequires: ncurses-devel
@ -452,6 +453,10 @@ fi
%changelog %changelog
* Tue Nov 22 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-5
- Update RISC-V support to fix
https://github.com/nojb/riscv-ocaml/issues/2
* Fri Nov 11 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-4 * Fri Nov 11 2016 Richard W.M. Jones <rjones@redhat.com> - 4.04.0-4
- riscv64: Fix intermediate operands. - riscv64: Fix intermediate operands.
(https://github.com/nojb/riscv-ocaml/issues/1) (https://github.com/nojb/riscv-ocaml/issues/1)