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6a533d52ba
numatop/0006-common-Add-sample-period-to-platform-event-config.patch
Pingfan Liu 6a533d52ba add x86 zen support 
Resolves: bz2088798
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2088798

Signed-off-by: Pingfan Liu <piliu@redhat.com>
2023-09-25 21:02:31 -04:00

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From 4a8b8d47f4a240a95830dc05abd3c19e10b6d821 Mon Sep 17 00:00:00 2001
From: Sandipan Das <sandipan.das@amd.com>
Date: Fri, 11 Nov 2022 13:56:09 +0530
Subject: [PATCH 06/15] common: Add sample period to platform event config
Precise PMU events are currently used for capturing memory
access statistics. The sample period used for such events is
currently hard-coded (LL_THRESH) and an universal value may
not work well on all platforms due to microarchitectural
differences in the design of the precise PMU.
E.g. precise events are programmed through Instruction Based
Sampling (IBS) on AMD processors but that PMU does not have
the ability to tag only load-store operations. This leads to
the capture of many samples that are not relevant for the
current use-case. To get an appropriate amount of relevant
data, more samples need to be captured and then filtered.
This is achieved by increasing the sampling frequency.
Add sample period as an additional attribute to the platform
event config structure so that a customized sample period
that works well on a specific platform can be passed during
event programming. If not set, a default value is chosen.
Signed-off-by: Sandipan Das <sandipan.das@amd.com>
---
common/include/os/plat.h | 1 +
common/os/os_perf.c | 6 +++++-
powerpc/power8.c | 14 +++++++-------
powerpc/power9.c | 14 +++++++-------
x86/bdw.c | 12 ++++++------
x86/nhm.c | 12 ++++++------
x86/skl.c | 32 ++++++++++++++++----------------
x86/snb.c | 12 ++++++------
x86/wsm.c | 22 +++++++++++-----------
x86/zen.c | 2 +-
10 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/common/include/os/plat.h b/common/include/os/plat.h
index e35093d..34535cd 100644
--- a/common/include/os/plat.h
+++ b/common/include/os/plat.h
@@ -53,6 +53,7 @@ typedef struct _plat_event_config {
uint64_t config;
uint64_t other_attr;
uint64_t extra_value;
+ uint64_t sample_period;
char desc[PLAT_EVENT_DESC_SIZE];
} plat_event_config_t;
diff --git a/common/os/os_perf.c b/common/os/os_perf.c
index f2f1104..f1036a9 100644
--- a/common/os/os_perf.c
+++ b/common/os/os_perf.c
@@ -839,7 +839,11 @@ ll_init(pf_conf_t *conf)
conf->type = cfg.type;
conf->config = (cfg.config) | (cfg.other_attr << 16);
conf->config1 = cfg.extra_value;
- conf->sample_period = LL_PERIOD;
+ conf->sample_period = cfg.sample_period;
+
+ /* If sample period is not set, choose a default value */
+ if (!cfg.sample_period)
+ conf->sample_period = LL_PERIOD;
}
int
diff --git a/powerpc/power8.c b/powerpc/power8.c
index b3cab75..a76851d 100644
--- a/powerpc/power8.c
+++ b/powerpc/power8.c
@@ -38,16 +38,16 @@
#include "include/power8.h"
static plat_event_config_t s_power8_profiling[PERF_COUNT_NUM] = {
- { PERF_TYPE_RAW, 0x600f4, 0, 0, "PM_RUN_CYC" },
- { PERF_TYPE_RAW, 0x4c04c, 0, 0, "PM_DATA_FROM_DMEM" },
- { PERF_TYPE_RAW, 0x1001e, 0, 0, "PM_CYC" },
- { PERF_TYPE_RAW, 0x500fa, 0, 0, "PM_RUN_INST_CMPL" },
- { PERF_TYPE_RAW, 0x2c048, 0, 0, "PM_DATA_FROM_LMEM" },
- { PERF_TYPE_RAW, 0x3c04a, 0, 0, "PM_DATA_FROM_RMEM" },
+ { PERF_TYPE_RAW, 0x600f4, 0, 0, 0, "PM_RUN_CYC" },
+ { PERF_TYPE_RAW, 0x4c04c, 0, 0, 0, "PM_DATA_FROM_DMEM" },
+ { PERF_TYPE_RAW, 0x1001e, 0, 0, 0, "PM_CYC" },
+ { PERF_TYPE_RAW, 0x500fa, 0, 0, 0, "PM_RUN_INST_CMPL" },
+ { PERF_TYPE_RAW, 0x2c048, 0, 0, 0, "PM_DATA_FROM_LMEM" },
+ { PERF_TYPE_RAW, 0x3c04a, 0, 0, 0, "PM_DATA_FROM_RMEM" },
};
static plat_event_config_t s_power8_ll = {
- PERF_TYPE_RAW, 0x0000, 0, 0, "PM_SUSPENDED"
+ PERF_TYPE_RAW, 0x0000, 0, 0, 0, "PM_SUSPENDED"
};
void
diff --git a/powerpc/power9.c b/powerpc/power9.c
index c6f1cec..4b0bcfc 100644
--- a/powerpc/power9.c
+++ b/powerpc/power9.c
@@ -38,16 +38,16 @@
#include "include/power9.h"
static plat_event_config_t s_power9_profiling[PERF_COUNT_NUM] = {
- { PERF_TYPE_RAW, 0x600f4, 0, 0, "PM_RUN_CYC" },
- { PERF_TYPE_RAW, 0x4c04c, 0, 0, "PM_DATA_FROM_DMEM" },
- { PERF_TYPE_RAW, 0x1001e, 0, 0, "PM_CYC" },
- { PERF_TYPE_RAW, 0x500fa, 0, 0, "PM_RUN_INST_CMPL" },
- { PERF_TYPE_RAW, 0x2c048, 0, 0, "PM_DATA_FROM_LMEM" },
- { PERF_TYPE_RAW, 0x3c04a, 0, 0, "PM_DATA_FROM_RMEM" },
+ { PERF_TYPE_RAW, 0x600f4, 0, 0, 0, "PM_RUN_CYC" },
+ { PERF_TYPE_RAW, 0x4c04c, 0, 0, 0, "PM_DATA_FROM_DMEM" },
+ { PERF_TYPE_RAW, 0x1001e, 0, 0, 0, "PM_CYC" },
+ { PERF_TYPE_RAW, 0x500fa, 0, 0, 0, "PM_RUN_INST_CMPL" },
+ { PERF_TYPE_RAW, 0x2c048, 0, 0, 0, "PM_DATA_FROM_LMEM" },
+ { PERF_TYPE_RAW, 0x3c04a, 0, 0, 0, "PM_DATA_FROM_RMEM" },
};
static plat_event_config_t s_power9_ll = {
- PERF_TYPE_RAW, 0x0000, 0, 0, "PM_SUSPENDED"
+ PERF_TYPE_RAW, 0x0000, 0, 0, 0, "PM_SUSPENDED"
};
void
diff --git a/x86/bdw.c b/x86/bdw.c
index 97e33ea..5640f7b 100644
--- a/x86/bdw.c
+++ b/x86/bdw.c
@@ -40,15 +40,15 @@
#include "include/bdw.h"
static plat_event_config_t s_bdw_config[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x638000001, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x604000001, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x638000001, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x604000001, 0, "off_core_response_1" }
};
static plat_event_config_t s_bdw_ll = {
- PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, "mem_trans_retired.latency_above_threshold"
+ PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, 0, "mem_trans_retired.latency_above_threshold"
};
void
diff --git a/x86/nhm.c b/x86/nhm.c
index bf8c14f..d29d396 100644
--- a/x86/nhm.c
+++ b/x86/nhm.c
@@ -41,15 +41,15 @@
#include "include/nhm.h"
static plat_event_config_t s_nhm_profiling[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, INVALID_CODE_UMASK, 0, 0, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, INVALID_CODE_UMASK, 0, 0, 0, "off_core_response_1" }
};
static plat_event_config_t s_nhm_ll = {
- PERF_TYPE_RAW, 0x100B, 0x53, LL_THRESH, "mem_inst_retired.latency_above_threshold"
+ PERF_TYPE_RAW, 0x100B, 0x53, LL_THRESH, 0, "mem_inst_retired.latency_above_threshold"
};
static void
diff --git a/x86/skl.c b/x86/skl.c
index ace0833..6f81298 100644
--- a/x86/skl.c
+++ b/x86/skl.c
@@ -40,31 +40,31 @@
#include "include/skl.h"
static plat_event_config_t s_skl_config[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x638000001, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x1f84000001, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x638000001, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x1f84000001, 0, "off_core_response_1" }
};
static plat_event_config_t s_icx_config[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x730000001, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x104000001, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x730000001, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x104000001, 0, "off_core_response_1" }
};
static plat_event_config_t s_spr_config[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x012A, 0x53, 0x730000001, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x012A, 0x53, 0x730000001, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, 0, "off_core_response_1" }
};
static plat_event_config_t s_skl_ll = {
- PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, "mem_trans_retired.latency_above_threshold"
+ PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, 0, "mem_trans_retired.latency_above_threshold"
};
void
diff --git a/x86/snb.c b/x86/snb.c
index eb89859..3d3185b 100644
--- a/x86/snb.c
+++ b/x86/snb.c
@@ -40,15 +40,15 @@
#include "include/snb.h"
static plat_event_config_t s_snb_ep_config[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x67f800001, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x600400001, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x67f800001, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x600400001, 0, "off_core_response_1" }
};
static plat_event_config_t s_snb_ll = {
- PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, "mem_trans_retired.latency_above_threshold"
+ PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, 0, "mem_trans_retired.latency_above_threshold"
};
void
diff --git a/x86/wsm.c b/x86/wsm.c
index f4285c2..16f68e4 100644
--- a/x86/wsm.c
+++ b/x86/wsm.c
@@ -40,23 +40,23 @@
#include "include/wsm.h"
static plat_event_config_t s_wsmex_profiling[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x5011, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x5011, 0, "off_core_response_1" }
};
static plat_event_config_t s_wsmep_profiling[PERF_COUNT_NUM] = {
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.core" },
- { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, "off_core_response_0" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, "cpu_clk_unhalted.ref" },
- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, "instr_retired.any" },
- { PERF_TYPE_RAW, 0x01BB, 0x53, 0x5011, "off_core_response_1" }
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.core" },
+ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x2011, 0, "off_core_response_0" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, "cpu_clk_unhalted.ref" },
+ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, "instr_retired.any" },
+ { PERF_TYPE_RAW, 0x01BB, 0x53, 0x5011, 0, "off_core_response_1" }
};
static plat_event_config_t s_wsm_ll = {
- PERF_TYPE_RAW, 0x100B, 0x53, LL_THRESH, "mem_inst_retired.latency_above_threshold"
+ PERF_TYPE_RAW, 0x100B, 0x53, LL_THRESH, 0, "mem_inst_retired.latency_above_threshold"
};
void
diff --git a/x86/zen.c b/x86/zen.c
index abf603a..c153a1a 100644
--- a/x86/zen.c
+++ b/x86/zen.c
@@ -48,7 +48,7 @@ static plat_event_config_t s_zen_config[PERF_COUNT_NUM] = {
};
static plat_event_config_t s_zen_ll = {
- PERF_TYPE_RAW, 0, 0, 0, "Unsupported"
+ PERF_TYPE_RAW, 0, 0, 0, 0, "Unsupported"
};
void
--
2.31.1
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