From 84a1c3721f2ed38a63e3e1e45a3e97d227cd5cc6 Mon Sep 17 00:00:00 2001 From: Pingfan Liu Date: Thu, 2 Jan 2025 09:10:30 +0800 Subject: [PATCH] Release 2.4-6 Resolves: https://issues.redhat.com/browse/RHEL-20036 Resolves: https://issues.redhat.com/browse/RHEL-20028 Support intel Sierra and Granite Signed-off-by: Pingfan Liu --- ...ve-EMR-specific-events-configuration.patch | 126 +++++++++ ...upport-Intel-Granite-Rapids-platform.patch | 83 ++++++ ...Support-Intel-Sierra-Forest-platform.patch | 251 ++++++++++++++++++ numatop.spec | 9 +- 4 files changed, 468 insertions(+), 1 deletion(-) create mode 100644 0035-Remove-EMR-specific-events-configuration.patch create mode 100644 0036-Support-Intel-Granite-Rapids-platform.patch create mode 100644 0037-Support-Intel-Sierra-Forest-platform.patch diff --git a/0035-Remove-EMR-specific-events-configuration.patch b/0035-Remove-EMR-specific-events-configuration.patch new file mode 100644 index 0000000..7783d2f --- /dev/null +++ b/0035-Remove-EMR-specific-events-configuration.patch @@ -0,0 +1,126 @@ +From 4d9a0e4cd945c58163c0655904f46f932338c9b9 Mon Sep 17 00:00:00 2001 +From: Dapeng Mi +Date: Tue, 15 Oct 2024 12:29:57 +0000 +Subject: [PATCH 1/3] Remove EMR specific events configuration + +Emerald Rapids shares same perf events configuration with +Sapphire rapids, it's unnecessary to define duplicated events +configuration and helper for EMR. It's fine to directly use SPR's +configuration. + +Thus delete these duplicated EMR code. + +Signed-off-by: Dapeng Mi +--- + x86/include/skl.h | 4 ---- + x86/plat.c | 6 +++--- + x86/skl.c | 28 +--------------------------- + 3 files changed, 4 insertions(+), 34 deletions(-) + +diff --git a/x86/include/skl.h b/x86/include/skl.h +index ab19f58..7a8b8f2 100644 +--- a/x86/include/skl.h ++++ b/x86/include/skl.h +@@ -51,10 +51,6 @@ extern void spr_profiling_config(perf_count_id_t, struct _plat_event_config *); + extern void spr_ll_config(struct _plat_event_config *); + extern int spr_offcore_num(void); + +-extern void emr_profiling_config(perf_count_id_t, struct _plat_event_config *); +-extern void emr_ll_config(struct _plat_event_config *); +-extern int emr_offcore_num(void); +- + #ifdef __cplusplus + } + #endif +diff --git a/x86/plat.c b/x86/plat.c +index d0c7cba..d69544e 100644 +--- a/x86/plat.c ++++ b/x86/plat.c +@@ -52,7 +52,7 @@ s_plat_profiling_config[CPU_TYPE_NUM] = { + skl_profiling_config, + icx_profiling_config, + spr_profiling_config, +- emr_profiling_config, ++ spr_profiling_config, /* EMR */ + zen_profiling_config, + zen3_profiling_config, + zen4_profiling_config +@@ -72,7 +72,7 @@ s_plat_ll_config[CPU_TYPE_NUM] = { + skl_ll_config, + icx_ll_config, + spr_ll_config, +- emr_ll_config, ++ spr_ll_config, /* EMR */ + zen_ll_config, + zen_ll_config, + zen_ll_config +@@ -92,7 +92,7 @@ s_plat_offcore_num[CPU_TYPE_NUM] = { + skl_offcore_num, + icx_offcore_num, + spr_offcore_num, +- emr_offcore_num, ++ spr_offcore_num, /* EMR */ + zen_offcore_num, + zen_offcore_num, + zen_offcore_num +diff --git a/x86/skl.c b/x86/skl.c +index a80a868..9be1bf0 100644 +--- a/x86/skl.c ++++ b/x86/skl.c +@@ -63,14 +63,6 @@ static plat_event_config_t s_spr_config[PERF_COUNT_NUM] = { + { PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, 0, 0, "off_core_response_1" } + }; + +-static plat_event_config_t s_emr_config[PERF_COUNT_NUM] = { +- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, 0, "cpu_clk_unhalted.core" }, +- { PERF_TYPE_RAW, 0x012A, 0x53, 0x730000001, 0, 0, "off_core_response_0" }, +- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, 0, "cpu_clk_unhalted.ref" }, +- { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, 0, "instr_retired.any" }, +- { PERF_TYPE_RAW, 0x012B, 0x53, 0x104000001, 0, 0, "off_core_response_1" } +-}; +- + static plat_event_config_t s_skl_ll = { + PERF_TYPE_RAW, 0x01CD, 0x53, LL_THRESH, 0, 1, "mem_trans_retired.latency_above_threshold" + }; +@@ -93,12 +85,6 @@ spr_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg) + plat_config_get(perf_count_id, cfg, s_spr_config); + } + +-void +-emr_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg) +-{ +- plat_config_get(perf_count_id, cfg, s_emr_config); +-} +- + void + skl_ll_config(plat_event_config_t *cfg) + { +@@ -117,12 +103,6 @@ spr_ll_config(plat_event_config_t *cfg) + skl_ll_config(cfg); + } + +-void +-emr_ll_config(plat_event_config_t *cfg) +-{ +- skl_ll_config(cfg); +-} +- + int + skl_offcore_num(void) + { +@@ -139,10 +119,4 @@ int + spr_offcore_num(void) + { + return skl_offcore_num(); +-} +- +-int +-emr_offcore_num(void) +-{ +- return skl_offcore_num(); +-} ++} +\ No newline at end of file +-- +2.41.0 + diff --git a/0036-Support-Intel-Granite-Rapids-platform.patch b/0036-Support-Intel-Granite-Rapids-platform.patch new file mode 100644 index 0000000..7f3e51a --- /dev/null +++ b/0036-Support-Intel-Granite-Rapids-platform.patch @@ -0,0 +1,83 @@ +From f1dadf9fbd33457b660884c6ce526315b1647e72 Mon Sep 17 00:00:00 2001 +From: Dapeng Mi +Date: Tue, 15 Oct 2024 12:41:10 +0000 +Subject: [PATCH 2/3] Support Intel Granite Rapids platform + +Granite Rapids shares same perf events configuration with +Sapphire rapids, directly reuse SPR's configuration to enable GNR's +support. + +Signed-off-by: Dapeng Mi +--- + x86/include/types.h | 3 ++- + x86/plat.c | 7 +++++++ + 2 files changed, 9 insertions(+), 1 deletion(-) + +diff --git a/x86/include/types.h b/x86/include/types.h +index 1a0199a..814ef1c 100644 +--- a/x86/include/types.h ++++ b/x86/include/types.h +@@ -48,12 +48,13 @@ typedef enum { + CPU_ICX, + CPU_SPR, + CPU_EMR, ++ CPU_GNR, + CPU_ZEN, + CPU_ZEN3, + CPU_ZEN4 + } cpu_type_t; + +-#define CPU_TYPE_NUM 16 ++#define CPU_TYPE_NUM 17 + + typedef enum { + PERF_COUNT_INVALID = -1, +diff --git a/x86/plat.c b/x86/plat.c +index d69544e..0eea408 100644 +--- a/x86/plat.c ++++ b/x86/plat.c +@@ -53,6 +53,7 @@ s_plat_profiling_config[CPU_TYPE_NUM] = { + icx_profiling_config, + spr_profiling_config, + spr_profiling_config, /* EMR */ ++ spr_profiling_config, /* GNR */ + zen_profiling_config, + zen3_profiling_config, + zen4_profiling_config +@@ -73,6 +74,7 @@ s_plat_ll_config[CPU_TYPE_NUM] = { + icx_ll_config, + spr_ll_config, + spr_ll_config, /* EMR */ ++ spr_ll_config, /* GNR */ + zen_ll_config, + zen_ll_config, + zen_ll_config +@@ -93,6 +95,7 @@ s_plat_offcore_num[CPU_TYPE_NUM] = { + icx_offcore_num, + spr_offcore_num, + spr_offcore_num, /* EMR */ ++ spr_offcore_num, /* GNR */ + zen_offcore_num, + zen_offcore_num, + zen_offcore_num +@@ -199,6 +202,9 @@ cpu_type_get(void) + case 207: + type = CPU_EMR; + break; ++ case 173: ++ type = CPU_GNR; ++ break; + } + } else if (family == 23) { /* Family 17h */ + type = CPU_ZEN; +@@ -252,6 +258,7 @@ plat_detect(void) + case CPU_ICX: + case CPU_SPR: + case CPU_EMR: ++ case CPU_GNR: + case CPU_ZEN: + case CPU_ZEN3: + case CPU_ZEN4: +-- +2.41.0 + diff --git a/0037-Support-Intel-Sierra-Forest-platform.patch b/0037-Support-Intel-Sierra-Forest-platform.patch new file mode 100644 index 0000000..b402134 --- /dev/null +++ b/0037-Support-Intel-Sierra-Forest-platform.patch @@ -0,0 +1,251 @@ +From 38fafde94d30242b6725f7f50ef92bc85a39f6f5 Mon Sep 17 00:00:00 2001 +From: Dapeng Mi +Date: Tue, 15 Oct 2024 12:56:10 +0000 +Subject: [PATCH 3/3] Support Intel Sierra Forest platform + +Add support for Intel Sierra Forest platform. SRF is the 1st generation +XEON server with pure E-cores. Since E-core's events are different with +P-cores, so create separate srf.h/c files to implement these E-core +specific data structures and helpers. + +Signed-off-by: Dapeng Mi +--- + Makefile.am | 2 ++ + x86/include/srf.h | 50 ++++++++++++++++++++++++++++++++ + x86/include/types.h | 3 +- + x86/plat.c | 8 ++++++ + x86/srf.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 132 insertions(+), 1 deletion(-) + create mode 100644 x86/include/srf.h + create mode 100644 x86/srf.c + +diff --git a/Makefile.am b/Makefile.am +index f23e1a6..a6ef1de 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -64,6 +64,7 @@ libnumatop_la_SOURCES += \ + x86/include/nhm.h \ + x86/include/skl.h \ + x86/include/snb.h \ ++ x86/include/srf.h \ + x86/include/types.h \ + x86/include/util.h \ + x86/include/wsm.h \ +@@ -73,6 +74,7 @@ libnumatop_la_SOURCES += \ + x86/plat.c \ + x86/skl.c \ + x86/snb.c \ ++ x86/srf.c \ + x86/ui_perf_map.c \ + x86/util.c \ + x86/wsm.c \ +diff --git a/x86/include/srf.h b/x86/include/srf.h +new file mode 100644 +index 0000000..8bb0f44 +--- /dev/null ++++ b/x86/include/srf.h +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2024, Intel Corporation ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Intel Corporation nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _NUMATOP_INTEL_SRF_H ++#define _NUMATOP_INTEL_SRF_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include ++#include ++#include "../../common/include/types.h" ++ ++struct _plat_event_config; ++ ++extern void srf_profiling_config(perf_count_id_t, struct _plat_event_config *); ++extern void srf_ll_config(struct _plat_event_config *); ++extern int srf_offcore_num(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _NUMATOP_INTEL_SRF_H */ +\ No newline at end of file +diff --git a/x86/include/types.h b/x86/include/types.h +index 814ef1c..4e3bea1 100644 +--- a/x86/include/types.h ++++ b/x86/include/types.h +@@ -49,12 +49,13 @@ typedef enum { + CPU_SPR, + CPU_EMR, + CPU_GNR, ++ CPU_SRF, + CPU_ZEN, + CPU_ZEN3, + CPU_ZEN4 + } cpu_type_t; + +-#define CPU_TYPE_NUM 17 ++#define CPU_TYPE_NUM 18 + + typedef enum { + PERF_COUNT_INVALID = -1, +diff --git a/x86/plat.c b/x86/plat.c +index 0eea408..557a8c9 100644 +--- a/x86/plat.c ++++ b/x86/plat.c +@@ -36,6 +36,7 @@ + #include "include/snb.h" + #include "include/bdw.h" + #include "include/skl.h" ++#include "include/srf.h" + #include "include/zen.h" + + pfn_plat_profiling_config_t +@@ -54,6 +55,7 @@ s_plat_profiling_config[CPU_TYPE_NUM] = { + spr_profiling_config, + spr_profiling_config, /* EMR */ + spr_profiling_config, /* GNR */ ++ srf_profiling_config, + zen_profiling_config, + zen3_profiling_config, + zen4_profiling_config +@@ -75,6 +77,7 @@ s_plat_ll_config[CPU_TYPE_NUM] = { + spr_ll_config, + spr_ll_config, /* EMR */ + spr_ll_config, /* GNR */ ++ srf_ll_config, + zen_ll_config, + zen_ll_config, + zen_ll_config +@@ -96,6 +99,7 @@ s_plat_offcore_num[CPU_TYPE_NUM] = { + spr_offcore_num, + spr_offcore_num, /* EMR */ + spr_offcore_num, /* GNR */ ++ srf_offcore_num, + zen_offcore_num, + zen_offcore_num, + zen_offcore_num +@@ -205,6 +209,9 @@ cpu_type_get(void) + case 173: + type = CPU_GNR; + break; ++ case 175: ++ type = CPU_SRF; ++ break; + } + } else if (family == 23) { /* Family 17h */ + type = CPU_ZEN; +@@ -259,6 +266,7 @@ plat_detect(void) + case CPU_SPR: + case CPU_EMR: + case CPU_GNR: ++ case CPU_SRF: + case CPU_ZEN: + case CPU_ZEN3: + case CPU_ZEN4: +diff --git a/x86/srf.c b/x86/srf.c +new file mode 100644 +index 0000000..790432e +--- /dev/null ++++ b/x86/srf.c +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2024, Intel Corporation ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright notice, ++ * this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Intel Corporation nor the names of its contributors ++ * may be used to endorse or promote products derived from this software ++ * without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* This file contains the bdw platform specific functions. */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../common/include/os/linux/perf_event.h" ++#include "../common/include/os/plat.h" ++#include "include/srf.h" ++ ++static plat_event_config_t s_srf_config[PERF_COUNT_NUM] = { ++ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES, 0x53, 0, 0, 0, "cpu_clk_unhalted.core" }, ++ { PERF_TYPE_RAW, 0x01B7, 0x53, 0x730000001, 0, 0, "off_core_response_0" }, ++ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES, 0x53, 0, 0, 0, "cpu_clk_unhalted.ref" }, ++ { PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS, 0x53, 0, 0, 0, "instr_retired.any" }, ++ { PERF_TYPE_RAW, 0x02B7, 0x53, 0x184000001, 0, 0, "off_core_response_1" } ++}; ++ ++static plat_event_config_t s_srf_ll = { ++ PERF_TYPE_RAW, 0x05D0, 0x53, LL_THRESH, 0, 1, "mem_trans_retired.latency_above_threshold" ++}; ++ ++void ++srf_profiling_config(perf_count_id_t perf_count_id, plat_event_config_t *cfg) ++{ ++ plat_config_get(perf_count_id, cfg, s_srf_config); ++} ++ ++void ++srf_ll_config(plat_event_config_t *cfg) ++{ ++ memcpy(cfg, &s_srf_ll, sizeof (plat_event_config_t)); ++} ++ ++int ++srf_offcore_num(void) ++{ ++ return (2); ++} +\ No newline at end of file +-- +2.41.0 + diff --git a/numatop.spec b/numatop.spec index 6bbad52..a5fecdd 100644 --- a/numatop.spec +++ b/numatop.spec @@ -3,7 +3,7 @@ Name: numatop Version: 2.4 -Release: 5%{?dist} +Release: 6%{?dist} Summary: Memory access locality characterization and analysis License: BSD @@ -44,6 +44,10 @@ Patch31: 0031-powerpc-util-fix-build-warning-cast-LHS-of-expressio.patch Patch32: 0032-common-os-map-Fix-overflow-warning.patch Patch33: 0033-Move-all-curses-calls-into-display-threads.patch Patch34: 0034-Avoid-race-on-submitting-display-commands.patch +Patch35: 0035-Remove-EMR-specific-events-configuration.patch +Patch36: 0036-Support-Intel-Granite-Rapids-platform.patch +Patch37: 0037-Support-Intel-Sierra-Forest-platform.patch + BuildRequires: autoconf @@ -97,6 +101,9 @@ autoreconf --force --install --symlink %changelog +* Thu Jan 2 2025 Pingfan Liu - 2.4.6 +- Add support for intel GNR and SRF + * Thu Jan 2 2025 Pingfan Liu - 2.4.5 - Fix ncures race issue