84 lines
2.0 KiB
Diff
84 lines
2.0 KiB
Diff
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From f1dadf9fbd33457b660884c6ce526315b1647e72 Mon Sep 17 00:00:00 2001
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From: Dapeng Mi <dapeng1.mi@linux.intel.com>
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Date: Tue, 15 Oct 2024 12:41:10 +0000
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Subject: [PATCH 2/3] Support Intel Granite Rapids platform
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Granite Rapids shares same perf events configuration with
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Sapphire rapids, directly reuse SPR's configuration to enable GNR's
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support.
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Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
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---
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x86/include/types.h | 3 ++-
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x86/plat.c | 7 +++++++
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2 files changed, 9 insertions(+), 1 deletion(-)
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diff --git a/x86/include/types.h b/x86/include/types.h
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index 1a0199a..814ef1c 100644
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--- a/x86/include/types.h
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+++ b/x86/include/types.h
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@@ -48,12 +48,13 @@ typedef enum {
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CPU_ICX,
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CPU_SPR,
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CPU_EMR,
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+ CPU_GNR,
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CPU_ZEN,
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CPU_ZEN3,
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CPU_ZEN4
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} cpu_type_t;
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-#define CPU_TYPE_NUM 16
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+#define CPU_TYPE_NUM 17
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typedef enum {
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PERF_COUNT_INVALID = -1,
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diff --git a/x86/plat.c b/x86/plat.c
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index d69544e..0eea408 100644
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--- a/x86/plat.c
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+++ b/x86/plat.c
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@@ -53,6 +53,7 @@ s_plat_profiling_config[CPU_TYPE_NUM] = {
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icx_profiling_config,
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spr_profiling_config,
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spr_profiling_config, /* EMR */
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+ spr_profiling_config, /* GNR */
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zen_profiling_config,
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zen3_profiling_config,
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zen4_profiling_config
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@@ -73,6 +74,7 @@ s_plat_ll_config[CPU_TYPE_NUM] = {
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icx_ll_config,
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spr_ll_config,
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spr_ll_config, /* EMR */
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+ spr_ll_config, /* GNR */
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zen_ll_config,
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zen_ll_config,
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zen_ll_config
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@@ -93,6 +95,7 @@ s_plat_offcore_num[CPU_TYPE_NUM] = {
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icx_offcore_num,
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spr_offcore_num,
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spr_offcore_num, /* EMR */
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+ spr_offcore_num, /* GNR */
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zen_offcore_num,
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zen_offcore_num,
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zen_offcore_num
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@@ -199,6 +202,9 @@ cpu_type_get(void)
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case 207:
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type = CPU_EMR;
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break;
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+ case 173:
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+ type = CPU_GNR;
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+ break;
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}
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} else if (family == 23) { /* Family 17h */
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type = CPU_ZEN;
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@@ -252,6 +258,7 @@ plat_detect(void)
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case CPU_ICX:
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case CPU_SPR:
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case CPU_EMR:
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+ case CPU_GNR:
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case CPU_ZEN:
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case CPU_ZEN3:
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case CPU_ZEN4:
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--
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2.41.0
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